background image

SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

1

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

2

D

– 55

°

C to 125

°

C Operating Temperature

Range, QML Processing

D

Processed to MIL-PRF-38535 (QML)

D

Performance

–  SMJ320C30-40 (50-ns Cycle)

40 MFLOPS

20 MIPS

–  SMJ320C30-50 (40-ns Cycle)

50 MFLOPS

25 MIPS

D

Two 1K-Word 

×

 32-Bit Single-Cycle

Dual-Access On-Chip RAM Blocks

D

Validated Ada Compiler

D

64-Word 

×

 32-Bit Instruction Cache

D

32-Bit Instruction and Data Words,

24-Bit Addresses

D

40 / 32-Bit Floating-Point / Integer Multiplier

and Arithmetic Logic Unit (ALU)

D

Parallel ALU and Multiplier Execution in a

Single Cycle

D

On-Chip Direct Memory Access (DMA)

Controller for Concurrent I/O and CPU

Operation

D

Integer, Floating-Point, and Logical

Operations

D

One 4K-Word 

×

 32-Bit Single-Cycle

Dual-Access On-Chip ROM Block

D

Two 32-Bit External Ports

(24- and 13-Bit Address)

D

Two Serial Ports With Support for

8- / 16- / 24- / 32-Bit Transfers

D

Packaging

–  181-Pin Grid Array Ceramic Package

(GB Suffix)

–  196-Pin Ceramic Quad Flatpack With

Nonconductive Tie-Bar (HFG Suffix)

D

SMD Approval for 40- and 50-MHz Versions

D

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Register Arithmetic Units (ARAUs)

D

Zero-Overhead Loops With Single-Cycle

Branches

D

Interlocked Instructions for

Multiprocessing Support

D

32-Bit Barrel Shifter

D

Eight Extended-Precision Registers

(Accumulators)

D

Two- and Three-Operand Instructions

D

Conditional Calls and Returns

D

Block Repeat Capability

D

Fabricated Using Enhanced Performance

Implanted CMOS (EPIC

t

) by Texas

Instruments (TI

t

)

D

Two 32-Bit Timers

description

The SMJ320C30 internal busing and special digital signal processor (DSP) instruction set has the speed and

flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions

in hardware that other processors implement through software or microcode. This hardware-intensive approach

provides performance previously unavailable on a single chip. The emphasis on total system cost has resulted

in a less expensive processor that can be designed into systems currently using costly bit-slice processors.

D

SMJ320C30-40: 50-ns single-cycle execution time, 5% supply

D

SMJ320C30-50: 40-ns single-cycle execution time, 5% supply

Copyright 

©

 1998, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC and TI are trademarks of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

2

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

A B C D E F G H J K L M N P R

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

181-Pin GB Grid Array Package

( BOTTOM VIEW )

196-Pin HFG Quad Flatpack

( TOP VIEW )

ÉÉ

ÉÉ

ÉÉÉ

ÉÉÉ

ÉÉ

ÉÉ

ÉÉ

ÉÉ

ÉÉ

ÉÉ

ÉÉ

ÉÉ

ÉÉÉ

ÉÉÉ

ÉÉ

ÉÉ

ÉÉ

ÉÉÉ

ÉÉÉ

ÉÉÉ

DVDD

DVSS

VDD

DVSS

DVDD

VSS

VSS

VDD

148

147

1

196

98

50

99

49

description (continued)

The SMJ320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single

cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,

internal dual-access memories, one DMA channel supporting concurrent I / O, and a short machine-cycle time.

High performance and ease of use are results of these features.

General-purpose applications are enhanced by the large address space, multiprocessor interface, internally

and externally generated wait states, two external interface ports, two timers, two serial ports, and multiple

interrupt structure. The SMJ320C30 supports a wide variety of system applications from host processor to

dedicated coprocessor.

High-level language support is implemented easily through a register-based architecture, large address space,

powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

3

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

functional block diagram

ÉÉÉ

ÉÉÉ

ÉÉÉ

ROM

Block

(4K 

×

 32)

Cache

(64 

×

 32)

RAM

Block 0

(1K 

×

 32)

RAM

Block 1

(1K 

×

 32)

RDY

HOLD

HOLDA

STRB

R / W

D31– D0

A23 – A0

RESET

IR

PC

CPU1

REG1

REG2

XRDY

MSTRB

IOSTRB

ÉÉÉ

XR / W

XD31–XD0

XA12 –XA0

MUX

40

32

32

32

32

32

32

32

24

24

24

24

BK

ARAU0

ARAU1

DISP0, IR0, IR1

Extended-

Precision

Registers

(R7–R0)

Auxiliary

Registers

(AR0 – AR7)

Other

Registers

(12)

40

40

40

40

Multiplier

32-Bit

Barrel

Shifter

ALU

DMA Controller

Global-Control

Register

Source-Address

Register

Destination-

Address

Register

Serial Port 0

Serial-Port-Control

Register

Receive/Transmit

(R/X) Timer Register

Data-Transmit

Register

Data-Receive

Register

FSX0

DX0

CLKX0

FSR0

DR0

CLKR0

Serial Port 1

ÉÉÉÉ

Data-Transmit

Register

Data-Receive

Register

FSX1

DX1

CLKX1

FSR1

DR1

CLKR1

Timer 0

Global-Control

Register

Timer-Period

Register

Timer-Counter

Register

TCLK0

Timer 1

Global-Control

Register

Timer-Period

Register

Timer-Counter

Register

TCLK1

Port Control

Primary-Control

Register

Expansion-Control

Register

Transfer-

Counter

Register

PDATA Bus

PADDR Bus

DDATA Bus

DADDR1 Bus

DADDR2 Bus

DMADATA Bus

DMAADDR Bus

24

40

32

32

24

24

32

24

INT(3 – 0)

IACK

MC / MP

XF(1,0)

VDD

IODVDD

ADVDD

PDVDD

DDVDD

MDVDD

VSS

DVSS

CVSS

IVSS

VBBP

VSUBS

X1

X2 / CLKIN

H1

H3

EMU(6 – 0)

RSV(10 – 0)

32

24

24

24

24

32

32

32

CPU2

32

32

40

40

Serial-Port-Control

Register

MUX

Controller

Peripheral Data Bus

Peripheral Address 

Bus

CPU1

REG1

REG2

MUX

Receive/Transmit

(R/X) Timer Register

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

4

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

memory map

Figure 1 shows the memory map for the SMJ320C30. See the 

TMS320C3x User’s Guide (literature number

SPRU031) for a detailed description of this memory mapping. Figure 2 shows the reset, interrupt, and trap

vector/branches memory-map locations. Figure 3 shows the peripheral bus memory-mapped registers.

Expansion-Bus

IOSTRB Active

(8K Words)

Reserved

(8K Words)

Expansion-Bus

IOSTRB Active

(8K Words)

Reserved

(8K Words)

Expansion-Bus

MSTRB Active

(8K Words)

Expansion-Bus

MSTRB Active

(8K Words)

Reset, Interrupt, Trap

Vectors, and Reserved

Locations (64) (External

STRB Active)

0h

03Fh

040h

7FFFFFh

800000h

801FFFh

Reserved

(8K Words)

802000h

803FFFh

804000h

805FFFh

806000h

807FFFh

808000h

Peripheral-Bus

Memory-Mapped

Registers

(6K Words Internal)

8097FFh

RAM Block 0

(1K Word Internal)

809800h

809BFFh

RAM Block 1

(1K Word Internal)

809C00h

809FFFh

External

STRB Active

(8M Words – 40K Words)

80A000h

0FFFFFFh

Reset, Interrupt,

Trap Vectors, and Reserved

Locations (192)

0h

0BFh

7FFFFFh

800000h

801FFFh

Reserved

(8K Words)

802000h

803FFFh

804000h

805FFFh

806000h

807FFFh

808000h

Peripheral-Bus

Memory-Mapped

Registers

(6K Words Internal)

8097FFh

RAM Block 0

(1K Word Internal)

809800h

809BFFh

RAM Block 1

(1K Word Internal)

809C00h

809FFFh

80A000h

0FFFFFFh

(a) Microprocessor Mode

(b) Microcomputer Mode

ROM

(Internal)

0C0h

0FFFh

External

STRB Active

(8M Words – 4K Words)

1000h

External

STRB Active

(8M Words – 40K Words)

External

STRB Active

(8M Words – 64 Words)

Figure 1. Memory Map

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

5

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

memory map (continued)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

1Fh

20h

3Bh

3Ch

3Fh

Reset

INT0

INT1

INT2

INT3

XINT0

RINT0

XINT1

RINT1

TINT0

TINT1

DINT

Reserved

TRAP 0

.

.

.

TRAP 27

Reserved

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

1Fh

20h

3Bh

3Ch

BFh

Reset

INT0

INT1

INT2

INT3

XINT0

RINT0

XINT1

RINT1

TINT0

TINT1

DINT

Reserved

TRAP 0

.

.

.

TRAP 27

Reserved

(a) Microprocessor Mode

(a) Microcomputer Mode

Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

6

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

memory map (continued)

FSX/DX/CLKX Serial Port 0 Control

FSR/DR/CLKR Serial Port 0 Control

Serial Port 0 R/X Timer Control

Serial Port 0 R/X Timer Counter

Serial Port 0 R/X Timer Period

Serial Port 0 Data Transmit

Serial Port 0 Data Receive

Serial Port 1 Global Control

FSX/DX/CLKX Serial Port 1 Control

FSR/DR/CLKR Serial Port 1 Control

Serial Port 1 R/X Timer Control

Serial Port 1 R/X Timer Counter

Serial Port 1 R/X Timer Period

Serial Port 1 Data Transmit

Serial Port 1 Data Receive

Expansion-Bus Control

Primary-Bus Control

DMA Global Control

DMA Source Address

DMA Destination Address

DMA Transfer Counter

Timer 0 Global Control

Timer 0 Counter

Timer 0 Period

Timer 1 Global Control

Timer 1 Counter

Timer 1 Period Register

Serial Port 0 Global Control

808000h

808004h

808006h

808008h

808020h

808024h

808028h

808030h

808034h

808038h

808040h

808042h

808043h

808044h

808045h

808046h

808048h

80804Ch

808050h

808052h

808053h

808054h

808055h

808056h

808058h

80805Ch

808060h

808064h

†Shading denotes reserved address locations

Figure 3. Peripheral Bus Memory-Mapped Registers

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

7

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

pin functions

This section gives signal descriptions for the SMJ320C30 devices in the microprocessor mode. The following

tables list each signal, the number of pins, type of operating mode(s) (that is, input, output, or high-impedance

state as indicated by I, O, or Z, respectively), and a brief function description. All pins labeled NC have special

functions and should not be connected by the user. A line over a signal name (for example, RESET) indicates

that the signal is active low (true at logic-0 level). The signals are grouped according to functions.

Pin Functions

PIN

TYPE†

DESCRIPTION

CONDITIONS

WHEN

NAME

QTY‡

TYPE†

DESCRIPTION

 WHEN

SIGNAL IS Z TYPE§

PRIMARY BUS INTERFACE

D31 – D0

32

I / O / Z

32-bit data port of the primary bus interface

S

H

A23 – A0

24

O / Z

24-bit address port of the primary bus interface

S

H

R

R / W

1

O / Z

Read / write for primary bus interface. R / W is high when a read is performed and low

when a write is performed over the parallel interface.

S

H

R

STRB

1

O / Z

External access strobe for the primary bus interface

S

H

RDY

1

I

Ready. RDY indicates that the external device is prepared for a primary bus interface

transaction to complete.

HOLD

1

I

Hold for primary bus interface. When HOLD is a logic low, any ongoing transaction

is completed. A23 – A0, D31 – D0, STRB, and R / W are in the high-impedance state

and all transactions over the primary bus interface are held until HOLD becomes a

logic high or the NOHOLD bit of the primary bus control register is set.

HOLDA

1

O / Z

Hold acknowledge for primary bus interface. HOLDA is generated in response to a

logic low on HOLD. HOLDA indicates that A23 – A0, D31 – D0, STRB, and R / W are

in the high-impedance state and that all transactions over the bus are held. HOLDA

is high in response to a logic high of HOLD or when the NOHOLD bit of the primary

bus control register is set.

S

EXPANSION BUS INTERFACE

XD31 – XD0

32

I / O / Z

32-bit data port of the expansion bus interface

S

R

XA12 – XA0

13

O / Z

13-bit address port of the expansion bus interface

S

R

XR / W

1

O / Z

Read / write signal for expansion bus interface. When a read is performed, XR / W is

held high; when a write is performed, XR / W is low.

S

R

MSTRB

1

O / Z

External memory access strobe for the expansion bus interface

S

IOSTRB

1

O / Z

External I / O access strobe for the expansion bus interface

S

XRDY

1

I

Ready signal. XRDY indicates that the external device is prepared for an expansion

bus interface transaction to complete.

CONTROL SIGNALS

RESET

1

I

Reset. When RESET is a logic low, the device is in the reset condition. When RESET

becomes a logic high, execution begins from the location specified by the reset vector.

INT3 – INT0

4

I

External interrupts

IACK

1

O / Z

Interrupt acknowledge. IACK is set to a logic high by the IACK instruction. IACK can

be used to indicate the beginning or end of an interrupt-service routine.

S

MC / MP

1

I

Microcomputer / microprocessor mode

XF1, XF0

2

I / O / Z

External flags. XF1 and XF0 are used as general-purpose I / Os or to support

interlocked processor instructions.

S

R

† I = input, O = output, Z = high-impedance state, NC = no connect

‡ For GB package

§ S = SHZ active, H = HOLD active, R = RESET active

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

8

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

Pin Functions (Continued)

PIN

TYPE†

DESCRIPTION

CONDITIONS

WHEN

NAME

QTY‡

TYPE†

DESCRIPTION

 WHEN

SIGNAL IS Z TYPE§

SERIAL PORT 0 SIGNALS

CLKX0

1

I / O / Z

Serial port 0 transmit clock. CLKX0 is the serial-shift clock for the serial port 0

transmitter.

S

R

DX0

1

I / O / Z

Data transmit output. Serial port 0 transmits serial data on DX0.

S

R

FSX0

1

I / O / Z

Frame synchronization pulse for transmit. The FSX0 pulse initiates the transmit-data

process over DX0.

S

R

CLKR0

1

I / O / Z

Serial port 0 receive clock. CLKR0 is the serial-shift clock for the serial port 0 receiver.

S

R

DR0

1

I / O / Z

Data receive. Serial port 0 receives serial data on DR0.

S

R

FSR0

1

I / O / Z

Frame synchronization pulse for receive. The FSR0 pulse initiates the receive-data

process over DR0.

S

R

SERIAL PORT 1 SIGNALS

CLKX1

1

I / O / Z

Serial port 1 transmit clock. CLKX1 is the serial-shift clock for the serial port 1

transmitter.

S

R

DX1

1

I / O / Z

Data transmit output. Serial port 1 transmits serial data on DX1.

S

R

FSX1

1

I / O / Z

Frame synchronization pulse for transmit. The FSX1 pulse initiates the transmit-data

process over DX1.

S

R

CLKR1

1

I / O / Z

Serial port 1 receive clock. CLKR1 is the serial-shift clock for the serial port 1 receiver.

S

R

DR1

1

I / O / Z

Data receive. Serial port 1 receives serial data on DR1.

S

R

FSR1

1

I / O / Z

Frame synchronization pulse for receive. The FSR1 pulse initiates the receive-data

process over DR1.

S

R

TIMER 0 SIGNALS

TCLK0

1

I / O / Z

Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an

output, TCLK0 outputs pulses generated by timer 0.

S

R

TIMER 1 SIGNALS

TCLK1

1

I / O / Z

Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an

output, TCLK1 outputs pulses generated by timer 1.

S

R

SUPPLY AND OSCILLATOR SIGNALS (see Note 1)

VDD

4

I

5-V supply¶

IODVDD

2

I

5-V supply¶

ADVDD

2

I

5-V supply¶

PDVDD

1

I

5-V supply¶

DDVDD

2

I

5-V supply¶

MDVDD

1

I

5-V supply¶

VSS

4

I

Ground

DVSS

4

I

Ground

CVSS

2

I

Ground

† I = input, O = output, Z = high-impedance state, NC = no connect

‡ For GB package

§ S = SHZ active, H = HOLD active, R = RESET active

¶ Recommended decoupling capacitor is 0.1 

µ

F.

NOTE 1: CVSS, VSS, and IVSS are on the same plane.

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

9

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

Pin Functions (Continued)

PIN

TYPE†

DESCRIPTION

CONDITIONS

WHEN

NAME

QTY‡

TYPE†

DESCRIPTION

 WHEN

SIGNAL IS Z TYPE§

SUPPLY AND OSCILLATOR SIGNALS (see Note 1) (CONTINUED)

IVSS

1

I

Ground

VBBP

1

NC

VBB pump oscillator output

VSUBS

1

I

Substrate pin. Tie to ground

X1

1

O

Output from the internal oscillator for the crystal. If a crystal is not used, X1 must

be left unconnected.

X2 / CLKIN

1

I

Input to the internal oscillator from the crystal or a clock

H1

1

O / Z

External H1 clock. H1 has a period equal to twice CLKIN.

S

H3

1

O / Z

External H3 clock. H3 has a period equal to twice CLKIN.

S

RESERVED (see Note 2)

EMU0 – EMU2

3

I

Reserved. Use pullup resistors to 5 V

EMU3

1

O / Z

Reserved

S

EMU4 / SHZ

1

I

Shutdown high impedance. When active, EMU4 / SHZ shuts down the SMJ320C30

and places all pins in the high-impedance state. EMU4 / SHZ is used for board-level

testing to ensure that no dual-drive conditions occur. CAUTION:  A low on SHZ

corrupts SMJ320C30 memory and register contents. Reset the device with SHZ

high to restore it to a known operating condition.

EMU5, EMU6

2

NC

Reserved

RSV0 – RSV4

5

I

Reserved. Tie pins directly to 5 V

RSV5 – RSV10

6

I / O

Reserved. Use pullups on each pin to 5 V

Locator

1

NC

Reserved

† I = input, O = output, Z = high-impedance state, NC = No Connect

‡ For GB package

§ S = SHZ active, H = HOLD active, R = RESET active

NOTES:

1. CVSS, VSS, IVSS are on the same plane.

2. The connections specified for the reserved pins must be followed. For best results, 18-k

– 22-k

 pullup resistors are

recommended. All 5-V supply pins must be connected to a common supply plane, and all ground pins must be connected to a

common ground plane.

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

10

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

Pin Assignments

PIN

PIN

PIN

PIN

PIN

NUMBER

NUMBER

NUMBER

NUMBER

NUMBER

GB

PKG

HFG

PKG

NAME

GB

PKG

HFG

PKG

NAME

GB

PKG

HFG

PKG

NAME

GB

PKG

HFG

PKG

NAME

GB

PKG

HFG

PKG

NAME

F15

G12

G13

G14

G15

H15

H14

J15

J14

J13

K15

J12

K14

L15

K13

L14

M15

K12

L13

M14

N15

M13

L12

N14

E5

G1

H2

H1

J1

J2

D15

E3

E1

F1

G4

F2

F4

C4

D5

A2

A3

B4

82

81

80

79

78

77

72

71

70

69

68

67

66

65

63

62

61

60

59

58

57

56

55

54

170

171

176

177

178

88

157

164

167

166

165

158

144

143

142

141

140

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

LOCATOR/NC

IACK

INT0

INT1

INT2

INT3

MC / MP

MSTRB

RDY

RESET

R / W

STRB

IOSTRB

D0

D1

D2

D3

D4

C5

D6

A4

B5

C6

A5

B6

D7

A6

C7

B7

A7

A8

B8

A9

B9

C9

A10

D9

B10

A11

C10

B11

A12

D10

C11

B12

F3

E2

D2

D1

P3

R2

N4

M5

R1

R3

M3

P1

L4

N2

N1

139

138

137

136

135

134

133

132

131

130

129

128

127

122

121

120

119

118

117

116

115

113

112

111

110

109

108

161

160

156

159

4

7

5

6

3

8

191

194

192

193

190

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

HOLD

HOLDA

XRDY

XR / W

FSR0

FSX0

CLKR0

CLKX0

DR0

DX0

FSR1

FSX1

CLKR1

CLKX1

DR1

P2

F14

E15

F13

E14

F12

C1

M6

B3

A1

C2

B1

P4

N5

G2

G3

D3

E4

H4

D8

M8

H12

N8

A13

A14

D11

C12

B13

A15

B15

C14

E12

D13

C15

D14

E13

J3

J4

K1

K2

L1

K3

195

83

84

85

86

87

155

11

145

146

152

151

9

10

169

168

154

153

123

73

74

124

27

107

106

105

104

103

102

95

94

93

92

91

90

89

179

180

181

182

183

184

DX1

EMU0

EMU1

EMU2

EMU3

EMU4 / SHZ

EMU5

EMU6

H1

H3

X1

X2 / CLKIN

TCLK0

TCLK1

XF0

XF1

V

BBP

V

SUBS

V

DD

}

V

DD

}

V

DD

}

V

DD

}

V

SS

w

XA0

XA1

XA2

XA3

XA4

XA5

XA6

XA7

XA8

XA9

XA10

XA11

XA12

RSV0

RSV1

RSV2

RSV3

RSV4

RSV5

L2

K4

M1

L3

M2

D12

H11

D4

E8

L8

M12

H5

M4

B2

P14

C8

H3

H13

R4

P5

N6

R5

P6

M7

R6

N7

P7

R7

P8

185

186

187

188

189

100

64

114

147

15

16

49

162

163

1

51

52

25

26

172

173

28

75

76

125

126

149

150

174

175

99

12

13

14

17

18

19

20

21

22

23

24

RSV6

RSV7

RSV8

RSV9

RSV10

ADV

DD

{

ADV

DD

{

DDV

DD

{

DDV

DD

{

IODV

DD

{

IODV

DD

{

IODV

DD

{

MDV

DD

{

MDV

DD

{

PDV

DD

{

CV

SS

w

CV

SS

w

V

DD

}

V

DD

}

V

DD

}

V

DD

}

V

SS

w

V

SS

w

V

SS

w

V

SS

w

V

SS

w

V

SS

w

V

SS

w

V

SS

w

V

SS

w

V

SUBS

XD0

XD1

XD2

XD3

XD4

XD5

XD6

XD7

XD8

XD9

XD10

R8

R9

P9

N9

R10

M9

P10

R11

N10

P11

R12

M10

N11

P12

R13

R14

M11

N12

P13

R15

P15

C3

C13

N3

N13

B14

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

53

2

101

50

98

148

196

96

97

XD11

XD12

XD13

XD14

XD15

XD16

XD17

XD18

XD19

XD20

XD21

XD22

XD23

XD24

XD25

XD26

XD27

XD28

XD29

XD30

XD31

DV

DD

DV

DD

DV

SS

W

DV

SS

W

DV

SS

W

DV

SS

W

IV

SS

w

IV

SS

w

† ADVDD, DDVDD, IODVDD, MDVDD, and PDVDD are on a common plane internal to the device.

‡ VDD is on a common plane internal to the device.

§ VSS, CVSS, and IVSS are on a common plane internal to the device.

¶ DVSS is on a common plane internal to the device.

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

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POST OFFICE BOX 1443 

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absolute maximum ratings over operating case temperature range (unless otherwise noted)

Supply voltage range, V

CC 

(see Note 3) 

– 0.3 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 

– 0.3 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage range, V

O

 

– 0.3 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous power dissipation (see Note 4) 

3.15 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating case temperature range, T

C

 – 

55

°

C to 125

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 – 

65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

3. All voltage values are with respect to VSS.

4. Actual operating power is less. This value was obtained under specially produced worst-case test conditions, which are not

sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both

primary and extension buses at the maximum rate possible. See normal (ICC) current specification in the electrical characteristics

table and also read 

Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020).

recommended operating conditions (see Note 5)

MIN

NOM‡

MAX

UNIT

VDD

Supply voltage (AVDD etc )

4 75

5

5 25

V

VDD

Supply voltage (AVDD, etc.)

4.75

5

5.25

V

VSS

Supply voltage (CVSS, etc.)

0

V

VIH

High-level input voltage

 2.1

VDD + 0.3*

V

VTH

High-level input voltage for CLKIN

3

VDD + 0.3*

V

VIL

Low-level input voltage

– 0.3*

0.8

V

IOH

High-level output current

– 300

µ

A

IOL

Low-level output current

2

mA

TC

Operating case temperature (see Note 6)

– 55

125

°

C

‡ All nominal values are at VDD = 5 V, TA (ambient-air temperature)= 25

°

C.

* This parameter is not production tested.

NOTE 5: All input and output voltage levels are TTL compatible.

NOTE 6: TC MAX at maximum rated operating conditions at any point on the case, TC MIN at initial (time zero) power up

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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POST OFFICE BOX 1443 

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electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)

(see Note 5)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

VDD = MIN, IOH = MAX

2.4

3

V

VOL

Low level output voltage

For XA12 – XA0

VDD = MIN, IOL = MAX

0.6*

V

VOL

Low-level output voltage

All others

VDD = MIN, IOL = MAX

0.3

0.6

V

IZ

High-impedance current

VDD = MAX

±

 20

µ

A

II

Input current

VI = VSS to VDD

±

 10

µ

A

IIP

Input current

Inputs with internal pullups (see Note 7)

– 600

20

µ

A

IIC

Input current ( X2 / CLKIN)

VI = VSS to VDD

±

 50

µ

A

ICC

Supply current

VDD = MAX, TA = 25

°

C,

200

600

mA

ICC

Supply current

DD

,

A

,

tc(CI) = MIN, See Note 8

200

600

mA

IDD

Supply current, standby; IDLE2, clock shut off

VDD = 5 V, TA = 25

°

C

50

mA

Ci

Input capacitance

15*

pF

Co

Output capacitance

20*

pF

Cx

X2 / CLKIN capacitance

25*

pF

† For conditions shown as MIN / MAX, use the appropriate value specified in recommended operating conditions.

‡ All typical values are at VDD = 5 V, TA = 25

°

C.

* This parameter is not production tested.

NOTES:

5. All input and output voltage levels are TTL compatible.

7. Pins with internal pullup devices: INT0 – INT3, MC / MP, RSV0 – RSV10. Although RSV0 – RSV10 have internal pullup devices,

external pullups should be used on each pin as identified in the pin function tables.

8. Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test

conditions, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a

checkerboard pattern to both primary and expansion buses at the maximum rate possible. See 

Calculation of TMS320C30 Power

Dissipation Application Report (literature number SPRA020).

PARAMETER MEASUREMENT INFORMATION

Tester Pin

Electronics

VLOAD

IOL

CT

IOH

Output

Under

Test

Where:

IOL

= 2 mA (all outputs)

IOH

= 300 

µ

A (all outputs)

VLOAD = Selected to emulate 50 

 termination (typical value = 1.54 V).

CT

= 80-pF typical load-circuit capacitance

Figure 4. Test Load Circuit

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

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PARAMETER MEASUREMENT INFORMATION

signal transition levels

TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.

Output transition times are specified as follows:

D

For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be

no longer high is 2 V and the level at which the output is said to be low is 1 V.

D

For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at

which the output is said to be high is 2 V.

0.6 V

1 V

2 V

2.4 V

Figure 5. TTL-Level Outputs

Transition times for TTL-compatible inputs are specified as follows:

D

For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is

2.1 V and the level at which the input is said to be low is 0.8 V.

D

For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is

0.8 V and the level at which the input is said to be high is 2.1 V.

0.8 V

2.1 V

Figure 6. TTL-Level Inputs

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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POST OFFICE BOX 1443 

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PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. To shorten

the symbols, some of the terminal names and other related terminology have been abbreviated as follows,

unless otherwise noted:

A

A23 – A0

IACK

IACK

ASYNCH

Asynchronous reset signals include XF0, XF1,

CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1,

DX1, FSX1, CLKR1, DR1, FSR1, TCLK0, and TCLK1

INT

INT3– INT0

CH

CLKX includes CLKX0 and CLKX1

IOS

IOSTRB

CI

CLKIN

(M)S

(M)STRB includes MSTRB and STRB

CONTROL

Control signals include STRB, MSTRB, and IOSTRB

RDY

RDY

D

D31 – D0

RESET

RESET

DR

Includes DR0, DR1

RW

R / W

DX

Includes DX0, DX1

S

STRB

FS

FSX/R includes FSX0, FSX1, FSR0, and FSR1

SCK

CLKX/R includes CLKX0, CLKX1,

CLKR0, and CLKR1

FSR

Includes FSR0, FSR1

TCLK

TCLK0, TCLK1

FSX

Includes FSX0, FSX1

(X)A

Includes A23 – A0 and XA12 – XA0

GPIO

General-purpose input/output; peripheral pins include

CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1,

and TCLK0/1

(X)D

Includes D31 – D0 and XD31 – XD0

H

Includes H1, H3

XF

XFx includes XF0 and XF1

H1

H1

XF0

XF0

H3

H3

XF1

XF1

HOLD

HOLD

(X)RDY

Includes RDY and XRDY

HOLDA

HOLDA

(X)RW

(X)R/W includes R/W and XR/W

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

15

POST OFFICE BOX 1443 

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X2/CLKIN, H1, and H3 timing

The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals. See the

RESET timing in Figure 20 for CLKIN to H1 and H3 delay specification.

timing parameters for X2/CLKIN, H1, H3 (see Note 5, Figure 7, Figure 8, and Figure 9)

NO †

’320C30-40

’320C30-50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

1

tf(CI)

Fall time, CLKIN

5*

5*

ns

2

tw(CIL)

Pulse duration, CLKIN low, tc(CI) = MIN (see Note 9)

9

7

ns

3

tw(CIH)

Pulse duration, CLKIN high, tc(CI) = MIN (see Note 9)

9

7

ns

4

tr(CI)

Rise time, CLKIN

5*

5*

ns

5

tc(CI)

Cycle time, CLKIN

25

303

20

303

ns

6

tf(H)

Fall time, H1 / H3

3

3

ns

7

tw(HL)

Pulse duration, H1 / H3 low (see Note 10)

P – 5

P – 5

ns

8

tw(HH)

Pulse duration, H1 / H3 high (see Note 10)

P – 6

P – 6

ns

9

tr(H)

Rise time, H1 / H3

3

3

ns

9.1

td(HL-HH) Delay time, from H1 low to H3 high or from H3 low to H1 high

0

4

0

4

ns

10

tc(H)

Cycle time, H1 / H3

50

606

40

606

ns

† Numbers in this column match those used in Figure 7, Figure 8, and Figure 9.

* This parameter is not production tested.

NOTES:

5. All input and output voltage levels are TTL compatible.

9. Rise and fall times, assuming a 35 – 65% duty cycle, are incorporated within this specification (see Figure 6).

10. P = tc(CI)

1

4

X2 / CLKIN

(1.5 V )

5

3

2

Figure 7. X2 / CLKIN Timing

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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POST OFFICE BOX 1443 

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timing parameters for X2/CLKIN, H1, H3 (see Note 5, Figure 7, Figure 8, and Figure 9) (continued)

H3

H1

6

9

9.1

9.1

6

9

10

8

7

8

7

10

Figure 8. H1 / H3 Timings

–60

–40

–20

0

20

40

60

80

100

120

140

Temperature – Degrees C

CLKIN to H1/H3 – ns

0

1

2

3

4

6

7

8

4.5 V Band

5.5 V Band

5

Figure 9. CLKIN to H1/H3 as a Function of Temperature

(Typical)

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

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memory read/write timing

The following table defines memory read/write timing parameters for (M)STRB.

timing parameters for a memory [(M)STRB = 0] read/write (see Figure 10 and Figure 11)

NO †

’320C30-40

’320C30-50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

11

td[H1L-(M)SL]

Delay time, H1 low to (M)STRB low

0*

10

0*

4

ns

12

td[H1L-(M)SH]

Delay time, H1 low to (M)STRB high

0*

6

0*

4

ns

13.1

td(H1H-RWL)

Delay time, H1 high to R / W low

0*

9

0*

7

ns

13.2

td[H1H-(X)RWL]

Delay time, H1 high to (X)R / W low

0*

13

0*

11

ns

14.1

td(H1L-A)

Delay time, H1 low to A valid

0*

11

0*

9

ns

14.2

td[H1L-(X)A]

Delay time, H1 low to (X)A valid

0*

9

0*

8

ns

15.1

tsu(D-H1L)R

Setup time, D valid before H1 low (read)

14

10

ns

15.2

tsu[(X)DR-H1L]R

Setup time, (X)D before H1 low (read)

16

14

ns

16

th[H1L-(X)D]R

Hold time, (X)D after H1 low (read)

0*

0*

ns

17.1

tsu(RDY-H1H)

Setup time, RDY before H1 high

8

6

ns

17.2

tsu[(X)RDY-H1H]

Setup time, (X)RDY before H1 high

9

8

ns

18

th[H1H-(X)RDY]

Hold time, (X)RDY after H1 high

0

0

ns

19

td[H1H-(X)RWH]W Delay time, H1 high to (X)R / W high (write)

9

7

ns

20

tv[H1L(X)D]W

Valid time, (X)D after H1 low (write)

17

14

ns

21

th[H1H-(X)D]W

Hold time, (X)D after H1 high (write)

0*

0*

ns

22.1

td(H1H-A)

Delay time, H1 high to A valid on back-to-back write cycles (write)

15

12

ns

22.2

td[H1H-(X)A]

Delay time, H1 high to (X)A valid on back-to-back write cycles (write)

21

18

ns

26

td[A-(X)RDY]

Delay time, (X)RDY from A valid

7*

6*

ns

† Numbers in this column match those used in Figure 10 and Figure 11.

* This parameter is not production tested.

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

18

POST OFFICE BOX 1443 

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memory read / write timing (continued)

11

13.1/13.2

14.1/14.2

12

15.1/15.2

16

18

17.1/17.2

H3

H1

(X)R/W

(X)A

(X)D

(X)RDY

(M)STRB

(see Note A)

26

NOTE A: (M)STRB remains low during back-to-back read operations.

Figure 10. Timing for Memory [(M)STRB = 0] Read

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

19

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

memory read / write timing (continued)

(X)RDY

(X)D

(X)A

(X)R / W

(M)STRB

H1

H3

19

21

22.1 / 22.2

17.1 / 17.2

18

14.1 / 14.2

12

26

20

13.1 / 13.2

11

Figure 11. Timing for Memory [(M)STRB = 0] Write

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

20

POST OFFICE BOX 1443 

 HOUSTON, TEXAS 77251–1443

memory read / write timing (continued)

The following table defines memory read timing parameters for IOSTRB.

timing parameters for a memory (IOSTRB = 0) read (see Figure 12)

NO †

’320C30-40

’320C30-50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

27

td(H1H-IOSL)

Delay time, H1 high to IOSTRB low

0*

9

0*

8

ns

28

td(H1H-IOSH)

Delay time, H1 high to IOSTRB high

0*

9

0*

8

ns

29

td[H1L-(X)RWH]

Delay time, H1 low to (X)R / W high

0*

9

0*

8

ns

30

td[H1L-(X)A]

Delay time, H1 low to (X)A valid

0*

9

0*

8

ns

31

tsu[(X)D-H1H]R

Setup time, (X)D before H1 high

13

11

ns

32

th[H1H-(X)D]R

Hold time, (X)D after H1 high

0*

0*

ns

33

tsu[(X)RDY-H1H]

Setup time, (X)RDY before H1 high

9

8

ns

34

th[H1H-(X)RDY]

Hold time, (X)RDY after H1 high

0

0

ns

† Numbers in this column match those used in Figure 12.

* This parameter is not production tested.

H3

H1

(X)R / W

(X)A

(X)D

(X)RDY

IOSTRB

27

28

30

31

32

34

33

29

Figure 12. Timing for Memory (IOSTRB = 0) Read

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DIGITAL SIGNAL PROCESSOR

 

 

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memory read / write timing (continued)

The following table defines memory write timing parameters for IOSTRB.

timing parameters for a memory (IOSTRB = 0) write (see Figure 13)

NO †

’320C30-40

’320C30-50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

27

td(H1H-IOSL)

Delay time, H1 high to IOSTRB low

0*

9

0*

8

ns

28

td(H1H-IOSH)

Delay time, H1 high to IOSTRB high

0*

9

0*

8

ns

29

td[H1L-(X)RWH]

Delay time, H1 low to (X)R / W high

0*

9

0*

8

ns

30

td[H1L-(X)A]

Delay time, H1 low to (X)A valid

0*

9

0*

8

ns

33

tsu[(X)RDY-H1H]

Setup time, (X)RDY before H1 high

9

8

ns

34

th[H1H-(X)RDY]

Hold time, (X)RDY after H1 high

0

0

ns

35

td(H1L-XRWL)

Delay time, H1 low to XR / W low

0*

13

0*

11

ns

36

tv[H1H(X)D]W

Valid time, (X)D after H1 high

25

20

ns

37

th[H1L-(X)D]W

Hold time, (X)D after H1 low

0

0

ns

† Numbers in this column match those used in Figure 13.

* This parameter is not production tested.

H3

H1

(X)R / W

(X)A

(X)D

(X)RDY

IOSTRB

27

28

33

34

36

37

29

30

35

Figure 13. Timing for Memory (IOSTRB = 0) Write

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

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XF0 and XF1 timing when executing LDFI or LDII

The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII.

timing parameters for XF0 and XF1 when executing LDFI or LDII (see Figure 14)

NO †

’320C30-40

’320C30-50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

38

td(H3H-XF0L)

Delay time, H3 high to XF0 low

13

12

ns

39

tsu(XF1-H1L)

Setup time, XF1 valid before H1 low

9

9

ns

40

th(H1L-XF1)

Hold time, XF1 after H1 low

0

0

ns

† Numbers in this column match those used in Figure 14.

H3

H1

(M)STRB

(X)R / W

(X)A

(X)D

(X)RDY

XF0

XF1

Fetch

LDFI or LDII

Decode

Read

Execute

38

39

40

Figure 14. Timing for XF0 and XF1 When Executing LDFI or LDII

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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XF0 timing when executing STFI and STII

The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.

timing parameters for XF0 when executing STFI or STII (see Figure 15)

NO †

’320C30 - 40

’320C30 - 50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

41

td(H3H-XF0H) Delay time, H3 high to XF0 high

13

12

ns

† The number in this column matches that used in Figure 15.

H3

H1

(M)STRB

(X)R/W

(X)A

(X)D

(X)RDY

XF0

Fetch 

STFI or STII

Read

Execute

41

Decode

Figure 15. Timing for XF0 When Executing an STFI or STII

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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XF0 and XF1 timing when executing SIGI

The following table defines the timing parameters for the XF0 and XF1 pins during execution of SIGI.

timing parameters for XF0 and XF1 when executing SIGI (see Figure 16)

NO †

’320C30 - 40

’320C30 - 50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

41.1

td(H3H-XF0L)

Delay time, H3 high to XF0 low

13

12

ns

42

td(H3H-XF0H) Delay time, H3 high to XF0 high

13

12

ns

43

tsu(XF1-H1L)

Setup time, XF1 valid before H1 low

9

9

ns

44

th(H1L-XF1)

Hold time, XF1 after H1 low

0

0

ns

† Numbers in this column match those used in Figure 16.

H3

H1

Fetch

SIGI

Decode

Read

Execute

XF0

XF1

43

44

41.1

42

Figure 16. Timing for XF0 and XF1 When Executing SIGI

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DIGITAL SIGNAL PROCESSOR

 

 

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loading when XFx is configured as an output

The following table defines the timing parameter for loading the XF register when the XFx pin is configured as

an output.

timing parameters for loading the XFx register when configured as an output pin (see Figure 17)

NO †

’320C30 - 40

’320C30 - 50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

45

tv(H3H-XF)

Valid time, H3 high to XF valid

13

12

ns

† The number in this column matches that used in Figure 17.

Fetch Load

Instruction

Decode

Read

Execute

H3

H1

OUTXF Bit

XFx

1 or 0

45

NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register.

Figure 17. Timing for Loading XFx Register When Configured as an Output Pin

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DIGITAL SIGNAL PROCESSOR

 

 

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changing XFx from an output to an input

The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin.

timing parameters of XFx changing from output to input mode (see Figure 18)

NO †

’320C30 - 40

’320C30 - 50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

46

td(H3H-XFx)

Delay time, XFx after H3 high

13*

12*

ns

47

tsu(XFx-H1L)

Setup time, XFx before H1 low

9

9

ns

48

th(H1L-XFx)

Hold time, XFx after H1 low

0

0

ns

† Numbers in this column match those used in Figure 18.

* This parameter is not production tested.

Execute

Load of IOF

H3

H1

XFx

INXFx Bit

(see Note A)

I/OXFx Bit

(see Note A)

46

47

48

Data

Sampled

Data 

Seen

Output

Value on

Terminal

Seen in IOF

Synchronizer

Delay

Buffers Go

From Output

to Input

NOTE A: I / OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register depending on

whether XF0 or XF1, respectively, is being affected.

Figure 18. Timing for Change of XFx From Output to Input Mode

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 – REVISED FEBRUARY 1999

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POST OFFICE BOX 1443 

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changing XFx from an input to an output

The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.

timing parameters of XFx changing from input to output mode (see Figure 19)

NO †

’320C30 - 40

’320C30 - 50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

49

td(H3H-XFIO)

Delay time, H3 high to XF switching from input to output

17

17

ns

† The number in this column matches that used in Figure 19.

Execution of

Load of IOF

49

H3

H1

I/OXFx Bit

(see Note A)

XFx

(see Note A)

NOTE A: I / OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register depending on

whether XF0 or XF1, respectively, is being affected.

Figure 19. Timing for Change of XFx From Input to Output Mode

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DIGITAL SIGNAL PROCESSOR

 

 

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reset timing

RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings

are met, the exact sequence shown in Figure 20 occurs; otherwise, an additional delay of one clock cycle can

occur. R / W and XR / W are in the high-impedance state during reset and can be provided with a resistive pullup,

nominally 18 k

 to 22 k

, to prevent spurious writes from occurring. The asynchronous reset signals include

XF0/1, CLKX0/1, DX0/1, FSX0/1, CLKR0/1, DR0/1, FSR0/1, and TCLK0/1. HOLD is an asynchronous input and

can be asserted during reset.

Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states

and, therefore, results in slow external accesses until these registers are initialized.

timing parameters for RESET [P = t

c(CI)

] (see Figure 9 and Figure 20)

NO

’320C30 - 40

’320C30 - 50

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

50

tsu(RESET)

Setup time, RESET before CLKIN low

10

P*

10

P*

ns

51

td(CLKINH-H1H)

Delay time, CLKIN high to H1 high†

2

14

2

10

ns

52

td(CLKINH-H1L)

Delay time, CLKIN high to H1 low†

2

14

2

10

ns

53

tsu(RESETH-H1L)

Setup time, RESET high before H1 low after ten H1 clock

cycles

9

7

ns

54

td(CLKINH-H3L)

Delay time, CLKIN high to H3 low†

2

14

2

10

ns

55

td(CLKINH-H3H)

Delay time, CLKIN high to H3 high†

2

14

2

10

ns

56

tdis(H1H-XD)

Disable time, H1 high to (X)D high-impedance state

15*

12*

ns

57

tdis(H3H-XA)

Disable time, H3 high to (X)A high-impedance state

9*

8*

ns

58

td(H3H-CONTROLH)

Delay time, H3 high to control signals high

9*

8*

ns

59

td(H1H-IACKH)

Delay time, H1 high to IACK high

9*

8*

ns

60

tdis(RESETL-ASYNCH)

Disable time, RESET low to asynchronous reset signals in

the high-impedance state

21*

17*

ns

† See Figure 9 for temperature dependence for the 40-MHz SMJ320C30.

* This parameter is not production tested.

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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reset timing (continued)

IACK

50

51

52

54

56

53

57

55

58

59

60

CLKIN

H1

H3

(X)D

(see Note A)

(X)A

(see Note B)

Control Signals

(see Note C)

Asynchronous

Reset Signals

(see Note D)

RESET

Ten H1 Clock Cycles

NOTES: A. In this diagram X(D) includes D31 – D0 and XD31 – XD0.

B. In this diagram, (X)A includes A23 – A0 and XA12 – XA0.

C. Control signals include STRB, MSTRB, and IOSTRB.

D. Asynchronous reset signals include XF1, XF0, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1, DX1, FSX1, CLKR1, DR1, FSR1,

TCLK0, and TCLK1.

E. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In micromputer mode, the reset

vector is fetched twice, with no software wait states.

Figure 20. Timing for Reset  [P = t

c(Cl)

]

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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interrupt-response timing

The following table defines the timing parameters for the INT signals.

timing parameters for INT3– INT0 [Q = t

c(H)

] (see Figure 21)

NO

’320C30 - 40

’320C30 - 50

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

61

tsu(INT)

Setup time, INT3 – INT0 before H1 low

13

10

ns

62

tw(INT)

Pulse duration, INT3 – INT0, to assure only one interrupt seen

Q

< 2Q*

Q

< 2Q*

ns

* This parameter is not production tested.

The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The

SMJ320C30 interrupts

 are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.

Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA

respond to detected interrupts on instruction-fetch boundaries only.

For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held

to:

D

A minimum of one H1 falling edge

D

No more than two H1 falling edges

The SMJ320C30 can accept an interrupt from the same source every two H1 clock cycles.

If the specified timings are met, the exact sequence shown in Figure 21 occurs; otherwise, an additional delay

of one clock cycle is possible.

Reset or

Interrupt

Vector

Read

H3

H1

INT3 – INT0

Pins

INT3 – INT0

Flag

Data

Vector Address

First

 Instruction

Address

61

Fetch First

Instruction of

Service Routine

62

Addr

Figure 21. Timing for INT3 – INT0 Response [Q = t

c(H)

]

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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interrupt-acknowledge timing

The IACK output goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and

goes inactive at the first half-cycle (H1 rising) of the read phase of the IACK instruction.

The following table defines the timing parameters for the IACK signal.

timing parameters for IACK (see Figure 22)

NO †

’320C30 - 40

’320C30 - 50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

63

td(H1H-IACKL)

Delay time, H1 high to IACK low

9

7

ns

64

td(H1H-IACKH)

Delay time, H1 high to IACK high

9

7

ns

† Numbers in this column match those used in Figure 22.

H3

H1

IACK

Address

Data

63

64

Fetch IACK

Instruction

IACK

Data Read

Figure 22. Timing for Interrupt-Acknowledge (IACK)

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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serial-port timing parameters (see Figure 23 and Figure 24)

NO

CLOCK

’320C30 - 40

’320C30 - 50

UNIT

NO.

SOURCE

MIN

MAX

MIN

MAX

UNIT

65

td(H1-SCK)

Delay time, H1 high to

internal CLKX / R

13

10

ns

66

t (SCK)

Cycle time,

CLKX / R ext

tc(H)

×

2.5*

tc(H)

×

2.6*

ns

66

tc(SCK)

y

,

CLKX / R

CLKX / R int

tc(H)

×

2

tc(H)

×

232*

tc(H)

×

2

tc(H)

×

232*

ns

67

t (SCK)

Pulse

duration,

CLKX / R ext

tc(H)+12*

tc(H)+10*

ns

67

tw(SCK)

,

CLKX / R

high / low

CLKX / R int

[tc(SCK) / 2] –15

[tc(SCK) / 2]+5

[tc(SCK) / 2] –5

[tc(SCK) / 2]+5

ns

68

tr(SCK)

Rise time, CLKX / R

7*

6*

ns

69

tf(SCK)

Fall time, CLKX / R

7*

6*

ns

70

td(DX)

Delay time,

CLKX to DX

CLKX ext

30

24

ns

70

 td(DX)

CLKX to DX

valid

CLKX int

17

16

ns

71

t

(DR)

Setup time,

DR before

CLKR ext

9

9

ns

71

tsu(DR)

DR before

CLKR low

CLKR int

21

17

ns

72

th(DR)

Hold time,

DR from

CLKR ext

9

7

ns

72

th(DR)

DR from

CLKR low

CLKR int

0

0

ns

73

td(FSX)

Delay time,

CLKX to

CLKX ext

27

22

ns

73

td(FSX)

internal FSX

high / low

CLKX int

15

15

ns

74

t

(FSR)

Setup time,

FSR before

CLKR ext

9

7

ns

74

tsu(FSR)

FSR before

CLKR low

CLKR int

9

7

ns

75

th(FS)

Hold time,

FSX / R input

CLKX / R ext

9

7

ns

75

th(FS)

from

CLKX / R low

CLKX / R int

0

0

ns

76

t

(FSX)

Setup time,

external FSX

CLKX ext

– [tc(H) – 8]

[tc(SCK) / 2] –10*

– [tc(H) – 8]

[tc(SCK) / 2] –10*

ns

76

tsu(FSX)

before CLKX

high

CLKX int

– [tc(H) – 21]

tc(SCK) / 2*

– [tc(H) – 21]

tc(SCK) / 2*

ns

77

td(CH DX)V

Delay time,

CLKX to first

DX bit FSX

CLKX ext

30

24

ns

77

td(CH-DX)V

DX bit, FSX

precedes

CLKX high

CLKX int

18

14

ns

78

td(FSX-DX)V

Delay time, FSX to first DX

bit, CLKX precedes FSX

30

24

ns

79

tdDXZ

Delay time, CLKX high to DX

high impedance following last

data bit

17*

14*

ns

* This parameter is not production tested.

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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33

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serial-port timing parameters (continued)

Unless otherwise indicated, the data-rate timings shown in Figure 23 and Figure 24 are valid for all serial-port

modes, including handshake. See serial-port timing parameter tables.

Timing diagrams shown in Figure 23 and Figure 24 show operations with the serial port global-control register

bits CLKXP = CLKRP = FSXP = FSRP = 0.

Timing diagrams shown in Figure 23 and Figure 24 depend upon the length of the serial-port word, n, where

n = 8, 16, 24, or 32 bits, respectively.

FSX (ext)

FSX  (int)

FSR

DR

DX

CLKX/ R

H1

72

68

69

71

76

75

73

75

74

73

70

65

65

79

Bit n – 1

Bit n – 2

Bit 0

Bit n – 2

66

67

67

Bit n – 1

Figure 23. Serial-Port Timing for Fixed-Data-Rate Mode

CLKX / R

FSX (int)

FSX (ext)

DX

FSR

DR

Bit n – 1

Bit n – 2

Bit n – 3

Bit 0

Bit n – 1

78

73

76

70

77

79

71

68

72

75

Bit n – 2

Bit n – 3

NOTE A: Timings not expressly specified for variable-data-rate mode are the same as those for fixed-data-rate mode.

Figure 24. Serial-Port Timing for Variable-Data-Rate Mode

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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HOLD timing

HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings

are met, the exact sequence shown in Figure 25 occurs; otherwise, an additional delay of one clock cycle is

possible.

The “timing parameters for HOLD / HOLDA” table defines the timing parameters for the HOLD and HOLDA

signals.

The NOHOLD bit of the primary bus control register overrides the HOLD signal. When this bit is set, the device

comes out of hold and prevents future hold cycles.

Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a

read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, allowing

the processor to continue until a second write is encountered.

HOLD / HOLDA timing (see Figure 25)

NO †

’320C30 - 40

’320C30 - 50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

80

tsu(HOLD)

Setup time, HOLD before H1 low

13

10

ns

81

tv(HOLDA)

Valid time, HOLDA after H1 low

0*

9

0*

7

ns

82

tw(HOLD)

Pulse duration, HOLD low

2tc(H)

2tc(H)

ns

83

tw(HOLDA)

Pulse duration, HOLDA low

tc(H) – 5*

tc(H) – 5*

ns

84

td(H1L-SH)H

Delay time, H1 low to STRB high for a HOLD

0*

9*

0*

7*

ns

85

tdis(H1L-S)

Disable time, H1 low to STRB high impedance

0*

9*

0*

8*

ns

86

ten(H1L-S)

Enable time, H1 low to STRB active

0*

9*

0*

7*

ns

87

tdis(H1L-RW) Disable time, H1 low to R / W high impedance

0*

9*

0*

8*

ns

88

ten(H1L-RW)

Enable time, H1 low to R / W active

0*

9*

0*

7*

ns

89

tdis(H1L-A)

Disable time, H1 low to address high impedance

0*

9*

0*

8*

ns

90

ten(H1L-A)

Enable time, H1 low to address valid

0*

13*

0*

12*

ns

91

tdis(H1H-D)

Disable time, H1 high to data high impedance

0*

12*

0*

8*

ns

† Numbers in this column are used in Figure 25.

* This parameter is not production tested.

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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HOLD / HOLDA timing (continued)

H3

H1

HOLD

HOLDA

(see Note A)

(M)STRB

and

STRB

R / W

A

D

80

80

81

81

85

87

86

88

90

89

91

84

Write Data

82

83

NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low through one H1 cycle after HOLD returns to high.

Figure 25. Timing for HOLD/HOLDA

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DIGITAL SIGNAL PROCESSOR

 

 

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general-purpose I/O timing

Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The contents of the

internal-control registers associated with each peripheral define the modes for these pins.

peripheral pin I/O timing

The following table defines peripheral pin general-purpose I/O timing parameters.

timing parameters for peripheral pin general-purpose I/O (see Note 11 and Figure 26)

NO †

’320C30 - 40

’320C30 - 50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

92

tsu(GPIOH1L) Setup time, general-purpose input before H1 low

10*

9*

ns

93

th(GPIOH1L)

Hold time, general-purpose input after H1 low

0*

0*

ns

94

td(GPIOH1H)

Delay time, general-purpose output after H1 high

13*

10*

ns

† Numbers in this column are used in Figure 26.

* This parameter is not production tested.

NOTE 11: Peripheral pins include CLKX0 / 1, CLKR0 / 1, DX0 / 1, DR0 / 1, FSX0 / 1, FSR0 / 1, and TCLK0 / 1. The modes of these pins are defined

by the contents of internal control registers associated with each peripheral.

H1

H3

94

92

93

Peripheral

Pin

94

Figure 26. Timing for Peripheral Pin General-Purpose I/O

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DIGITAL SIGNAL PROCESSOR

 

 

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changing the peripheral pin I/O modes

The following tables show the timing parameters for changing the peripheral pin from a general-purpose output

pin to a general-purpose input pin and the reverse.

timing parameters for peripheral pin changing from general-purpose output to input mode

 (see Note 12 and Figure 27)

NO †

’320C30 - 40

’320C30 - 50

UNIT

NO.†

MIN

MAX

MIN

MAX

UNIT

95

th(H1H)

Hold time after H1 high

13

10

ns

96

tsu(GPIOH1L)

Setup time, peripheral pin before H1 low

9

9

ns

97

th(GPIOH1L)

Hold time, peripheral pin after H1 low

0

0

ns

† Numbers in this column are used in Figure 27.

NOTE 12: Peripheral pins include CLKX0 / 1, CLKR0 / 1, DX0 / 1, DR0 / 1, FSX0 / 1, FSR0 / 1, and TCLK0 / 1. The modes of these pins are defined

by the contents of internal control registers associated with each peripheral.

97

96

95

Value on

Terminal Seen in

Peripheral

Control Register

Synchronizer Delay

Buffers Go

From Output to

Input

Execute Store

of Peripheral

Control

Register

Data Bit

I/O

Control Bit

H1

H3

Output

Data

Seen

Data Sampled

Peripheral

Pin

Figure 27. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

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timing parameters for peripheral pin changing from general-purpose input to output mode

(see Figure 28)

NO

’320C30 - 40

’320C30 - 50

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

98

td(GPIOH1H)

Delay time, H1 high to peripheral pin switching from input to output

13

10

ns

H1

H3

Execution of Store of

Peripheral Control

Register

98

I / O

Control

Bit

Peripheral

Pin

Figure 28. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode

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DIGITAL SIGNAL PROCESSOR

 

 

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timer pin (TCLK0 and TCLK1) timing

Valid logic-level periods and polarity are specified by the contents of the internal control registers.

The following tables define the timing parameters for the timer pin.

timing parameters for timer pin (TCLK0 and TCLK1) (see Figure 29)

NO

’320C30 - 40‡

’320C30 - 50‡

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

99

tsu(TCLK-H1L)

Setup time,

TCLK ext

before H1 low

TCLK ext

10

8

ns

100

th(TCLK-H1L)

Hold time,

TCLK ext after

H1 low

TCLK ext

0

0

ns

101

td(TCLK-H1H)

Delay time, H1

high to TCLK

int valid

TCLK int

9

9

ns

102

t (TCLK)

Cycle time,

TCLK ext

tc(H) 

×

 2.6*

tc(H) 

×

 2.6*

ns

102

tc(TCLK)

y

,

TCLK

TCLK int

tc(H) 

×

 2

tc(H) 

×

 232*

tc(H) 

×

 2

tc(H) 

×

 232*

ns

103

t (TCLK)

Pulse duration,

TCLK ext

tc(H) + 12*

tc(H) + 10*

ns

103

tw(TCLK)

,

TCLK high / low

TCLK int

[tc(TCLK) / 2] –5

[tc(TCLK) / 2]+5

[tc(TCLK) / 2] –5

[tc(TCLK) / 2]+5

ns

† Numbers in this column are used in Figure 29.

‡ Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous

input clock.

* This parameter is not production tested.

timer pin (TCLK0 and TCLK1) timing (continued)

101

101

100

H1

H3

99

Timer

Pin

103

102

NOTE A: Period and polarity of valid logic level are specified by contents of internal control registers.

Figure 29. Timing for Timer Pin

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 –  REVISED FEBRUARY 1999

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SHZ pin timing

The following table defines the timing parameter for the SHZ pin.

timing parameters for SHZ pin (see Figure 30)

NO.†

’320C30 -40

’320C30 -50

UNIT

MIN

MAX

104

tdis(SHZ)

Disable time, SHZ low to all O, I / O high impedance

0*

3P + 15*

ns

105

ten(SHZ)

Enable time, SHZ high to all O, I / O active

0*

2P*

ns

† Numbers in this column are used in Figure 30.

* This parameter is not production tested.

104

H1

H3

All I / Os

SHZ

(see

Note A)

105

1.5

NOTE A: Enabling SHZ destroys SMJ320C30 register and memory contents. Assert SHZ and reset the SMJ320C30 to restore it to a known

condition.

Figure 30. Timing for SHZ

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 –  REVISED FEBRUARY 1999

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SMJ320C30 part order information

DEVICE

TECHNOLOGY

POWER

SUPPLY

OPERATING

FREQUENCY

PACKAGE TYPE

PROCESSING

LEVEL

SMJ320C30GBM40

0.7-

µ

m CMOS

5 V 

±

5%

40 MHz

Ceramic 181-pin PGA

QML

SM320C30GBM40

0.7-

µ

m CMOS

5 V 

±

5%

40 MHz

Ceramic 181-pin PGA

Standard

SMJ320C30HFGM40

0.7-

µ

m CMOS

5 V 

±

5%

40 MHz

Ceramic 196-pin quad flatpack with

nonconductive tie bar

QML

SM320C30HFGM40

0.7-

µ

m CMOS

5 V 

±

5%

40 MHz

Ceramic 196-pin quad flatpack with

nonconductive tie bar

Standard

5962–9052604MXA

0.7-

µ

m CMOS

5 V 

±

5%

40 MHz

Ceramic 181-pin PGA

DESC SMD

5962–9052604MUA

0.7-

µ

m CMOS

5 V 

±

5%

40 MHz

Ceramic 196-pin quad flatpack with

nonconductive tie bar

DESC SMD

SMJ320C30GBM50

0.7-

µ

m CMOS

5 V 

±

5%

50 MHz

Ceramic 181-pin PGA

QML

SM320C30GBM50

0.7-

µ

m CMOS

5 V 

±

5%

50 MHz

Ceramic 181-pin PGA

Standard

SMJ320C30HFGM50

0.7-

µ

m CMOS

5 V 

±

5%

50 MHz

Ceramic 196-pin quad flatpack with

nonconductive tie bar

QML

SM320C30HFGM50

0.7-

µ

m CMOS

5 V 

±

5%

50 MHz

Ceramic 196-pin quad flatpack with

nonconductive tie bar

Standard

5962–9052605MXA

0.7-

µ

m CMOS

5 V 

±

5%

50 MHz

Ceramic 181-pin PGA

DESC SMD

5962–9052605MUA

0.7-

µ

m CMOS

5 V 

±

5%

50 MHz

Ceramic 196-pin quad flatpack with

nonconductive tie bar

DESC SMD

SMJ

320

C

30

GB

M

40

PREFIX

SMJ =

MIL-STD-38535 (QML)

SM

=

Standard Processing

DEVICE FAMILY

320 = SMJ320 Family

TECHNOLOGY

C = CMOS

SPEED RANGE

40 = 40 MHz

50 = 50 MHz

TEMPERATURE RANGE

M = – 55

°

C to 125

°

C

L =

0

°

C to 70

°

C

PACKAGE TYPE

GB

=

181-Pin Grid Array (PGA) Ceramic

Package

HFG =

196-Pin Ceramic Quad Flatpack with a

nonconductive tie bar

KGD =

Known Good Die

DEVICE

30 = ’320C30

Figure 31. SMJ320C30 Device Nomenclature

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SMJ320C30

DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 –  REVISED FEBRUARY 1999

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MECHANICAL DATA

HFG (S-CQFP-F196)   

CERAMIC QUAD FLATPACK WITH TIE BAR

4040231-6 / F 04/96

2.505 (63,63)

2.485 (63,12)

“C”

“B”

0.004 (0,10)

0.105 (2,67) MAX

DETAIL “C”

0.008 (0,20)

0.002 (0,05)

0.130 (3,30) MAX

0.014 (0,36)

0.018 (0,46) MAX

1.365 (34,67)

1.325 (33,66)

196

1

148

49

“A”

50

98

DETAIL “B”

Braze

8 Places

1.150 (29,21)

0.010 (0,25)

0.006 (0,15)

DIA 4 Places

DETAIL “A”

196 



0.061 (1,55)

0.059 (1,50)

99

147

1.200 (30,48) TYP

0.225 (5,72)

1.710 (43,43)

1.690 (42,93)

0.600 (15,20) TYP

0.030 (0,76)

0.040 (1,02)

0.020 (0,51) MAX

0.175 (4,45)

0.025 (0,64)

1.3

PARAMETER

Thermal Resistance Characteristics

°

C/W

28.9

R

θ

JC

R

θ

JA

Tie Bar Width

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Ceramic quad flatpack with flat leads brazed to nonconductive tie-bar carrier

D. This package can be hermetically sealed with a metal lid.

E. The terminals will be gold plated.

F. Falls within JEDEC MO -113 AB

The above data applies to the SMJ320C30 196-pin QFP.

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DIGITAL SIGNAL PROCESSOR

 

 

SGUS014F – FEBRUARY 1991 –  REVISED FEBRUARY 1999

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POST OFFICE BOX 1443 

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MECHANICAL DATA

GA-GB (S-CPGA-P15 X 15)   

CERAMIC PIN GRID ARRAY PACKAGE

4040114-8 / C 04/96

Down

Cavity

Up

Cavity

Down

Cavity

Cavity

Up

Outline

Small

Outline

Large

MAXIMUM PINS WITHIN MATRIX – 225

C1

0.025 (0,63)

0.060 (1,52)

0.060 (1,52)

0.040 (1,02)

C

B1

0.095 (2,41)

0.205 (5,21)

0.205 (5,21)

0.110 (2,79)

B

A1

1.480 (37,59)

1.535 (38,99)

1.590 (40,38)

DIM

MIN

MAX

Notes

1.540 (39,12)

A

A or A1 SQ

4 Places

DIA TYP

1.400 (35,56) TYP

0.050 (1,27) DIA

0.120 (3,05)

0.016 (0,41)

0.022 (0,55)

0.140 (3,56)

B or B1

C or C1

J

H

G

F

E

D

C

A

B

1 2 3 4 5 6 7 8 9

K

10

L

11 12

M

13

N

14

P

0.100 (2,54)

15

R

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Index mark may appear on top or bottom depending on package vendor.

D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within

0.030 (0,76) diameter relative to the edges of the ceramic.

E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.

F. The pins can be gold plated or solder dipped.

G. Falls within MIL-STD-1835 CMGA7-PN and CMGA19-PN and JEDEC MO-067AG and MO-066AG, respectively

1.1

PARAMETER

Thermal Resistance Characteristics

°

C/W

26.6

R

θ

JC

R

θ

JA

The above data applies to the SMJ320C30 181-pin PGA.

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

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Copyright 

©

 1999, Texas Instruments Incorporated