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SN54LV74, SN74LV74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

 

 

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

EPIC

 (Enhanced-Performance Implanted

CMOS) 2-

µ

 Process

D

Typical V

OLP

 (Output Ground Bounce)

< 0.8 V at V

CC

, T

A

 = 25

°

C

D

Typical V

OHV

 (Output V

OH

 Undershoot)

> 2 V at V

CC

, T

A

 = 25

°

C

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA

Per JEDEC Standard JESD-17

D

Package Options Include Plastic

Small-Outline (D), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW),

Ceramic Flat (W) Packages, Chip Carriers

(FK), and (J) 300-mil DIPs

     

description

These dual positive-edge-triggered D-type flip-

flops are designed for 2.7-V to 5.5-V V

CC

operation.

A low level at the preset (PRE) or clear (CLR)

inputs sets or resets the outputs regardless of the

levels of the other inputs. When PRE and CLR are

inactive (high), data at the data (D) inputs meeting

the setup-time requirements is transferred to the

outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly

related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed

without affecting the levels at the outputs.

The SN74LV74 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LV74 is characterized for operation over the full military temperature range of –55

°

C to 125

°

C. The

SN74LV74 is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 1996, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1CLR

1D

1CLK

1PRE

1Q

1Q

GND

V

CC

2CLR

2D

2CLK

2PRE

2Q

2Q

SN54LV74 . . . J  OR  W  PACKAGE

SN74LV74 . . . D, DP, OR PW PACKAGE

(TOP VIEW)

3

2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

2D

NC

2CLK

NC

2PRE

1CLK

NC

1PRE

NC

1Q

1D

1CLR

NC

2Q

2Q

V

2CLR

1Q

GND

NC

SN54LV74 . . . FK PACKAGE

(TOP VIEW)

CC

NC – No internal connection

EPIC is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SN54LV74, SN74LV74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

 

 

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H†

H†

H

H

H

H

L

H

H

L

L

H

H

H

L

X

Q0

Q0

† This configuration is nonstable; that is, it does not

persist when PRE or CLR returns to its inactive

(high) level.

logic symbol

S

4

3

1CLK

1D

2

1D

R

1

1Q

5

6

C1

10

11

2CLK

12

2D

13

2Q

9

8

1PRE

2PRE

1CLR

2CLR

1Q

2Q

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for D, DB, J, PW, and W packages.

logic diagram, each flip-flop (positive logic)

TG

C

C

TG

C

C

TG

C

C

C

C

TG

C

C

PRE

CLK

D

CLR

Q

Q

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SN54LV74, SN74LV74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

 

 

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage range, V

O

 (see Notes 1 and 2) 

–0.5 V to V

CC

 + 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0 or V

I

 > V

CC

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0 or V

O

 > V

CC

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 (V

O

 = 0 to V

CC

±

25 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through V

CC

 or GND 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Maximum power dissipation at T

A

 = 55

°

C (in still air) (see Note 3): D package 

1.25 W

. . . . . . . . . . . . . . . . . . . 

DB or PW package 

0.5 W

. . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150

°

C and a board trace length of 750 mils.

recommended operating conditions (see Note 4)

SN54LV74

SN74LV74

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

2.7

5.5

2.7

5.5

V

VIH

High level input voltage

VCC = 2.7 V to 3.6 V

2

2

V

VIH

High-level input voltage

VCC = 4.5 V to 5.5 V

3.15

3.15

V

VIL

Low level input voltage

VCC = 2.7 V to 3.6 V

0.8

0.8

V

VIL

Low-level input voltage

VCC = 4.5 V to 5.5 V

1.65

1.65

V

VI

Input voltage

0

VCC

0

VCC

V

VO

Output voltage

0

VCC

0

VCC

V

IOH

High level output current

VCC = 2.7 V to 3.6 V

–6

–6

mA

IOH

High-level output current

VCC = 4.5 V to 5.5 V

–12

–12

mA

IOL

Low level output current

VCC = 2.7 V to 3.6 V

6

6

mA

IOL

Low-level output current

VCC = 4.5 V to 5.5 V

12

12

mA

t/

v

Input transition rise or fall rate

0

100

0

100

ns/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 4: Unused inputs must be held high or low to prevent them from floating.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

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SN54LV74, SN74LV74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

 

 

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

V

SN54LV74

SN74LV74

UNIT

PARAMETER

TEST CONDITIONS

VCC†

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

IOH = –100 

µ

A

MIN to MAX

VCC – 0.2

VCC – 0.2

VOH

IOH = –6 mA

3 V

2.4

2.4

V

IOH = –12 mA

4.5 V

3.6

3.6

IOL = 100 

µ

A

MIN to MAX

0.2

0.2

VOL

IOL = 6 mA

3 V

0.4

0.4

V

IOL = 12 mA

4.5 V

0.55

0.55

II

VI = VCC or GND

3.6 V

±

1

±

1

µ

A

II

VI = VCC or GND

5.5 V

±

1

±

1

µ

A

ICC

VI = VCC or GND

IO = 0

3.6 V

20

20

µ

A

ICC

VI = VCC or GND

IO = 0

5.5 V

20

20

µ

A

n

ICC

One input at

VCC – 0.6 V

Other inputs at

VCC or GND

3 V to 3.6 V

500

500

µ

A

Ci

VI = VCC or GND

3.3 V

2.5

2.5

pF

Ci

VI = VCC or GND

5 V

3

3

pF

† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

SN54LV74

VCC = 5 V

±

 0.5 V

VCC = 3.3 V 

±

 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

0

70

0

60

0

50

ns

t

Pulse duration LE high

PRE or CLR low

15

20

25

ns

tw

Pulse duration, LE high

CLK high or low

15

20

25

ns

t

Setup time data before CLK

Data

6

8

12

ns

tsu

Setup time, data before CLK

PRE or CLR inactive

5

6

8

ns

th

Hold time, data after CLK

3

3

3

ns

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

SN74LV74

VCC = 5 V

±

 0.5 V

VCC = 3.3 V

±

 0.3 V

VCC = 2.7 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

0

70

0

60

0

50

ns

t

Pulse duration LE high

PRE or CLR low

15

20

25

ns

tw

Pulse duration, LE high

CLK high or low

15

20

25

ns

t

Setup time data before CLK

Data

6

8

12

ns

tsu

Setup time, data before CLK

PRE or CLR inactive

5

6

8

ns

th

Hold time, data after CLK

3

3

3

ns

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54LV74, SN74LV74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

 

 

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, C

L

 = 50 pF

(unless otherwise noted) (see Figure 1)

FROM

TO

SN54LV74

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V 

±

 0.5 V

VCC = 3.3 V 

±

 0.3 V

VCC = 2.7 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

MAX

fmax

70

100

60

90

50

MHz

tpd

PRE or CLR

Q or Q

11

19

18

27

34

ns

tpd

CLK

Q or Q

10

17

17

26

28

ns

switching characteristics over recommended operating free-air temperature range, C

L

 = 50 pF

(unless otherwise noted) (see Figure 1)

FROM

TO

SN74LV74

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V 

±

 0.5 V

VCC = 3.3 V 

±

 0.3 V

VCC = 2.7 V

UNIT

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

MAX

fmax

70

100

60

90

50

MHz

tpd

PRE or CLR

Q or Q

11

19

18

27

34

ns

tpd

CLK

Q or Q

10

17

17

26

28

ns

operating characteristics, T

= 25

°

C

PARAMETER

TEST CONDITIONS

VCC

TYP

UNIT

C d

Power dissipation capacitance per flip flop

CL = 50 pF

f = 10 MHz

3.3 V

32

pF

Cpd

Power dissipation capacitance per flip-flop

CL = 50 pF,

f = 10 MHz

5 V

68

pF

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

background image

SN54LV74, SN74LV74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

 

 

SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Vm

th

tsu

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

Vz

Open

GND

1 k

1 k

Data Input

Timing Input

Vm

Vi

0 V

Vm

Vm

Vi

0 V

Vi

0 V

Vm

Vm

tw

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

Vm

Vm

Vi

0 V

Vm

Vm

Input

Vm

Output

Control

Output

Waveform 1

S1 at Vz

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

Vm

Vm

0.5 

×

 Vz

0 V

Vm

VOL + 0.3 V

Vm

VOH – 0.3 V

[

 0 V

Vi

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

Vz

GND

TEST

S1

0.5 

×

VCC

VCC

×

VCC

1.5 V

2.7 V

6 V

WAVEFORM

CONDITION

VCC = 4.5 V

to 5.5 V

VCC = 2.7 V

to 3.6 V

Vm

Vi

Vz

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 10 MHz, ZO = 50 

, tr 

 2.5 ns, tf

 2.5 ns.

D. The outputs are measured one at a time with one transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 1998, Texas Instruments Incorporated