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 SN74F377A

 OCTAL D-TYPE FLIP-FLOP

 WITH CLOCK ENABLE

 SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993

Copyright 

©

 1993, Texas Instruments Incorporated

2–1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Contains Eight D-Type Flip-Flops

With Single-Rail Outputs

Clock Enable Latched to Avoid False

Clocking

Applications Include:

Buffer/Storage Registers

Shift Registers

Pattern Generators

Buffered Common Enable Input

Package Options Include Plastic

Small-Outline Packages and Standard

Plastic 300-mil DIPs

 

description

The SN74F377A is a monolithic, positive-edge-triggered, octal, D-type flip-flop with clock enable inputs. The

SN74F377A features a latched clock enable (CE) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the

positive-going edge of the clock pulse if CE is low. Clock triggering occurs at a particular voltage level and is

not directly related to the positive-going pulse. When the clock input is at either the high or low level, the D input

signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the CE

input.

The SN74F377A is characterized for operation from 0

°

C to 70

°

C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CE

CLK

D

Q

H

X

X

Q0

L

H

H

L

L

L

X

L

X

Q0

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CE

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

V

CC

8Q

8D

7D

7Q

6Q

6D

5D

5Q

CLK

DW OR N PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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SN74F377A

OCTAL D-TYPE FLIP-FLOP

WITH CLOCK ENABLE

SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993

2–2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

13

5D

14

6D

17

7D

18

8D

1Q

2

2Q

5

3Q

6

4Q

9

1C2

CE

G1

1

11

CLK

2D

3

1D

4

2D

7

3D

8

4D

5Q

12

6Q

15

7Q

16

8Q

19

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

1D

11

1Q

1D

C1

CLK

CE

1

3

2

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

– 0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1)

– 1.2 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input current range 

 – 30 mA to 5 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high state

– 0.5 V to V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Current into any output in the low state

 40 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range

 0

°

C to 70

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range

– 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input-voltage ratings may be exceeded provided the input-current ratings are observed.

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 SN74F377A

 OCTAL D-TYPE FLIP-FLOP

 WITH CLOCK ENABLE

 SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993

2–3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.5

5

5.5

V

VIH

High-level input voltage

2

V

VIL

Low-level input voltage

0.8

V

IIK

Input clamp current

– 18

mA

IOH

High-level output current

– 1

mA

IOL

Low-level output current

20

mA

TA

Operating free-air temperature

0

70

°

C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOH

VCC = 4.5 V,

IOH = – 1 mA

2.5

3.4

V

VOH

VCC = 4.75 V,

IOH = – 1 mA

2.7

V

VOL

VCC = 4.5 V,

IOL = 20 mA

0.3

0.5

V

II

VCC = 0,

VI = 7 V

0.1

mA

IIH

VCC = 5.5 V,

VI = 2.7 V

20

µ

A

IIL

VCC = 5.5 V,

VI = 0.5 V

– 0.6

mA

IOS‡

VCC = 5.5 V,

VO = 0

– 60

– 150

mA

ICCH

VCC = 5.5 V,

See Note 2

55

72

mA

ICCL

VCC = 5.5 V,

See Note 3

70

90

mA

† All typical values are at VCC = 5 V, TA = 25

°

C.

‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

NOTES:

2. ICCH is measured after applying a momentary ground, then 4.5 V, to the clock input with all data inputs at 4.5 V and the enable input

at GND.

3. ICCL is measured after applying a momentary ground, then 4.5 V, to the clock input with all data and enable inputs at GND.

timing requirements

VCC = 5 V,

TA = 25

°

C

VCC = 4.5 V to 5.5 V,

TA = MIN to MAX§

UNIT

MIN

MAX

MIN

MAX

fclock

Clock frequency

0

110

0

110

MHz

tw

Pulse duration

4

5

ns

Data high or low

2

2

tsu

Setup time before CLK

CE high

2.5

2.5

ns

CE low

4

4.5

th

Hold time after CLK

Data high or low

1

1

ns

th

Hold time after CLK

CE high or low

0

0

ns

§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

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SN74F377A

OCTAL D-TYPE FLIP-FLOP

WITH CLOCK ENABLE

SDFS018D – D2932, MARCH 1987 – REVISED OCTOBER 1993

2–4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics (see Note 4)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

CL = 50 pF,

RL = 500 

,

TA = 25

°

C

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

RL = 500

,

TA = MIN to MAX †

UNIT

MIN

TYP

MAX

MIN

MAX

fmax

110

125

110

MHz

tPLH

CLK

Any Q

4

6.5

8.5

4

10

ns

tPHL

CLK

Any Q

4

7

9

4

10.5

ns

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

NOTE 4: Load circuit and waveforms are shown in Section 1.

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Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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Copyright 

©

 1998, Texas Instruments Incorporated