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 SN54F175, SN74F175

 QUADRUPLE D-TYPE FLIP-FLOPS

 WITH CLEAR

SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993

Copyright 

©

 1993, Texas Instruments Incorporated

2–1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Contain Four Flip-Flops With Double-Rail

Outputs

Buffered Clock and Direct Clear Inputs

Applications Include:

Buffer/Storage Registers

Shift Registers

Pattern Generators

Package Options Include Plastic

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

   

description

These monolithic, positive-edge-triggered flip-

flops utilize TTL circuitry to implement D-type

flip-flop logic with a direct clear (CLR) input.

Information at the data (D) inputs meeting setup

time requirements is transferred to outputs on the

positive-going edge of the clock pulse. Clock

triggering occurs at a particular voltage level and

is not directly related to the transition time of the

positive-going pulse. When the clock (CLK) input

is at either the high or low level, the D-input signal

has no effect at the output.

The SN54F175 is characterized for operation over

the full military temperature range of – 55

°

C to

125

°

C. The SN74F175 is characterized for

operation from 0

°

C to 70

°

C.

FUNCTION TABLE

INPUTS

OUTPUTS

CLR

CLK

D

Q

Q

L

X

X

L

H

H

H

H

L

H

L

L

H

H

L

X

Q0

Q0

SN54F175 . . . J  PACKAGE

SN74F175 . . . D  OR  N  PACKAGE

(TOP VIEW)

SN54F175 . . . FK PACKAGE

(TOP VIEW)

3

2

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

4Q

4D

NC

3D

3Q

1Q

1D

NC

2D

2Q

1Q

CLR

NC

CLK

3Q

V

4Q

2Q

GND

NC

CC

NC – No internal connection

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CLR

1Q

1Q

1D

2D

2Q

2Q

GND

V

CC

4Q

4Q

4D

3D

3Q

3Q

CLK

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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SN54F175, SN74F175

QUADRUPLE D-TYPE FLIP-FLOPS

WITH CLEAR

SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993

2–2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

CLR

1Q

2Q

R

1

9

CLK

C1

1D

4

1D

3

1Q

2

5

2D

6

2Q

7

12

3D

11

3Q

10

13

4D

14

4Q

15

3Q

4Q

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

15

4Q

13

1Q

4

9

1

C1

1D

2

C1

1D

CLR

CLK

1D

4D

R

R

Two Identical Channels

Not Shown

14

4Q

1Q

3

Pin numbers shown are for the D, J, and N packages.

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 SN54F175, SN74F175

 QUADRUPLE D-TYPE FLIP-FLOPS

 WITH CLEAR

 SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993

2–3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

 – 0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

 – 1.2 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input current range 

 – 30 mA to 5 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to any output in the high state 

 – 0.5 V to V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Current into any output in the low state 

 40 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range: SN54F175 

 – 55

°

C to 125

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74F175  

0

°

C to 70

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range 

 – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.

recommended operating conditions

SN54F175

SN74F175

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.5

5

5.5

4.5

5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

IIK

Input clamp current

– 18

– 18

mA

IOH

High-level output current

– 1

– 1

mA

IOL

Low-level output current

20

20

mA

TA

Operating free-air temperature

– 55

125

0

70

°

C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

SN54F175

SN74F175

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP‡

MAX

MIN

TYP‡

MAX

UNIT

VIK

VCC = 4.5 V,

II = – 18 mA

– 1.2

– 1.2

V

VOH

VCC = 4.5 V,

IOH = – 1 mA

2.5

3.4

2.5

3.4

V

VOH

VCC = 4.75 V,

IOH = – 1 mA

2.7

V

VOL

VCC = 4.5 V,

IOL = 20 mA

0.3

0.5

0.3

0.5

V

II

VCC = 5.5 V,

VI = 7 V

0.1

0.1

mA

IIH

VCC = 5.5 V,

VI = 2.7 V

20

20

µ

A

IIL

VCC = 5.5 V,

VI = 0.5 V

– 0.6

– 0.6

mA

IOS§

VCC = 5.5 V,

VO = 0

– 60

–150

– 60

–150

mA

ICC

VCC = 5.5 V,

See Note 2

22.5

34

22.5

34

mA

‡ All typical values are at VCC = 5 V, TA = 25

°

C.

§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

NOTE 2: ICC is measured with outputs open with 4.5 V applied to all data inputs after a momentary ground followed by 4.5 V applied to CLK.

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SN54F175, SN74F175

QUADRUPLE D-TYPE FLIP-FLOPS

WITH CLEAR

SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993

2–4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

VCC = 5 V,

TA = 25

°

C

SN54F175

SN74F175

UNIT

F175

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

fclock

Clock frequency

0

100

0

100

0

100

MHz

CLK high

4

4

4

tw

Pulse duration

CLK low

5

5

5

ns

CLR low

5

5

5

t

Setup time, data before CLK

High or low

3

3

3

ns

tsu

Setup time, inactive state, data before CLK

CLR high

5

5

5

ns

th

Hold time, data after CLK

High or low

1

1

1

ns

† Inactive-state setup time is also referred to as recovery time.

switching characteristics (see Note 3)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

CL = 50 pF,

RL = 500 

,

TA = 25

°

C

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

RL = 500

,

TA = MIN to MAX‡

UNIT

(INPUT)

(OUTPUT)

F175

SN54F175

SN74F175

MIN

TYP

MAX

MIN

MAX

MIN

MAX

fmax

100

140

100

100

MHz

tPLH

CLK

Q or Q

3.2

4.6

6.5

2.7

8.5

3.2

7.5

ns

tPHL

CLK

Q or Q

3.2

6.1

8.5

3.2

10.5

3.2

9.5

ns

tPLH

CLR

Q

3.2

6.1

8.5

3.2

10

3.2

9

ns

tPHL

CLR

Q

3.7

8.6

11.5

3.7

15

3.7

13

ns

‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

NOTE 3: Load circuits and waveforms are shown in Section 1.

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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Copyright 

©

 1998, Texas Instruments Incorporated