background image

 

SN54AHC273, SN74AHC273

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

 

SCLS376E – JUNE 1997 – REVISED JANUARY 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Operating Range 2-V to 5.5-V V

CC

D

Contain Eight Flip-Flops With Single-Rail

Outputs

D

Direct Clear Input

D

Individual Data Input to Each Flip-Flop

D

Applications Include:

–  Buffer/Storage Registers

–  Shift Registers

–  Pattern Generators

D

Latch-Up Performance Exceeds 250 mA Per

JESD 17

D

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Very Small-Outline (DGV), Thin

Shrink Small-Outline (PW), and Ceramic

Flat (W) Packages, Ceramic Chip Carriers

(FK), and Standard Plastic (N) and Ceramic

(J) DIPs

description

These circuits are positive-edge-triggered D-type

flip-flops with a direct clear (CLR) input.

Information at the data (D) inputs meeting the

setup time requirements is transferred to the

Q outputs on the positive-going edge of the clock

(CLK) pulse. Clock triggering occurs at a

particular voltage level and is not directly related

to the transition time of the positive-going pulse.

When CLK is at either the high or low level, the

D input has no effect at the output.

The SN54AHC273 is characterized for operation over the full military temperature range of –55

°

C to 125

°

C.

The SN74AHC273 is characterized for operation from –40

°

C to 85

°

C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLR

CLK

D

OUTPUT

Q

L

X

X

L

H

H

H

H

L

L

H

L

X

Q0

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Copyright 

©

 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

SN54AHC273 . . . J  OR  W  PACKAGE

SN74AHC273 . . . DB, DGV, DW, N, OR PW PACKAGE

(TOP VIEW)

 SN54AHC273 . . . FK PACKAGE

(TOP VIEW)

3

2

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

2D

2Q

3Q

3D

4D

1D

1Q

CLR

5Q

5D

8Q

4Q

GND

CLK

V

CC

8D

7D

7Q

6Q

6D

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CLR

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

V

CC

8Q

8D

7D

7Q

6Q

6D

5D

5Q

CLK

background image

SN54AHC273, SN74AHC273

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

 

SCLS376E – JUNE 1997 – REVISED JANUARY 2000

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

1D

3

1D

4

2D

7

3D

R

1

1Q

2

2Q

5

3Q

6

8

4D

13

5D

14

6D

4Q

9

5Q

12

6Q

15

CLR

17

7D

18

8D

11

CLK

7Q

16

8Q

19

C1

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

CLK

1D

1Q

2D

2Q

3D

3Q

4D

4Q

5D

5Q

6D

6Q

7D

7Q

8D

8Q

CLR

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

1D

R

C1

3

4

7

8

13

14

17

18

2

5

6

9

12

15

16

19

11

1

logic diagram, each flip-flop (positive logic)

CLK(I)

R

Q

C

C

D

C

C

C

C

C

C

TG

C

C

TG

TG

TG

background image

SN54AHC273, SN74AHC273

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

 

SCLS376E – JUNE 1997 – REVISED JANUARY 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage range, V

O

 (see Note 1) 

–0.5 V to V

CC 

+ 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK 

(V

< 0) 

–20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK 

(V

< 0 or V

O

 > V

CC

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

(V

= 0 to V

CC

±

25 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through V

CC

 or GND 

±

75 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA

 (see Note 2): DB package 

70

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DGV package 

92

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DW package 

58

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

N package 

69

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

PW package 

83

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

SN54AHC273

SN74AHC273

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

2

5.5

2

5.5

V

VCC = 2 V

1.5

1.5

VIH

High-level input voltage

VCC = 3 V

2.1

2.1

V

VCC = 5.5 V

3.85

3.85

VCC = 2 V

0.5

0.5

VIL

Low-level input voltage

VCC = 3 V

0.9

0.9

V

VCC = 5.5 V

1.65

1.65

VI

Input voltage

0

5.5

0

5.5

V

VO

Output voltage

0

VCC

0

VCC

V

VCC = 2 V

–50

–50

m

A

IOH

High-level output current

VCC = 3.3 V 

±

 0.3 V

–4

–4

mA

VCC = 5 V 

±

 0.5 V

–8

–8

mA

VCC = 2 V

50

50

m

A

IOL

Low-level output current

VCC = 3.3 V 

±

 0.3 V

4

4

mA

VCC = 5 V 

±

 0.5 V

8

8

mA

t/

v

Input transition rise or fall rate

VCC = 3.3 V 

±

 0.3 V

100

100

ns/V

t/

v

Input transition rise or fall rate

VCC = 5 V 

±

 0.5 V

20

20

ns/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

background image

SN54AHC273, SN74AHC273

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

 

SCLS376E – JUNE 1997 – REVISED JANUARY 2000

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25

°

C

SN54AHC273

SN74AHC273

UNIT

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

1.9

1.9

1.9

IOH = –50 

m

A

3 V

2.9

2.9

2.9

VOH

4.5 V

4.4

4.4

4.4

V

IOH = –4 mA

3 V

2.58

2.48

2.48

IOH = –8 mA

4.5 V

3.94

3.8

3.8

2 V

0.1

0.1

0.1

IOL = 50 

m

A

3 V

0.1

0.1

0.1

VOL

4.5 V

0.1

0.1

0.1

V

IOL = 4 mA

3 V

0.36

0.5

0.44

IOL = 8 mA

4.5 V

0.36

0.5

0.44

II

VI = VCC or GND

0 V to 5.5 V

±

0.1

±

1*

±

1

m

A

ICC

VI = VCC or GND,

IO = 0

5.5 V

4

40

40

m

A

Ci

VI = VCC or GND

5 V

2.5

10

10

pF

* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.

timing requirements over recommended operating free-air temperature range, V

CC

 = 3.3 V 

±

 0.3 V

(unless otherwise noted) (see Figure 1)

SN54AHC273

SN74AHC273

TA = 25

°

C

MIN

MAX

TA = 25

°

C

MIN

MAX

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

t

Pulse duration

CLR low

5

6

5

6

ns

tw

Pulse duration

CLK high or low

5

6.5

5

6.5

ns

t

Setup time

Data before CLK

5.5

6.5

5.5

6.5

ns

tsu

Setup time

CLR before CLK

2.5

2.5

2.5

2.5

ns

th

Hold time, data after CLK

1.5

2

1

1

ns

timing requirements over recommended operating free-air temperature range, V

CC

 = 5 V 

±

 0.5 V

(unless otherwise noted) (see Figure 1)

SN54AHC273

SN74AHC273

TA = 25

°

C

MIN

MAX

TA = 25

°

C

MIN

MAX

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

t

Pulse duration

CLR low

5

5

5

5

ns

tw

Pulse duration

CLK high or low

5

5

5

5

ns

t

Setup time

Data before CLK

4.5

4.5

4.5

4.5

ns

tsu

Setup time

CLR before CLK

2

2

2

2

ns

th

Hold time, data after CLK

1.5

2

1

1

ns

background image

SN54AHC273, SN74AHC273

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

 

SCLS376E – JUNE 1997 – REVISED JANUARY 2000

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range,

V

CC 

= 3.3 V

±

0.3 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

LOAD

TA = 25

°

C

SN54AHC273

SN74AHC273

UNIT

PARAMETER

(INPUT)

(OUTPUT)

CAPACITANCE

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

f

CL = 15 pF

75*

120*

65*

65

MHz

fmax

CL = 50 pF

50

75

45

45

MHz

tPHL

CLR

Q

CL = 15 pF

8.9*

13.6*

1*

16*

1

16

ns

tPLH

CLK

Q

CL = 15 pF

8.7*

13.6*

1*

16*

1

16

ns

tPHL

CLK

Q

CL = 15 pF

8.7*

13.6*

1*

16*

1

16

ns

tPHL

CLR

Q

CL = 50 pF

11.4

17.1

1

19.5

1

19.5

ns

tPLH

CLK

Q

CL = 50 pF

11.2

17.1

1

19.5

1

19.5

ns

tPHL

CLK

Q

CL = 50 pF

11.2

17.1

1

19.5

1

19.5

ns

tsk(o)

CL = 50 pF

1.5**

1.5

ns

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

** On products compliant to MIL-PRF-38535, this parameter does not apply.

switching characteristics over recommended operating free-air temperature range,

V

CC 

= 5 V

±

0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

LOAD

TA = 25

°

C

SN54AHC273

SN74AHC273

UNIT

PARAMETER

(INPUT)

(OUTPUT)

CAPACITANCE

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

f

CL = 15 pF

120*

165*

100*

100

MHz

fmax

CL = 50 pF

80

110

70

70

MHz

tPHL

CLR

Q

CL = 15 pF

5.2*

8.5*

1*

10*

1

10

ns

tPLH

CLK

Q

CL = 15 pF

5.8*

9*

1*

10.5*

1

10.5

ns

tPHL

CLK

Q

CL = 15 pF

5.8*

9*

1*

10.5*

1

10.5

ns

tPHL

CLR

Q

CL = 50 pF

6.7

10.5

1

12

1

12

ns

tPLH

CLK

Q

CL = 50 pF

7.3

11

1

12.5

1

12.5

ns

tPHL

CLK

Q

CL = 50 pF

7.3

11

1

12.5

1

12.5

ns

tsk(o)

CL = 50 pF

1**

1

ns

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

** On products compliant to MIL-PRF-38535, this parameter does not apply.

noise characteristics, V

CC 

= 5 V, C

L

 = 50 pF, T

A

 = 25

°

C (see Note 4)

PARAMETER

SN74AHC273

UNIT

PARAMETER

MIN

TYP

MAX

UNIT

VOL(P)

Quiet output, maximum dynamic VOL

0.7

V

VOL(V)

Quiet output, minimum dynamic VOL

–0.7

V

VOH(V)

Quiet output, minimum dynamic VOH

4.7

V

VIH(D)

High-level dynamic input voltage

3.5

V

VIL(D)

Low-level dynamic input voltage

1.5

V

NOTE 4: Characteristics are for surface-mount packages only.

operating characteristics, T

A

 = 25

°

C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

No load,

f = 1 MHz

31

pF

background image

SN54AHC273, SN74AHC273

OCTAL D-TYPE FLIP-FLOPS

WITH CLEAR

 

SCLS376E – JUNE 1997 – REVISED JANUARY 2000

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

50% VCC

VCC

VCC

0 V

0 V

th

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

VCC

0 V

50% VCC

50% VCC

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

50% VCC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

Waveform 1

S1 at VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VCC

0 V

50% VCC

VOL

 

+ 0.3 V

50% VCC

0 V

VCC

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open Drain

Open

VCC

GND

VCC

TEST

S1

VCC

0 V

50% VCC

tw

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 1 MHz, ZO = 50 

, tr 

3 ns, tf 

 3 ns.

D. The outputs are measured one at a time with one input transition per measurement.

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

S1

VCC

RL = 1 k

GND

From Output

Under Test

CL

(see Note A)

Test

Point

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

VOH –

 

0.3 V

Figure 1. Load Circuit and Voltage Waveforms

background image

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 2000, Texas Instruments Incorporated