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1

Data sheet acquired from Harris Semiconductor

SCHS184

Features

• Buffered Common Clock

• Buffered Inputs

• Typical Propagation Delay = 17ns at C

L

 = 15pF,

V

CC

 = 5V, T

A

 = 25

o

C

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs  . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range  . . . -55

o

C to 125

o

C

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

= 30%, N

IH

= 30%of V

CC

at

V

CC

 = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

IL

= 0.8V (Max), V

IH

 = 2V (Min)

- CMOS Input Compatibility, I

l

1

µ

A at V

OL

, V

OH

Description

The Harris CD74HC377 and CD74HCT377 are octal D-type

flip-flops with a buffered clock (CP) common to all eight flip-

flops. All the flip-flops are loaded simultaneously on the

positive edge of the clock (CP) when the Data Enable (E) is

Low.

Pinout

CD74HC377, CD74HCT377

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE (

o

C)

PACKAGE

PKG.

NO.

CD74HC377E

-55 to 125

20 Ld PDIP

E20.3

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

E

Q

0

D

0

D

1

Q

1

Q

2

D

3

D

2

Q

3

GND

V

CC

D

7

D

6

Q

6

Q

7

Q

5

D

5

D

4

Q

4

CP

September 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

 ©

 Harris Corporation 1997

File Number

1675.1

CD74HC377,

CD74HCT377

High Speed CMOS Logic

Octal D-Type Flip-Flop with Data Enable

[ /Title

(CD74

HC377

,

CD74

HCT37

7)

/Sub-

ject

(High

Speed

CMOS

Logic

Octal

D-

Type

Flip-

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2

Functional Diagram

Logic Diagram

TRUTH TABLE

OPERATING MODE

INPUTS

OUPUTS

CP

E

D

n

Q

n

Load “1”

l

h

H

Load “0”

l

l

L

Hold (Do Nothing)

h

X

No Change

X

H

X

No Change

NOTES:

H = High Voltage Level Steady State.

h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition.

L = Low Voltage Level Steady State.

l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition.

X = Don’t Care.

 = Low to High Clock Transition.

2

5

6

9

15

19

16

12

Q

0

Q

1

Q

2

Q

3

Q

4

Q

5

Q

6

Q

7

CP

E

11

1

GND = 10

V

CC

= 20

3

4

7

8

14

18

17

13

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

E

D

0

D

1

D

2

D

3

D

6

D

7

Q

D

CP

CP

Q

0

Q

1

Q

2

Q

3

Q

6

Q

7

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

4

Q

5

D

4

D

5

CD74HC377, CD74HCT377

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3

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

CC

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For V

I

 < -0.5V or V

I

 > V

CC

 + 0.5V

. . . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Diode Current, I

OK

For V

O

 < -0.5V or V

O

 > V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Source or Sink Current per Output Pin, I

O

For V

O

 > -0.5V or V

O

 < V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

25mA

DC V

CC

 or Ground Current, I

CC or

I

GND

. . . . . . . . . . . . . . . . . .±

50mA

Operating Conditions

Temperature Range (T

A

)  . . . . . . . . . . . . . . . . . . . . . -55

o

C to 125

o

C

Supply Voltage Range, V

CC

HC Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

I

, V

O

 . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3)

θ

JA

 (

o

C/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

125

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

o

C

Maximum Storage Temperature Range  . . . . . . . . . .-65

o

C to 150

o

C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

o

C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3.

θ

JA

 is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C -55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

High Level Input

Voltage

V

IH

-

-

2

1.5

-

-

1.5

-

1.5

-

V

4.5

3.15

-

-

3.15

 -

3.15

-

V

6

4.2

-

-

4.2

-

4.2

-

V

Low Level Input

Voltage

V

IL

-

-

2

-

-

0.5

-

0.5

-

0.5

V

4.5

-

-

1.35

-

1.35

-

1.35

V

6

-

-

1.8

-

1.8

-

1.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

or V

IL

-0.02

2

1.9

-

-

1.9

-

1.9

-

V

-0.02

4.5

4.4

-

-

4.4

 -

4.4

-

V

-0.02

6

5.9

-

-

5.9

-

5.9

-

V

High Level Output

Voltage

TTL Loads

-

-

-

-

-

-

-

-

-

V

-4

4.5

3.98

-

-

3.84

-

3.7

-

V

-5.2

6

5.48

-

-

5.34

-

5.2

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

or V

IL

0.02

2

-

-

0.1

-

0.1

-

0.1

V

0.02

4.5

-

-

0.1

-

0.1

-

0.1

V

0.02

6

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

-

-

-

-

-

-

-

-

-

V

4

4.5

-

-

0.26

-

0.33

-

0.4

V

5.2

6

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

 or

GND

-

6

-

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

6

-

-

8

-

80

-

160

µ

A

CD74HC377, CD74HCT377

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4

HCT TYPES

High Level Input

Voltage

V

IH

-

-

4.5 to

5.5

2

-

-

2

-

2

-

V

Low Level Input

Voltage

V

IL

-

-

4.5 to

5.5

-

-

0.8

-

0.8

-

0.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

or V

IL

-0.02

4.5

4.4

-

-

4.4

-

4.4

-

V

High Level Output

Voltage

TTL Loads

-4

4.5

3.98

-

-

3.84

-

3.7

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

or V

IL

0.02

4.5

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

4

4.5

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

and

GND

0

5.5

-

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

5.5

-

-

8

-

80

-

160

µ

A

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

I

CC

V

CC

-2.1

-

4.5 to

5.5

-

100

360

-

450

-

490

µ

A

NOTE: For dual-supply systems theoretical worst case (V

I

 = 2.4V, V

CC

 = 5.5V) specification is 1.8mA.

DC Electrical Specifications

 (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C -55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HCT Input Loading Table

INPUT

UNIT LOADS

E

1.5

CP

0.5

All D

n

 Inputs

0.25

NOTE: Unit Load is

I

CC

limit specified in DC Electrical Table, e.g.,

360

µ

A max at 25

o

C.

Prerequisite for Switching Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

Maximum Clock

Frequency

f

MAX

-

2

6

-

-

5

-

4

-

MHz

4.5

30

-

-

25

-

20

-

MHz

6

35

-

-

29

-

23

-

MHz

Clock Pulse Width

t

W

-

2

80

-

-

100

-

120

-

ns

4.5

16

-

-

20

-

24

-

ns

6

14

-

-

17

-

20

-

ns

CD74HC377, CD74HCT377

background image

5

Set-up Time,

E, Data to CP

t

SU

-

2

60

-

-

75

-

90

-

ns

4.5

12

-

-

15

-

18

-

ns

6

10

-

-

13

-

15

-

ns

Hold Time,

Data to CP

t

H

-

2

3

-

-

3

-

3

-

ns

4.5

3

-

-

3

-

3

-

ns

6

3

-

-

3

-

3

-

ns

Hold Time,

E to CP

t

H

-

2

5

-

-

5

-

5

-

ns

4.5

5

-

-

5

-

5

-

ns

6

5

-

-

5

-

5

-

ns

HCT TYPES

Maximum Clock

Frequency

f

MAX

-

4.5

25

-

-

20

-

16

-

MHz

Clock Pulse Width

t

W

-

4.5

20

-

-

25

-

30

-

ns

Set-up, Time

E, Data to CP

t

SU

-

4.5

12

-

-

15

-

18

-

ns

Hold Time,

Data to CP

t

H

-

4.5

3

-

-

3

-

3

-

ns

Hold Time,

E to CP

t

H

-

4.5

5

-

-

5

-

5

-

ns

Switching Specifications

Input t

r

, t

f

 = 6ns

PARAMETER

SYMBOL

TEST

CONDITIONS

 V

CC

(V)

25

o

C

-40

o

C TO

85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

Propagation Delay (Figure 1)

t

PLH,

t

PHL

C

L

= 50pF

2

-

-

175

-

220

-

265

ns

CP to Q

4.5

-

-

35

-

44

-

53

ns

C

L

=15pF

5

-

14

-

-

-

-

-

ns

C

L

= 50pF

6

-

-

30

-

37

-

45

ns

Output Transition Time

(Figure 1)

t

TLH

, t

THL

C

L

= 50pF

2

-

-

75

-

95

-

110

ns

4.5

-

-

15

-

19

-

22

ns

6

-

-

13

-

16

-

19

ns

Input Capacitance

C

IN

C

L

= 50pF

-

-

-

10

-

10

-

10

pF

Maximum Clock Frequency

f

MAX

C

L

=15pF

5

-

60

-

-

-

-

-

MHz

Power Dissipation Capacitance

(Notes 4, 5)

C

PD

C

L

=15pF

5

-

31

-

-

-

-

-

pF

HCT TYPES

Propagation Delay (Figure 1)

t

PLH,

t

PHL

C

L

= 50pF

4.5

-

-

38

-

48

-

57

ns

CP to Q

C

L

=15pF

5

-

16

-

-

-

-

-

ns

Output Transition Time

(Figure 1)

t

TLH

, t

THL

C

L

= 50pF

4.5

-

-

15

-

19

-

22

ns

Input Capacitance

C

IN

C

L

= 50pF

-

-

-

10

-

10

-

10

pF

Prerequisite for Switching Specifications

 (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

CD74HC377, CD74HCT377

background image

6

Maximum Clock Frequency

f

MAX

C

L

=15pF

5

-

50

-

-

-

-

-

MHz

Power Dissipation Capacitance

(Notes 4, 5)

C

PD

C

L

=15pF

5

-

35

-

-

-

-

-

pF

NOTES:

4. C

PD

 is used to determine the dynamic power consumption, per flip-flop.

5. P

D

 = V

CC

2

 f

i

(C

PD

 + C

L

) where f

i

 = Input Frequency, C

L

 = Output Load Capacitance, V

CC

 = Supply Voltage.

Switching Specifications

Input t

r

, t

f

 = 6ns  (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

 V

CC

(V)

25

o

C

-40

o

C TO

85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Test Circuits and Waveforms

FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

t

r

C

L

t

f

C

L

GND

V

CC

GND

V

CC

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

V

CC

50%

50%

90%

10%

50%

90%

t

REM

t

PLH

t

SU(H)

t

TLH

t

THL

t

H(L)

t

PHL

IC

C

L

50pF

t

SU(L)

t

H(H)

t

r

C

L

t

f

C

L

GND

3V

GND

3V

1.3V

2.7V

0.3V

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

3V

1.3V

1.3V

1.3V

90%

10%

1.3V

90%

t

REM

t

PLH

t

SU(H)

t

TLH

t

THL

t

H(L)

t

PHL

IC

C

L

50pF

t

SU(L)

1.3V

t

H(H)

1.3V

CD74HC377, CD74HCT377

background image

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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In order to minimize risks associated with the customer’s applications, adequate design and operating

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TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

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Copyright 

©

 1999, Texas Instruments Incorporated