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1

Data sheet acquired from Harris Semiconductor

SCHS160

Features

• Common Clock and Asynchronous Reset on Four

D-Type Flip-Flops

• Positive Edge Pulse Triggering

• Complementary Outputs

• Buffered Inputs

• Typical f

MAX

 = 50MHz at V

CC

 = 5V, C

L

 = 15pF,

T

A

 = 25

o

C

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs  . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range  . . . -55

o

C to 125

o

C

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

 = 30%, N

IH

 = 30% of V

CC

at V

CC

 = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

IL

= 0.8V (Max), V

IH

 = 2V (Min)

- CMOS Input Compatibility, I

l

1

µ

A at V

OL

, V

OH

Description

The Harris CD74HC175 and CD74HCT175 are high speed

Quad D-type Flip-Flops with individual D-inputs and Q, Q

complementary outputs. The devices are fabricated using

silicon gate CMOS technology. They have the low power

consumption advantage of standard CMOS ICs and the

ability to drive 10 LSTTL devices.

Information at the D input is transferred to the Q, Q outputs on

the positive going edge of the clock pulse. All four Flip-Flops

are controlled by a common clock (CP) and a common reset

(MR). Resetting is accomplished by a low voltage level

independent of the clock. All four Q outputs are reset to a

logic 0 and all four Q outputs to a logic 1.

Pinout

CD74HC175, CD74HCT175

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

o

C)

PACKAGE

PKG.

NO.

CD74HC175E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT175E

-55 to 125

16 Ld PDIP

E16.3

CD74HC175M

-55 to 125

16 Ld SOIC

M16.15

CD74HCT175M

-55 to 125

16 Ld SOIC

M16.15

CD74HCT175W

-55 to 125

Wafer

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical

specifications. Please contact your local sales office or Harris

customer service for ordering information.

MR

Q

0

Q

0

D

0

D

1

Q

1

GND

V

CC

Q

3

Q

3

D

3

D

2

Q

2

Q

2

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

CP

Q

1

August 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

 ©

 Harris Corporation 1997

CD74HC175,

CD74HCT175

High Speed CMOS Logic

Quad D-Type Flip-Flop with Reset

File Number

1474.1

[ /Title

(CD74

HC175

,

CD74

HCT17

5)

/Sub-

ject

(High

Speed

CMOS

Logic

Quad

D-

Type

Flip-

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2

Functional Diagram

Logic Diagram

TRUTH TABLE

INPUTS

OUTPUTS

RESET (MR)

CLOCK CP

DATA D

n

Q

n

Q

n

L

X

X

L

H

H

H

H

L

H

L

L

H

H

L

X

Q

0

Q

0

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,

 = Transition from Low to High Level,

Q

0

= Level Before the Indicated Steady-State Input Conditions Were Established.

CP

D

R

2

Q

0

9

4

D

0

CP

Q

Q

3

Q

0

MR

1

CP

D

R

7

Q

1

5

D

1

Q

Q

6

Q

1

CP

D

R

10

Q

2

12

D

2

Q

Q

11

Q

2

CP

D

R

15

Q

3

13

D

3

Q

Q

14

Q

3

C

L

p

n

C

L

D

n

MR

CP

1

9

4 (5, 12, 13)

D

C

L

C

L

C

L

C

L

TO OTHER THREE F/F

TO OTHER THREE F/F

R

Q

n

2( 7, 10, 15)

CP

C

L

p

n

C

L

p

n

C

L

C

L

p

n

8

16

V

CC

ONE OF FOUR F/F

Q

n

GND

3( 6, 11, 14)

CD74HC175, CD74HCT175

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3

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

CC

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For V

I

 < -0.5V or V

I

 > V

CC

 + 0.5V

. . . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Diode Current, I

OK

For V

O

 < -0.5V or V

O

 > V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Source or Sink Current per Output Pin, I

O

For V

O

 > -0.5V or V

O

 < V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

25mA

DC V

CC

 or Ground Current, I

CC or

I

GND

. . . . . . . . . . . . . . . . . .±

50mA

Operating Conditions

Temperature Range (T

A

)  . . . . . . . . . . . . . . . . . . . . . -55

o

C to 125

o

C

Supply Voltage Range, V

CC

HC Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

I

, V

O

 . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3)

θ

JA

 (

o

C/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

90

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

110

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

o

C

Maximum Storage Temperature Range  . . . . . . . . . .-65

o

C to 150

o

C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

o

C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3.

θ

JA

 is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO +85

o

C

-55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

High Level Input

Voltage

V

IH

-

-

2

1.5

-

-

1.5

-

1.5

-

V

4.5

3.15

-

-

3.15

 -

3.15

-

V

6

4.2

-

-

4.2

-

4.2

-

V

Low Level Input

Voltage

V

IL

-

-

2

-

-

0.5

-

0.5

-

0.5

V

4.5

-

-

1.35

-

1.35

-

1.35

V

6

-

-

1.8

-

1.8

-

1.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

 or

V

IL

-0.02

2

1.9

-

-

1.9

-

1.9

-

V

-0.02

4.5

4.4

-

-

4.4

 -

4.4

-

V

-0.02

6

5.9

-

-

5.9

-

5.9

-

V

High Level Output

Voltage

TTL Loads

-4

4.5

3.98

-

-

3.84

-

3.7

-

V

-5.2

6

5.48

-

-

5.34

-

5.2

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

 or

V

IL

0.02

2

-

-

0.1

-

0.1

-

0.1

V

0.02

4.5

-

-

0.1

-

0.1

-

0.1

V

0.02

6

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

4

4.5

-

-

0.26

-

0.33

-

0.4

V

5.2

6

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

 or

GND

-

6

-

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

6

-

-

8

-

80

-

160

µ

A

CD74HC175, CD74HCT175

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4

HCT TYPES

High Level Input

Voltage

V

IH

-

-

4.5 to

5.5

2

-

-

2

-

2

-

V

Low Level Input

Voltage

V

IL

-

-

4.5 to

5.5

-

-

0.8

-

0.8

-

0.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

 or

V

IL

-0.02

4.5

4.4

-

-

4.4

-

4.4

-

V

High Level Output

Voltage

TTL Loads

-4

4.5

3.98

-

-

3.84

-

3.7

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

 or

V

IL

0.02

4.5

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

4

4.5

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

 to

GND

0

5.5

-

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

5.5

-

-

8

-

80

-

160

µ

A

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

(Note 4)

I

CC

V

CC

-2.1

-

4.5 to

5.5

-

100

360

-

450

-

490

µ

A

NOTES:

4. For dual-supply systems theorectical worst case (V

I

 = 2.4V, V

CC

 = 5.5V) specification is 1.8mA.

5. Die for this part number is available which meets all electrical specifications.

DC Electrical Specifications

 (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO +85

o

C

-55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HCT Input Loading Table

INPUT

UNIT LOADS

MR

1

CP

0.60

D

0.15

NOTE: Unit Load is

I

CC

limit specified in DC Electrical

Specifications table, e.g. 360

µ

A max at 25

o

C.

Prerequisite For Switching Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

Clock Pulse Width

t

w

-

2

80

-

-

100

-

120

-

ns

4.5

16

-

-

20

-

24

-

ns

6

14

-

-

17

-

20

-

ns

MR Pulse Width

t

w

-

2

80

-

-

100

-

120

-

ns

4.5

16

-

-

20

-

24

-

ns

6

14

-

-

17

-

20

-

ns

CD74HC175, CD74HCT175

background image

5

Setup Time, Data to Clock

t

SU

-

2

80

-

-

100

-

120

-

ns

4.5

16

-

-

20

-

24

-

ns

6

14

-

-

17

-

20

-

ns

Hold Time, Data to Clock

t

H

-

2

5

-

-

5

-

5

-

ns

4.5

5

-

-

5

-

5

-

ns

6

5

-

-

5

-

5

-

ns

Removal Time, MR to Clock

t

REM

-

2

5

-

-

5

-

5

-

ns

4.5

5

-

-

5

-

5

-

ns

6

5

-

-

5

-

5

-

ns

Clock Frequency

f

MAX

-

2

6

-

-

5

-

4

-

MHz

4.5

30

-

-

25

-

20

-

MHz

6

35

-

-

29

-

23

-

MHz

HCT TYPES

Clock Pulse Width

t

w

-

4.5

20

-

-

25

-

30

-

ns

MR Pulse Width

t

w

-

4.5

20

-

-

25

-

30

-

ns

Setup Time Data to Clock

t

SU

-

4.5

20

-

-

25

-

30

-

ns

Hold Time Data to Clock

t

H

-

4.5

5

-

-

5

-

5

-

ns

Removal Time MR to Clock

t

REM

-

4.5

5

-

-

5

-

5

-

ns

Clock Frequency

f

MAX

-

4.5

25

-

-

20

-

16

-

MHz

Switching Specifications

Input t

r

, t

f

 = 6ns

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO

125

o

C

UNITS

TYP

MAX

MAX

MAX

HC TYPES

Propagation Delay, Clock to

Q or Q

t

PLH

, t

PHL

C

L

= 50pF

2

-

175

220

265

ns

4.5

-

35

44

53

ns

6

-

30

37

45

ns

C

L

= 15pF

5

14

-

-

-

ns

Propagation Delay,

MR to Q or Q

t

PLH

, t

PHL

C

L

= 50pF

2

-

175

220

265

ns

4.5

-

35

44

53

ns

6

-

30

37

45

ns

C

L

= 15pF

5

14

-

-

-

ns

Output Transition Times

t

TLH

, t

THL

C

L

= 50pF

2

-

75

95

110

ns

4.5

-

15

19

22

ns

6

-

13

16

19

ns

Input Capacitance

C

IN

-

-

-

10

10

10

pF

Power Dissipation

Capacitance

(Notes 6, 7)

C

PD

-

5

65

-

-

-

pF

Prerequisite For Switching Specifications

 (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

CD74HC175, CD74HCT175

background image

6

HCT TYPES

Propagation Delay,

Clock to Q or Q

t

PLH

, t

PHL

C

L

= 50pF

4.5

-

33

41

50

ns

C

L

= 15pF

5

13

-

-

-

ns

Propagation Delay,

MR to Q or Q

t

PLH

, t

PHL

C

L

= 50pF

4.5

-

35

44

53

ns

C

L

= 15pF

5

17

-

-

-

ns

Output Transition Times

t

TLH

, t

THL

C

L

= 50pF

4.5

-

15

19

22

ns

Input Capacitance

C

IN

-

-

-

10

10

10

pF

Power Dissipation

Capacitance

(Notes 6, 7)

C

PD

-

5

67

-

-

-

pF

NOTES:

6. C

PD

 is used to determine the dynamic power consumption, per flip-flop.

7. P

D

= V

CC

2

f

i

+

(C

L

V

CC

2

+ f

O

) where f

i

= Input Frequency, f

O

= Input Frequency, C

L

= Output Load Capacitance, V

CC

= Supply Voltage.

Switching Specifications

Input t

r

, t

f

 = 6ns  (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

 (V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO

125

o

C

UNITS

TYP

MAX

MAX

MAX

Test Circuits and Waveforms

FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

t

r

C

L

t

f

C

L

GND

V

CC

GND

V

CC

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

V

CC

50%

50%

90%

10%

50%

90%

t

REM

t

PLH

t

SU(H)

t

TLH

t

THL

t

H(L)

t

PHL

IC

C

L

50pF

t

SU(L)

t

H(H)

t

r

C

L

t

f

C

L

GND

3V

GND

3V

1.3V

2.7V

0.3V

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

3V

1.3V

1.3V

1.3V

90%

10%

1.3V

90%

t

REM

t

PLH

t

SU(H)

t

TLH

t

THL

t

H(L)

t

PHL

IC

C

L

50pF

t

SU(L)

1.3V

t

H(H)

1.3V

CD74HC175, CD74HCT175

background image

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

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WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

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In order to minimize risks associated with the customer’s applications, adequate design and operating

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