background image

 SN54ALS874B, SN74ALS874B, SN74ALS876A

 SN74AS874, SN74AS876

 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS

 SDAS061C – APRIL 1982 – REVISED JANUARY 1995

Copyright 

©

 1995, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

3-State Buffer-Type Outputs Drive Bus

Lines Directly

Bus-Structured Pinout

Choice of True or Inverting Logic

–  SN54ALS874B, SN74ALS874B,

SN74AS874 Have True Outputs

–  SN74ALS876A, SN74AS876 Have

Inverting Outputs

Asynchronous Clear

Package Options Include Plastic

Small-Outline (DW) Packages, Plastic (FN)

and Ceramic (FK) Chip Carriers, and

Standard Plastic (NT) and Ceramic (JT)

300-mil DIPs

 

description

These dual 4-bit D-type edge-triggered flip-flops

feature 3-state outputs designed specifically as

bus drivers. They are particularly suitable for

implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

The edge-triggered flip-flops enter data on the

low-to-high transition of the clock (CLK) input.

The SN54ALS874B, SN74ALS874B, and

SN74AS874 have clear (CLR) inputs and

noninverting Q outputs. The SN74ALS876A and

SN74AS876 have preset (PRE) inputs and

inverting Q outputs; taking PRE low causes the

four Q or Q outputs to go low independently of the

clock.

The SN54ALS874B is characterized for operation

over the full military temperature range of – 55

°

C

to 125

°

C. The SN74ALS874B, SN74ALS876A,

SN74AS874, and SN74AS876 devices are

characterized for operation from 0

°

C to 70

°

C.

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

1CLR

1OE

1D1

1D2

1D3

1D4

2D1

2D2

2D3

2D4

2OE

GND

V

CC

1CLK

1Q1

1Q2

1Q3

1Q4

2Q1

2Q2

2Q3

2Q4

2CLK

2CLR

SN54ALS874B . . . JT  PACKAGE

SN74ALS874B, SN74AS874 . . . DW OR NT PACKAGE

(TOP VIEW)

3 2

1

13 14

5

6

7

8

9

10

11

1Q2

1Q3

1Q4

NC

2Q1

2Q2

2Q3

1D2

1D3

1D4

NC

2D1

2D2

2D3

4

15 16 17 18

2OE

GND

NC

2CLR

2CLK

2Q4

1D1

1OE

1CLR

NC

SN54ALS874B . . . FK PACKAGE

(TOP VIEW)

28 27 26

25

24

23

22

21

20

19

12

2D4

1CLK

1Q1

CC

V

NC – No internal connection

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

1PRE

1OE

1D1

1D2

1D3

1D4

2D1

2D2

2D3

2D4

2OE

GND

V

CC

1CLK

1Q1

1Q2

1Q3

1Q4

2Q1

2Q2

2Q3

2Q4

2CLK

2PRE

SN74ALS876A, SN74AS876 . . . DW OR NT PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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SN54ALS874B, SN74ALS874B, SN74ALS876A

SN74AS874, SN74AS876

DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SDAS061C – APRIL 1982 – REVISED JANUARY 1995

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Function Tables

SN54ALS874B, SN74ALS874B, SN74AS874

(each flip-flop)

INPUTS

OUTPUT

OE

CLR

CLK

D

Q

L

L

X

X

L

L

H

H

H

L

H

L

L

L

H

L

X

Q0

H

X

X

X

Z

SN74ALS876A, SN74AS876

(each flip-flop)

INPUTS

OUTPUT

OE

PRE

CLK

D

Q

L

L

X

X

L

L

H

H

L

L

H

L

H

L

H

L

X

Q0

H

X

X

X

Z

logic symbols

1OE

23

1CLK

EN

2

C1

SN54ALS874B, SN74ALS874B, SN74AS874

1CLR

R

1

1D

3

1D1

4

1D2

5

1D3

6

1D4

1Q1

22

1Q2

21

1Q3

20

1Q4

19

2OE

14

2CLK

EN

11

C1

2CLR

R

13

1D

7

2D1

8

2D2

9

2D3

10

2D4

2Q1

18

2Q2

17

2Q3

16

2Q4

15

1OE

23

1CLK

EN

2

C1

SN74ALS876A, SN74AS876

1PRE

S

1

1D

3

1D1

4

1D2

5

1D3

6

1D4

22

21

20

19

2OE

14

2CLK

EN

11

C1

2PRE

S

13

1D

7

2D1

8

2D2

9

2D3

10

2D4

18

17

16

15

1Q1

1Q2

1Q3

1Q4

2Q1

2Q2

2Q3

2Q4

† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, JT, and NT packages.

background image

 SN54ALS874B, SN74ALS874B, SN74ALS876A

 SN74AS874, SN74AS876

 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS

 SDAS061C – APRIL 1982 – REVISED JANUARY 1995

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagrams (positive logic)

R

C1

1D

D1

Q1

R

C1

1D

D2

Q2

R

C1

1D

D3

Q3

R

C1

1D

D4

Q4

OE

CLK

CLR

SN54ALS874B, SN74ALS874B, SN74AS874

(each quad flip-flop)

S

C1

1D

D1

Q1

S

C1

1D

D2

Q2

S

C1

1D

D3

Q3

S

C1

1D

D4

Q4

OE

CLK

PRE

SN74ALS876A, SN74AS876

(each quad flip-flop)

Pin numbers shown are for the DW, JT, and NT packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

CC

 

 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage, V

I

 

 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage applied to a disabled 3-state output 

 5.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range, T

A

: SN54ALS874B  

– 55

°

C to 125

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74ALS874B, SN74ALS876A 

 0

°

C to 70

°

C

. . . . . . . . . . . . . . . . . 

Storage temperature range 

 – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

background image

SN54ALS874B, SN74ALS874B, SN74ALS876A

SN74AS874, SN74AS876

DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SDAS061C – APRIL 1982 – REVISED JANUARY 1995

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions

SN54ALS874B

SN74ALS874B

SN74ALS876A

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

VCC

Supply voltage

4.5

5

5.5

4.5

5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.7

0.8

V

IOH

High-level output current

– 1

– 2.6

mA

IOL

Low-level output current

12

24

mA

fclock

Clock frequency

0

25

0

30

MHz

PRE or CLR low

15

10

tw

Pulse duration

CLK high

20

16.5

ns

CLK low

20

16.5

t

Set p time before CLK

Data

15

15

ns

tsu

Setup time before CLK

PRE or CLR inactive

15

10

ns

th

Hold time, data after CLK

4

0

ns

TA

Operating free-air temperature

– 55

125

0

70

°

C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

SN54ALS874B

SN74ALS874B

SN74ALS876A

UNIT

MIN

TYP†

MAX

MIN

TYP†

MAX

VIK

VCC = 4.5 V,

II = – 18 mA

– 1.2

– 1.2

V

VCC = 4.5 V to 5.5 V,

IOH = – 0.4 mA

VCC  – 2

VCC  – 2

VOH

VCC = 4 5 V

IOH = – 1 mA

2.4

3.3

V

VCC = 4.5 V

IOH = – 2.6 mA

2.4

3.2

VOL

VCC = 4 5 V

IOL = 12 mA

0.25

0.4

0.25

0.4

V

VOL

VCC = 4.5 V

IOL = 24 mA

0.35

0.5

V

IOZH

VCC = 5.5 V,

VO = 2.7 V

20

20

µ

A

IOZL

VCC = 5.5 V,

VO = 0.4 V

– 20

– 20

µ

A

II

VCC = 5.5 V,

VI = 7 V

0.1

0.1

mA

IIH

VCC = 5.5 V,

VI = 2.7 V

20

20

µ

A

IIL

VCC = 5.5 V,

VI = 0.4 V

– 0.2

– 0.2

mA

IO‡

VCC = 5.5 V,

VO = 2.25 V

– 20

– 112

– 30

– 112

mA

Outputs high

14

21

14

21

ALS874B

VCC = 5.5 V

Outputs low

19

30

19

30

ICC

Outputs disabled

20

32

20

32

mA

ICC

Outputs high

14

21

mA

SN74ALS876A

VCC = 5.5 V

Outputs low

18

29

Outputs disabled

20

31

† All typical values are at VCC = 5 V, TA = 25

°

C.

‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

background image

 SN54ALS874B, SN74ALS874B, SN74ALS876A

 SN74AS874, SN74AS876

 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS

 SDAS061C – APRIL 1982 – REVISED JANUARY 1995

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

R1 = 500 

,

R2 = 500 

,

TA = MIN to MAX†

UNIT

SN54ALS874B

SN74ALS874B

MIN

MAX

MIN

MAX

fmax

25

30

MHz

tPLH

CLK

An Q

4

18

4

14

ns

tPHL

CLK

Any Q

4

16

4

14

ns

tPHL

CLR

Any Q

5

23

5

17

ns

tPZH

OE

An Q

4

24

4

18

ns

tPZL

OE

Any Q

4

21

4

18

ns

tPHZ

OE

Any Q

2

15

2

10

ns

tPLZ

OE

Any Q

3

22

3

12

ns

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

switching characteristics (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

R1 = 500 

,

R2 = 500 

,

TA = MIN to MAX†

UNIT

SN74ALS876A

MIN

MAX

fmax

30

MHz

tPLH

CLK

An Q

4

14

ns

tPHL

CLK

Any Q

4

14

ns

tPHL

PRE

Any Q

6

19

ns

tPZH

OE

An Q

4

18

ns

tPZL

OE

Any Q

4

18

ns

tPHZ

OE

Any Q

2

10

ns

tPLZ

OE

Any Q

3

13

ns

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

CC

 

 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage, V

I

 

 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range, T

A

: SN74AS874, SN74AS876 

 0

°

C to 70

°

C

. . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range 

 – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

background image

SN54ALS874B, SN74ALS874B, SN74ALS876A

SN74AS874, SN74AS876

DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SDAS061C – APRIL 1982 – REVISED JANUARY 1995

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions

SN74AS874

SN74AS876

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.5

5

5.5

4.5

5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

IOH

High-level output current

– 15

– 15

mA

IOL

Low-level output current

48

48

mA

fclock

Clock frequency

0

125

0

80

MHz

PRE or CLR low

2

4.5

tw

Pulse duration

CLK high

3

6.2

ns

CLK low

4

6.2

t

Set p time before CLK

Data

2

4.5

ns

tsu

Setup time before CLK

PRE or CLR inactive

4

5

ns

th

Hold time, data after CLK

1

2

ns

TA

Operating free-air temperature

0

70

0

70

°

C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

SN74AS874

SN74AS876

UNIT

MIN

TYP†

MAX

VIK

VCC = 4.5 V,

II = – 18 mA

– 1.2

V

VOH

VCC = 4.5 V to 5.5 V,

IOH = – 2 mA

VCC  – 2

V

VOH

VCC = 4.5 V,

IOH = – 15 mA

2.4

3.3

V

VOL

VCC = 4.5 V,

IOL = 48 mA

0.35

0.5

V

IOZH

VCC = 5.5 V,

VO = 2.7 V

50

µ

A

IOZL

VCC = 5.5 V,

VO = 0.4 V

– 50

µ

A

II

VCC = 5.5 V,

VI = 7 V

0.1

mA

IIH

VCC = 5.5 V,

VI = 2.7 V

20

µ

A

IIL

D

VCC = 5 5 V

VI = 0 4 V

– 2

mA

IIL

All others

VCC = 5.5 V,

VI = 0.4 V

– 0.5

mA

IO‡

VCC = 5.5 V,

VO = 2.25 V

– 30

– 112

mA

Outputs high

82

133

SN74AS874

VCC = 5.5 V

Outputs low

92

149

ICC

Outputs disabled

100

160

mA

ICC

Outputs high

88

142

mA

SN74AS876

VCC = 5.5 V

Outputs low

94

150

Outputs disabled

100

160

† All typical values are at VCC = 5 V, TA = 25

°

C.

‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

background image

 SN54ALS874B, SN74ALS874B, SN74ALS876A

 SN74AS874, SN74AS876

 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS

 SDAS061C – APRIL 1982 – REVISED JANUARY 1995

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

R1 = 500 

,

R2 = 500 

,

TA = MIN to MAX†

UNIT

SN74AS874

MIN

MAX

fmax

125

MHz

tPLH

CLK

An Q

3

8.5

ns

tPHL

CLK

Any Q

4

10.5

ns

tPHL

CLR

Any Q

4

9.5

ns

tPZH

OE

An Q

2

7

ns

tPZL

OE

Any Q

3

10.5

ns

tPHZ

OE

Any Q

2

6

ns

tPLZ

OE

Any Q

2

7.5

ns

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

switching characteristics (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

R1 = 500 

,

R2 = 500 

,

TA = MIN to MAX†

UNIT

SN74AS876

MIN

MAX

fmax

80

MHz

tPLH

CLK

An Q

3

8.5

ns

tPHL

CLK

Any Q

4

10.5

ns

tPHL

PRE

Any Q

4

9.5

ns

tPZH

OE

An Q

2

7

ns

tPZL

OE

Any Q

3

11

ns

tPHZ

OE

Any Q

2

7

ns

tPLZ

OE

Any Q

2

7

ns

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

background image

SN54ALS874B, SN74ALS874B, SN74ALS876A

SN74AS874, SN74AS876

DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SDAS061C – APRIL 1982 – REVISED JANUARY 1995

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/ 74ALS AND 54AS/ 74AS DEVICES

tPHZ

tPLZ

tPHL

tPLH

0.3 V

tPZL

tPZH

tPLH

tPHL

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

From Output

Under Test

Test 

Point

R1

S1

CL

(see Note A)

7 V

1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

th

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

High-Level

Pulse

Low-Level

Pulse

tw

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

Out-of-Phase

Output

(see Note C)

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

VOL

VOH

VOH

VOL

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

[

0 V

VOH

VOL

[

3.5 V

In-Phase

Output

0.3 V

1.3 V

1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

R2

VCC

RL

Test 

Point

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR 

BI-STATE

TOTEM-POLE OUTPUTS

From Output

Under Test

Test 

Point

CL

(see Note A)

RL

RL = R1 = R2

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. When measuring propagation delay items of 3-state outputs, switch S1 is open.

D. All input pulses have the following characteristics: PRR 

 1 MHz, tr = tf = 2 ns, duty cycle = 50%.

E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

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