background image

 

SN54AHC574, SN74AHC574

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

 

SCLS244G – OCTOBER 1995 – REVISED JANUARY 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Operating Range 2-V to 5.5-V V

CC

D

3-State Outputs Drive Bus Lines Directly

D

Latch-Up Performance Exceeds 250 mA Per

JESD 17

D

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Very Small-Outline (DGV), Thin

Shrink Small-Outline (PW), and Ceramic

Flat (W) Packages, Ceramic Chip Carriers

(FK), and Standard Plastic (N) and Ceramic

(J) DIPs

description

The ’AHC574 devices are octal edge-triggered

D-type flip-flops that feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. These devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

On the positive transition of the clock (CLK) input,

the Q outputs are set to the logic levels of the data

(D) inputs.

A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low) or the

high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

The high-impedance state and the increased drive provide the capability to drive bus lines without interface or

pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V

CC

 through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54AHC574 is characterized for operation over the full military temperature range of –55

°

C to 125

°

C. The

SN74AHC574 is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

SN54AHC574 . . . J  OR  W  PACKAGE

SN74AHC574 . . . DB, DGV, DW, N, OR PW PACKAGE

(TOP VIEW)

 SN54AHC574 . . . FK PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1D

2D

3D

4D

5D

6D

7D

8D

GND

V

CC

1Q

2Q

3Q

4Q

5Q

6Q

7Q

8Q

CLK

3

2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

2Q

3Q

4Q

5Q

6Q

3D

4D

5D

6D

7D

2D

1D

OE

8Q

7Q

1Q

8D

GND

CLK

V

CC

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

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SN54AHC574, SN74AHC574

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

 

SCLS244G – OCTOBER 1995 – REVISED JANUARY 2000

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

OE

CLK

D

Q

L

H

H

L

L

L

L

H or L

X

Q0

H

X

X

Z

logic symbol

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

OE

1D

2

1D

3

2D

4

3D

5

4D

6

5D

11

CLK

1Q

19

2Q

18

3Q

17

4Q

16

5Q

15

6Q

14

7Q

13

8Q

12

7

6D

8

7D

9

8D

EN

1

C1

logic diagram (positive logic)

OE

CLK

1D

1Q

To Seven Other Channels

C1

1

11

2

19

1D

background image

SN54AHC574, SN74AHC574

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

 

SCLS244G – OCTOBER 1995 – REVISED JANUARY 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 (see Note 1) 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage range, V

O

 (see Note 1) 

–0.5 V to V

CC 

+ 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK 

(V

< 0) 

–20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK 

(V

< 0 or V

O

 > V

CC

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

(V

= 0 to V

CC

±

25 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through V

CC

 or GND 

±

75 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA

 (see Note 2): DB package 

70

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DGV package 

92

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

DW package 

58

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

N package 

69

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

PW package 

83

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 3)

SN54AHC574

SN74AHC574

UNIT

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

2

5.5

2

5.5

V

VCC = 2 V

1.5

1.5

VIH

High-level input voltage

VCC = 3 V

2.1

2.1

V

VCC = 5.5 V

3.85

3.85

VCC = 2 V

0.5

0.5

VIL

Low-level input voltage

VCC = 3 V

0.9

0.9

V

VCC = 5.5 V

1.65

1.65

VI

Input voltage

0

5.5

0

5.5

V

VO

Output voltage

0

VCC

0

VCC

V

VCC = 2 V

–50

–50

m

A

IOH

High-level output current

VCC = 3.3 V 

±

 0.3 V

–4

–4

mA

VCC = 5 V 

±

0.5 V

–8

–8

mA

VCC = 2 V

50

50

m

A

IOL

Low-level output current

VCC = 3.3 V 

±

 0.3 V

4

4

mA

VCC = 5 V 

±

0.5 V

8

8

mA

t

/∆

v

Input transition rise or fall rate

VCC = 3.3 V 

±

 0.3 V

100

100

ns/V

t

/∆

v

Input transition rise or fall rate

VCC = 5 V 

±

0.5 V

20

20

ns/V

TA

Operating free-air temperature

–55

125

–40

85

°

C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

background image

SN54AHC574, SN74AHC574

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

 

SCLS244G – OCTOBER 1995 – REVISED JANUARY 2000

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25

°

C

SN54AHC574

SN74AHC574

UNIT

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

1.9

2

1.9

1.9

IOH = –50 

m

A

3 V

2.9

3

2.9

2.9

VOH

4.5 V

4.4

4.5

4.4

4.4

V

OH

IOH = –4 mA

3 V

2.58

2.48

2.48

IOH = –8 mA

4.5 V

3.94

3.8

3.8

2 V

0.1

0.1

0.1

IOL = 50 

m

A

3 V

0.1

0.1

0.1

VOL

4.5 V

0.1

0.1

0.1

V

OL

IOL = 4 mA

3 V

0.36

0.5

0.44

IOL = 8 mA

4.5 V

0.36

0.5

0.44

II

VI = VCC or GND

0 V to 5.5 V

±

0.1

±

1*

±

1

m

A

IOZ

VO = VCC or GND

5.5 V

±

0.25

±

2.5

±

2.5

m

A

ICC

VI = VCC or GND,

IO = 0

5.5 V

4

40

40

m

A

Ci

VI = VCC or GND

5 V

3

10

10

pF

Co

VO = VCC or GND

5 V

3

pF

* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.

timing requirements over recommended operating free-air temperature range,

V

CC

 = 3.3 V 

±

 0.3 V (unless otherwise noted) (see Figure 1)

TA = 25

°

C

SN54AHC574

SN74AHC574

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tw

Pulse duration, CLK high or low

5

5

5

ns

tsu

Setup time, data before CLK

3.5

3.5

3.5

ns

th

Hold time, data after CLK

1.5

1.5

1.5

ns

timing requirements over recommended operating free-air temperature range,

V

CC

 = 5 V 

±

 0.5 V (unless otherwise noted) (see Figure 1)

TA = 25

°

C

SN54AHC574

SN74AHC574

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tw

Pulse duration, CLK high or low

5

5

5

ns

tsu

Setup time, data before CLK

3

3

3

ns

th

Hold time, data after CLK

1.5

1.5

1.5

ns

background image

SN54AHC574, SN74AHC574

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

 

SCLS244G – OCTOBER 1995 – REVISED JANUARY 2000

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range,

V

CC 

= 3.3 V

±

0.3 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

LOAD

TA = 25

°

C

SN54AHC574

SN74AHC574

UNIT

PARAMETER

(INPUT)

(OUTPUT)

CAPACITANCE

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

f

CL = 15 pF

80*

125*

65*

65

MHz

fmax

CL = 50 pF

50

75

45

45

MHz

tPLH

CLK

Q

CL = 15 pF

8.5*

13.2*

1*

15.5*

1

15.5

ns

tPHL

CLK

Q

CL = 15 pF

8.5*

13.2*

1*

15.5*

1

15.5

ns

tPZH

OE

Q

CL = 15 pF

8.2*

12.8*

1*

15*

1

15

ns

tPZL

OE

Q

CL = 15 pF

8.2*

12.8*

1*

15*

1

15

ns

tPHZ

OE

Q

CL = 15 pF

8.5*

13*

1*

15*

1

15

ns

tPLZ

OE

Q

CL = 15 pF

8.5*

13*

1*

15*

1

15

ns

tPLH

CLK

Q

CL = 50 pF

11

16.7

1

19

1

19

ns

tPHL

CLK

Q

CL = 50 pF

11

16.7

1

19

1

19

ns

tPZH

OE

Q

CL = 50 pF

10.7

16.3

1

18.5

1

18.5

ns

tPZL

OE

Q

CL = 50 pF

10.7

16.3

1

18.5

1

18.5

ns

tPHZ

OE

Q

CL = 50 pF

11

15

1

17

1

17

ns

tPLZ

OE

Q

CL = 50 pF

11

15

1

17

1

17

ns

tsk(o)

CL = 50 pF

1.5**

1.5

ns

 On products compliant to MIL-PRF-38535, this parameter is not production tested.

∗∗

 On products compliant to MIL-PRF-38535, this parameter does not apply.

switching characteristics over recommended operating free-air temperature range,

V

CC 

= 5 V

±

0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

LOAD

TA = 25

°

C

SN54AHC574

SN74AHC574

UNIT

PARAMETER

(INPUT)

(OUTPUT)

CAPACITANCE

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

f

CL = 15 pF

130*

180*

110*

110

MHz

fmax

CL = 50 pF

85

115

75

75

MHz

tPLH

CLK

Q

CL = 15 pF

5.6*

8.6*

1*

10*

1

10

ns

tPHL

CLK

Q

CL = 15 pF

5.6*

8.6*

1*

10*

1

10

ns

tPZH

OE

Q

CL = 15 pF

5.9*

9*

1*

10.5*

1

10.5

ns

tPZL

OE

Q

CL = 15 pF

5.9*

9*

1*

10.5*

1

10.5

ns

tPHZ

OE

Q

CL = 15 pF

5.5*

9*

1*

10.5*

1

10.5

ns

tPLZ

OE

Q

CL = 15 pF

5.5*

9*

1*

10.5*

1

10.5

ns

tPLH

CLK

Q

CL = 50 pF

7.1

10.6

1

12

1

12

ns

tPHL

CLK

Q

CL = 50 pF

7.1

10.6

1

12

1

12

ns

tPZH

OE

Q

CL = 50 pF

7.4

11

1

12.5

1

12.5

ns

tPZL

OE

Q

CL = 50 pF

7.4

11

1

12.5

1

12.5

ns

tPHZ

OE

Q

CL = 50 pF

7.1

10.1

1

11.5

1

11.5

ns

tPLZ

OE

Q

CL = 50 pF

7.1

10.1

1

11.5

1

11.5

ns

tsk(o)

CL = 50 pF

1**

1

ns

 On products compliant to MIL-PRF-38535, this parameter is not production tested.

∗∗

 On products compliant to MIL-PRF-38535, this parameter does not apply.

background image

SN54AHC574, SN74AHC574

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

 

SCLS244G – OCTOBER 1995 – REVISED JANUARY 2000

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

noise characteristics, V

CC 

= 5 V, C

L

 = 50 pF, T

A

 = 25

°

C (see Note 4)

PARAMETER

SN74AHC574

UNIT

PARAMETER

MIN

MAX

UNIT

VOL(P)

Quiet output, maximum dynamic VOL

0.8

V

VOL(V)

Quiet output, minimum dynamic VOL

–0.8

V

VOH(V)

Quiet output, minimum dynamic VOH

4.2

V

VIH(D)

High-level dynamic input voltage

3.5

V

VIL(D)

Low-level dynamic input voltage

1.5

V

NOTE 4: Characteristics are for surface-mount packages only.

operating characteristics, V

CC 

= 5 V, T

A

 = 25

°

C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

No load,

f = 1 MHz

28

pF

background image

SN54AHC574, SN74AHC574

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

 

SCLS244G – OCTOBER 1995 – REVISED JANUARY 2000

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

50% VCC

VCC

VCC

0 V

0 V

th

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

VCC

0 V

50% VCC

50% VCC

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

50% VCC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

Waveform 1

S1 at VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VCC

0 V

50% VCC

VOL

 

+ 0.3 V

50% VCC

0 V

VCC

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open Drain

Open

VCC

GND

VCC

TEST

S1

VCC

0 V

50% VCC

tw

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 

 1 MHz, ZO = 50 

, tr 

3 ns, tf 

 3 ns.

D. The outputs are measured one at a time with one input transition per measurement.

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

S1

VCC

RL = 1 k

GND

From Output

Under Test

CL

(see Note A)

Test

Point

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

50% VCC

VOH –

 

0.3 V

Figure 1. Load Circuit and Voltage Waveforms

background image

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any product or service without notice, and advise customers to obtain the latest version of relevant information

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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Copyright 

©

 2000, Texas Instruments Incorporated