background image

 

SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident

D

Read and Write Operations Synchronized

to Independent System Clocks

D

Input-Ready Flag Synchronized to Write

Clock

D

Output-Ready Flag Synchronized to Read

Clock

D

512 Words by 18 Bits

D

Low-Power Advanced CMOS Technology

D

Half-Full Flag and Programmable

Almost-Full/Almost-Empty Flag

D

Bidirectional Configuration and Width

Expansion Without Additional Logic

D

Fast Access Times of 12 ns With a 50-pF

Load and All Data Outputs Switching

Simultaneously

D

Data Rates up to 67 MHz

D

Pin-to-Pin Compatible With SN74ACT7805

and SN74ACT7813

D

Packaged in Shrink Small-Outline 300-mil

Package Using 25-mil Center-to-Center

Spacing

description

The SN74ACT7803 is a 512-word 

×

18-bit FIFO

suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering

without additional logic. Multiple distributed V

CC

 and GND pins, along with Texas Instruments patented output

edge control (OEC

) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.

Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input

ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low

and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,

regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output

buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four

WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes

the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be

reset upon power up.

The SN74ACT7803 is characterized for operation from 0

°

C to 70

°

C.

Copyright 

©

 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Widebus and OEC are trademarks of Texas Instruments Incorporated.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

RESET

D17

D16

D15

D14

D13

D12

D11

D10

V

CC

D9

D8

GND

D7

D6

D5

D4

D3

D2

D1

D0

HF

PEN

AF/AE

WRTCLK

WRTEN2

WRTEN1

IR

OE1

Q17

Q16

Q15

GND

Q14

V

CC

Q13

Q12

Q11

Q10

Q9

GND

Q8

Q7

Q6

Q5

V

CC

Q4

Q3

Q2

GND

Q1

Q0

RDCLK

RDEN

OE2

OR

DL PACKAGE

(TOP VIEW)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

WRTEN

&

RDEN

&

0

21

D0

20

D1

19

D2

18

D3

17

D4

16

D5

15

D6

14

D7

12

D8

Q0

33

0

Q1

34

Q2

36

Q3

37

Q4

38

IR

28

IN RDY

HF

22

HALF-FULL

AF/AE

24

ALMOST FULL/EMPTY

OR

29

OUT RDY

Q5

40

Q6

41

Q7

42

Q8

43

Data

1    

11

D9

9

D10

8

D11

7

D12

6

D13

5

D14

4

D15

3

D16

17

2

D17

Q9

45

Q10

46

Q11

47

Q12

48

Q13

49

Q14

51

Q15

53

Q16

54

Q17

55

17

RESET

WRTEN2

OE1

OE2

RDEN

30

EN1

&

56

PEN

RESET

1

25

WRTCLK

WRTCLK

Data

27

WRTEN1

26

PROGRAM ENABLE

23

31

32

RDCLK

RDCLK

Φ

FIFO 512 

×

 18

SN74ACT7803

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

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SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

functional block diagram

Q0–Q17

IR

AF/AE

HF

Register

512 

×

 18 RAM

OE2

D0–D17

RDCLK

OE1

RDEN

WRTCLK

WRTEN1

WRTEN2

RESET

PEN

Synchronous

Read

Control

Synchronous

Write

Control

Reset

Logic

Read

Pointer

Write

Pointer

Status-

Flag

Logic

Location 1

Location 2

Location 511

Location 512

Output

Control

OR

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SN74ACT7803

512 

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SCAS191C – MARCH 1991 – REVISED APRIL 1998

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AF/AE

24

O

Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE, or the default value

of 64 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when

memory contains X or fewer words or (512 – Y) or more words. AF/AE is high after reset.

D0–D17

2–9, 11–12,

14–21

I

18-bit data input port

HF

22

O

Half-full flag. HF is high when the FIFO memory contains 256 or more words. HF is low after reset.

IR

28

O

Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO

is full and writes are disabled. IR is low during reset and goes high on the second low-to-high transition

of WRTCLK after reset.

OE1

OE2

56

30

I

Output enables. When OE1, OE2, and RDEN are low and OR is high, data is read from the FIFO on

a low-to-high transition of RDCLK. When either OE1 or OE2 is high, reads are disabled and the data

outputs are in the high-impedance state.

OR

29

O

Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the

FIFO is empty and reads are disabled. Ready data is present on Q0–Q17 when OR is high. OR is low

during reset and goes high on the third low-to-high transition of RDCLK after the first word is loaded

to empty memory.

PEN

23

I

Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7

is latched as an AF/AE offset value when PEN is low and WRTCLK is high.

Q0–Q17

33–34, 36–38,

40–43, 45–49,

51, 53–55

O

18-bit data output port. After the first valid write to empty memory, the first word is output on Q0–Q17

on the third rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When

OR is low, the last word read from the FIFO is present on Q0–Q17.

RDCLK

32

I

Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A

low-to-high transition of RDCLK reads data from memory when OE1, OE2, and RDEN are low and OR

is high. OR is synchronous to the low-to-high transition of RDCLK.

RDEN

31

I

Read enable. When RDEN, OE1, and OE2 are low and OR is high, data is read from the FIFO on the

low-to-high transition of RDCLK.

RESET

1

I

Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of

WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high.

WRTCLK

25

I

Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A

low-to-high transition of WRTCLK writes data to memory when WRTEN2 is low, WRTEN1 is high, and

IR is high. IR is synchronous to the low-to-high transition of WRTCLK.

WRTEN1

WRTEN2

27

26

I

Write enables. When WRTEN1 is high, WRTEN2 is low, and IR is high, data is written to the FIFO on

a low-to-high transition of WRTCLK.

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SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

1

2

3

4

1

2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Don’t Care

Don’t Care

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Don’t Care

1

2

3

4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Don’t Care

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Don’t Care

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Don’t Care

Invalid

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ

Don’t Care

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

Don’t Care

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

Don’t Care

ÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Don’t Care

RESET

WRTCLK

PEN

WRTEN1

WRTEN2

D0–D17

RDCLK

OE1

OE2

RDEN

Q0–Q17

OR

AF/AE

HF

IR

Define the AF/AE Flag Using the

Default Value of X = Y = 64

Figure 1. Reset Cycle

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SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

1

2

3

Invalid

RESET

WRTCLK

PEN

WRTEN1

WRTEN2

D0–D17

RDCLK

OE1

OE2

RDEN

Q0–Q17

OR

AF/AE

HF

IR

1

0

1

0

1

0

W1

W2

W3

W4

W(X+2)

W257

W(513–Y)

W513

1

0

1

0

1

0

W1

Figure 2. Write Cycle

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SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

W258

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

RESET

WRTCLK

PEN

WRTEN1

WRTEN2

D0–D17

RDCLK

OE1

OE2

RDEN

Q0–Q17

OR

AF/AE

HF

IR

1

0

1

0

1

0

W513

1

0

1

2

W1

W2

W3

W(Y+1)

W(Y+2)

W257

W(512–X)

W(513–X)

W512

W513

Figure 3. Read Cycle

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SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

offset values for AF/AE

The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset

value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the

offsets are not programmed, the default values of X = Y = 64 are used. The AF/AE flag is high when the FIFO

contains X or fewer words or (512 – Y) or more words.

Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR

is high and WRTCLK is low. On the following low-to-high transition of WRTCLK, the binary value on D0–D7 is

stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another

low-to-high transition of WRTCLK reprograms Y to the binary value on D0–D7 at the time of the second

WRTCLK low-to-high transition. When the offsets are being programmed, writes to the FIFO memory are

disabled, regardless of the state of the write enables (WRTEN1, WRTEN2). A maximum value of 255 can be

programmed for either X or Y (see Figure 4). To use the default values of X = Y = 64, PEN must be held high.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Î

Î

ÎÎÎÎÎÎ

ÎÎÎÎÎÎ

3

4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

RESET

WRTCLK

PEN

WRTEN1

WRTEN2

D0–D7

IR

X and Y

Y

Figure 4. Programming X and Y Separately

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range applied to a disabled 3-state output 

5.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA

 (see Note 1)

74

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.

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SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions

’ACT7803-15

’ACT7803-20

’ACT7803-25

’ACT7803-40

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

VCC

Supply voltage

4.5

5.5

4.5

5.5

4.5

5.5

4.5

5.5

V

VIH

High-level input voltage

2

2

2

2

V

VIL

Low-level input voltage

0.8

0.8

0.8

0.8

V

IOH

High-level output current

Q outputs, flags

–8

–8

–8

–8

mA

IOL

Low level output current

Q outputs

16

16

16

16

mA

IOL

Low-level output current

Flags

8

8

8

8

mA

TA

Operating free-air temperature

0

70

0

70

0

70

0

70

°

C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VOH

VCC = 4.5 V,

IOH = –8 mA

2.4

V

VOL

Flags

VCC = 4.5 V,

IOL = 8 mA

0.5

V

VOL

Q outputs

VCC = 4.5 V,

IOL = 16 mA

0.5

V

II

VCC = 5.5 V,

VI = VCC or 0

±

5

µ

A

IOZ

VCC = 5.5 V,

VO = VCC or 0

±

5

µ

A

ICC

VI = VCC – 0.2 V or 0

400

µ

A

ICC‡

VCC = 5.5 V,

One input at 3.4 V,

Other inputs at VCC or GND

1

mA

Ci

VI = 0,

f = 1 MHz

4

pF

Co

VO = 0,

f = 1 MHz

8

pF

† All typical values are at VCC = 5 V, TA = 25

°

C.

‡ This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

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SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

10

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

timing requirements over recommended operating conditions (see Figures 1 through 5)

’ACT7803-15

’ACT7803-20

’ACT7803-25

’ACT7803-40

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

67

50

40

25

MHz

WRTCLK high or low

6

7

8

12

tw

Pulse duration

RDCLK high or low

6

7

8

12

ns

PEN low

8

9

9

12

D0–D17 before WRTCLK

4

5

5

5

WRTEN1, WRTEN2

before WRTCLK

4

5

5

5

t

Setup time

OE1, OE2 before RDCLK

5

5

6

6

ns

tsu

Setup time

RDEN before RDCLK

4

5

5

5

ns

Reset: RESET low before first

WRTCLK

 and RDCLK

5

6

6

6

PEN before WRTCLK

5

6

6

6

D0–D17 after WRTCLK

0

0

0

0

WRTEN1, WRTEN2

after WRTCLK

0

0

0

0

th

Hold time

OE1, OE2, RDEN after RDCLK

0

0

0

0

ns

th

Hold time

Reset: RESET low after fourth

WRTCLK

 and RDCLK

2

2

2

2

ns

PEN high after WRTCLK

0

0

0

0

PEN low after WRTCLK

2

2

2

2

† To permit the clock pulse to be utilized for reset purposes

switching characteristics over recommended ranges of supply voltage and operating free-air

temperature, C

L

 = 50 pF (unless otherwise noted) (see Figure 5)

PARAMETER

FROM

TO

’ACT7803-15

’ACT7803-20

’ACT7803-25

’ACT7803-40

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP†

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

fmax

WRTCLK or

RDCLK

67

50

40

25

MHz

tpd

RDCLK

Any Q

4

9.5

12

4

13

4

15

4

20

ns

tpd‡

RDCLK

Any Q

8.5

ns

WRTCLK

IR

3

8.5

3

11

3

13

3

15

t d

RDCLK

OR

3

8.5

3

11

3

13

3

15

ns

tpd

WRTCLK

AF/AE

7

16.5

7

19

7

21

7

23

ns

RDCLK

AF/AE

7

17

7

19

7

21

7

23

tPLH

WRTCLK

HF

7

15

7

17

7

19

7

21

ns

tPHL

RDCLK

HF

7

15.5

7

18

7

20

7

22

ns

tPLH

RESET low

AF/AE

2

9

2

11

2

13

2

15

ns

tPHL

RESET low

HF

2

10

2

12

2

14

2

16

ns

ten

OE1, OE2

Any Q

2

8.5

2

11

2

11

2

11

ns

tdis

OE1, OE2

Any Q

2

9.5

2

11

2

14

2

14

ns

‡ This parameter is measured with a 30-pF load (see Figure 6).

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512 

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 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

11

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

operating characteristics, V

CC

 = 5 V, T

A

 = 25

°

C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

Outputs enabled

CL = 50 pF,

f = 5 MHz

53

pF

PARAMETER MEASUREMENT INFORMATION

VOH

VOL

th

tPLH

tPHL

Output

Control

Output

Waveform 1

S1 at 7 V

Output

Waveform 2

S1 at Open

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

1.5 V

1.5 V

3 V

0 V

1.5 V

1.5 V

VOH

VOL

0 V

1.5 V

VOL + 0.3 V

1.5 V

VOH – 0.3 V

0 V

1.5 V

3 V

0 V

1.5 V

1.5 V

0 V

3 V

0 V

1.5 V

1.5 V

tw

Input

3 V

3 V

3.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

S1

500 

LOAD CIRCUIT

500 

7 V

From Output

Under Test

Test

Point

NOTE A: CL includes probe and jig capacitance.

CL = 50 pF

(see Note A)

tsu

tPZH

tPZL

tPHZ

tPLZ

tPLH

tPHL

Open

Closed

Open

Closed

Open

Open

PARAMETER

S1

ten

tdis

tpd

Figure 5. Load Circuit and Voltage Waveforms

background image

SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

12

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 6

PROPAGATION DELAY TIME

vs

LOAD CAPACITANCE

50

100

200

250

150

300

pd

CL – Load Capacitance – pF

t

VCC = 5 V 

TA = 25

°

RL = 500 

0

typ + 8

typ + 6

typ + 4

typ + 2

typ

typ – 2

– Propagation Delay T

ime – ns

Figure 7

60

20

160

0

0

10

20

30

40

– Supply Current – mA

120

80

140

SUPPLY CURRENT

vs

CLOCK FREQUENCY

200

50

60

70

180

100

40

VCC = 5 V

VCC = 4.5 V

fclock – Clock Frequency – MHz

CC(f)

I

VCC = 5.5 V

TA = 75

°

C

CL = 0 pF

5

4

2

1

0

3

0

10

20

30

40

50

60

6

70

f – Frequency – MHz

7

8

9

Slope = 0.12

VCC = 4.5 V

VCC = 5 V

VCC = 5.5 V

TA = 25

°

I

CC(I)

– Idle I

CC

– mA

Figure 8. SN74ACT7803 Idle I

CC

 With RDCLK or WRTCLK Switching

background image

SN74ACT7803

512 

×

 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

 

 

SCAS191C – MARCH 1991 – REVISED APRIL 1998

13

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

WRTCLK

WRTEN1

RDCLK

SN74ACT7803

WRTEN2

OE1

RDEN

WRTCLK

WRTEN1

RDCLK

WRTEN2

OE1

RDEN

A0–A17

CLOCK A

W/RA

CSA

CLOCK B

W/RB

CSB

B0–B17

OE2

OE2

SN74ACT7803

D0–D17

D0–D17

Q0–Q17

Q0–Q17

18

18

Figure 9. Bidirectional Configuration

IR

RDCLK

OR

WRTCLK

WRTEN1

WRTEN2

D0–D35

OE1

WRTCLK

WRTEN1

IR

RDCLK

OR

WRTEN2

RDEN

OE1

WRTCLK

WRTEN1

IR

RDCLK

OR

WRTEN2

OE1

RDEN

OE2

OE2

SN74ACT7803

SN74ACT7803

D0–D17

D0–D17

Q0–Q17

Q0–Q17

Q0–Q35

OE2

36

36

Figure 10. Word-Width Expansion: 512 

×

 36 Bits

background image

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©

 1999, Texas Instruments Incorporated