background image

1

Data sheet acquired from Harris Semiconductor

SCHS222

Features

• Independent Asynchronous Inputs and Outputs

• Expandable in Either Direction

• Reset Capability

• Status Indicators on Inputs and Outputs

• Three-State Outputs

• Shift-Out Independent of Three-State Control

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs  . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range  . . . -55

o

C to 125

o

C

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

 = 30%, N

IH

 = 30% of V

CC

at V

CC

 = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

IL

= 0.8V (Max), V

IH

 = 2V (Min)

- CMOS Input Compatibility, I

l

1

µ

A at V

OL

, V

OH

Applications

• Bit-Rate Smoothing

• CPU/Terminal Buffering

• Data Communications

• Peripheral Buffering

• Line Printer Input Buffers

• Auto-Dialers

• CRT Buffer Memories

• Radar Data Acquisition

Description

The Harris CD74HC40105 and CD74HCT40105 are high-

speed silicon-gate CMOS devices that are compatible,

except for “shift-out” circuitry, with the Harris CD40105B.

They are low-power first-in-out (FIFO) “elastic” storage

registers that can store 16 four-bit words. The 40105 is

capable of handling input and output data at different shifting

rates. This feature makes particularly useful as a buffer

between asynchronous systems.

Each work position in the register is clocked by a control flip-

flop, which stores a marker bit. A “1” signifies that the posi-

tion’s data is filled and a “0” denotes a vacancy in that posi-

tion. The control flip-flop detects the state of the preceding

flip-flop and communicates its own status to the succeeding

flip-flop. When a control flip-flop is in the “0” state and sees a

“1” in the preceeding flip-flop, it generates a clock pulse that

transfers data from the preceding four data latches into its

own four data latches and resets the preceding flip-flop to

“0”. The first and last control flip-flops have buffered outputs.

Since all empty locations “bubble” automatically to the input

end, and all valid data ripple through to the output end, the

status of the first control flip-flop (DATA-IN READY) indicates

if the FIFO is full, and the status of the last flip-flop (DATA-

OUT READY) indicates if the FIFO contains data. As the

earliest data are removed from the bottom of the data stack

(the output end), all data entered later will automatically

propagate (ripple) toward the output.

Ordering Information

PART NUMBER

TEMP. RANGE

(

o

C)

PACKAGE

PKG. NO.

CD74HC40105E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT40105E

-55 to 125

16 Ld PDIP

E16.3

CD74HC40105M

-55 to 125

16 Ld SOIC

M16.15

CD74HCT40105M

-55 to 125

16 Ld SOIC

M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all

electrical specifications. Please contact your local sales office or

Harris customer service for ordering information.

February 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

 ©

 Harris Corporation 1998

File Number

1834.1

CD74HC40105,

CD74HCT40105

High Speed CMOS Logic

4-Bit x 16-Word FIFO Register

[ /Title

(CD74

HC401

05,

CD74

HCT40

105)

/Sub-

ject

(High

Speed

CMOS

background image

2

Pinout

CD74HC40105, CD74HCT40105

(PDIP, SOIC)

TOP VIEW

Loading Data

Data can be entered whenever the DATA-IN READY (DIR)

flag is high, by a low to high transition on the SHIFT-IN (SI)

input. This input must go low momentarily before the next

word is accepted by the FIFO. The DIR flag will go low

momentarily, until the data have been transferred to the sec-

ond location. The flag will remain low when all 16-word loca-

tions are filled with valid data, and further pulses on the SI

input will be ignored until DIR goes high.

Unloading Data

As soon as the first word has rippled to the output, the data-

out ready output (DOR) goes HIGH and data of the first word

is available on the outputs. Data of other words can be

removed by a negative-going transition on the shift-out input

(SO). This negative-going transition causes the DOR signal

to go LOW while the next word moves to the output. As long

as valid data is available in the FIFO, the DOR signal will go

high again, signifying that the next word is ready at the

output. When the FIFO is empty, DOR will remain LOW, and

any further commands will be ignored until a “1” marker

ripples down to the last control register and DOR goes

HIGH. If during unloading SI is HIGH, (FIFO is full) data on

the data input of the FIFO is entered in the first location.

Master Reset

A high on the MASTER RESET (MR) sets all the control

logic marker bits to “0”. DOR goes low and DIR goes high.

The contents of the data register are not changed, only

declared invalid, and will be superseded when the first word

is loaded. Thus, MR does not clear data within the register

but only the control logic. If the shift-in flag (SI) is HIGH

during the master reset pulse, data present at the input (D0

to D3) are immediately moved into the first location upon

completion of the reset process.

Three-State Outputs

In order to facilitate data busing, three-state outputs (Q0 to

Q3) are provided on the data output lines, while the load

condition of the register can be detected by the state of the

DOR output. A HIGH on the three-state control flag (output

enable input OE) forces the outputs into the high-impedance

OFF-state mode. Note that the shift-out signal, unlike that in

the Harris CD40105B, is independent of the three-state

output control. In the CD40105B, the three-state control

must not be shifted from High to Low when the shift-out

signal is Low (data loss would occur). In the high-speed

CMOS version this restriction has been eliminated.

Cascading

The 40105 can be cascaded to form longer registers simply

by connecting the DIR to SO and DOR to SI. In the cascaded

mode, a MASTER RESET pulse must be applied after the

supply voltage is turned on. For words wider than four bits, the

DIR and the DOR outputs must be gated together with AND

gates. Theri outputs drive the SI and SO inputs in parallel, if

expanding is done in both directions (see Figures 12 and 13).

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

THREE-STATE

DIR

SI

D0

D1

D2

GND

D3

V

CC

DOR

Q0

Q1

Q2

Q3

MR

SO

CONTROL

STATE

Q0

Q1

Q2

Q3

CONTROL

D0

D1

D2

D3

SHIFT OUT

4

1

5

6

7

3

15

13

12

11

10

MASTER

9

SHIFT IN

RESET

14

2

DATA-OUT

DATA-IN

READY

READY

GND = 8

V

CC

= 16

THREE-

CD74HC40105, CD74HCT40105

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3

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM

4 x 16

DATA

REGISTER

4

5

6

7

D0

D1

D2

D3

13

12

11

10

Q0

Q1

Q2

Q3

1

THREE-STATE CONTROL

DATA-OUT READY (DOR)

2

CONTROL LOGIC

14

3

15

SHIFT OUT (SO)

9

MASTER

RESET

(MR)

DATA-IN READY (DIR)

SHIFT IN (SI)

INPUT

BUFFERS

OUTPUT

BUFFERS

CD74HC40105, CD74HCT40105

background image

4

“S” overrides “R”.

††

“R” overrides “S”.

FIGURE 2. LOGIC DIAGRAM

MR

9

3

SI

R Q

Q

S

F/F1

R Q

Q

S

† †

2

4

5

6

7

DIR

D0

D1

D2

D3

CL

CL

POSITION 1

L1

4

LATCHES

R Q

Q

S

† †

F/Fs

2-15

14 x

14 x

R Q

Q

S

† †

F/F16

POSITION 2-15

POSITIONS 16

12

13

11

10

Q3

Q2

Q1

Q0

R

Q

S

14

DOR

15

S0

OE

1

CL

CL

14 x L1

4 x 14

LATCHES

CL

CL

L16

4

LATCHES

E

THREE-

STATE

OUTPUT

BUFFERS

E

CD74HC40105, CD74HCT40105

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5

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

CC

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For V

I

 < -0.5V or V

I

 > V

CC

 + 0.5V

. . . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Diode Current, I

OK

For V

O

 < -0.5V or V

O

 > V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Source or Sink Current per Output Pin, I

O

For V

O

 > -0.5V or V

O

 < V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

25mA

DC V

CC

 or Ground Current, I

CC

 . . . . . . . . . . . . . . . . . . . . . . . . .±

50mA

Operating Conditions

Temperature Range (T

A

)  . . . . . . . . . . . . . . . . . . . . . -55

o

C to 125

o

C

Supply Voltage Range, V

CC

HC Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

I

, V

O

 . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3)

θ

JA

 (

o

C/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

90

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

160

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150

o

C

Maximum Storage Temperature Range  . . . . . . . . . .-65

o

C to 150

o

C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

o

C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3.

θ

JA

 is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C -55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

High Level Input

Voltage

V

IH

-

-

2

1.5

-

-

1.5

-

1.5

-

V

4.5

3.15

-

-

3.15

 -

3.15

-

V

6

4.2

-

-

4.2

-

4.2

-

V

Low Level Input

Voltage

V

IL

-

-

2

-

-

0.5

-

0.5

-

0.5

V

4.5

-

-

1.35

-

1.35

-

1.35

V

6

-

-

1.8

-

1.8

-

1.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

or V

IL

-0.02

2

1.9

-

-

1.9

-

1.9

-

V

-0.02

4.5

4.4

-

-

4.4

 -

4.4

-

V

-0.02

6

5.9

-

-

5.9

-

5.9

-

V

High Level Output

Voltage

TTL Loads

-

-

-

-

-

-

-

-

-

V

-4

4.5

3.98

-

-

3.84

-

3.7

-

V

-5.2

6

5.48

-

-

5.34

-

5.2

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

or V

IL

0.02

2

-

-

0.1

-

0.1

-

0.1

V

0.02

4.5

-

-

0.1

-

0.1

-

0.1

V

0.02

6

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

-

-

-

-

-

-

-

-

-

V

4

4.5

-

-

0.26

-

0.33

-

0.4

V

5.2

6

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

 or

GND

-

6

-

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

6

-

-

8

-

80

-

160

µ

A

CD74HC40105, CD74HCT40105

background image

6

Three-State Leakage

Current

I

OZ

V

IL

or V

IH

V

O

 =

V

CC

 or

GND

6

-

-

±

0.5

-

±

5

-

±

10

µ

A

HCT TYPES

High Level Input

Voltage

V

IH

-

-

4.5 to

5.5

2

-

-

2

-

2

-

V

Low Level Input

Voltage

V

IL

-

-

4.5 to

5.5

-

-

0.8

-

0.8

-

0.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

or V

IL

-0.02

4.5

4.4

-

-

4.4

-

4.4

-

V

High Level Output

Voltage

TTL Loads

-4

4.5

3.98

-

-

3.84

-

3.7

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

or V

IL

0.02

4.5

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

4

4.5

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

and

GND

0

5.5

-

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

5.5

-

-

8

-

80

-

160

µ

A

Three-State Leakage

Current

I

OZ

V

IL

or V

IH

V

O

 =

V

CC

 or

GND

5.5

-

-

±

0.5

-

±

5

-

±

10

µ

A

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

I

CC

(Note)

V

CC

-2.1

-

4.5 to

5.5

-

100

360

-

450

-

490

µ

A

NOTE: For dual-supply systems theoretical worst case (V

I

 = 2.4V, V

CC

 = 5.5V) specification is 1.8mA.

DC Electrical Specifications

 (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C -55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HCT Input Loading Table

INPUT

UNIT LOADS

OE

0.75

SI, SO

0.4

Dn

0.3

MR

1.5

NOTE: Unit Load is

I

CC

limit specified in DC Electrical Table, e.g.,

360

µ

A max at 25

o

C.

CD74HC40105, CD74HCT40105

background image

7

Prerequisite for Switching Specifications

PARAMETER

SYMBOL

V

CC

 (V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

HC TYPES

SI Pulse Width

HIGH or LOW

t

W

2

80

-

100

-

120

-

ns

4.5

16

-

20

-

24

-

ns

6

14

-

17

-

20

-

ns

SO Pulse Width

HIGH or LOW

t

W

2

120

-

150

-

180

-

ns

4.5

24

-

30

-

36

-

ns

6

20

-

26

-

31

-

ns

DIR Pulse Width

HIGH or LOW

t

W

2

200

-

250

-

300

-

ns

4.5

40

-

50

-

60

-

ns

6

34

-

43

-

51

-

ns

DOR Pulse Width

HIGH or LOW

t

W

2

200

-

250

-

300

-

ns

4.5

40

-

50

-

60

-

ns

6

34

-

43

-

51

-

ns

MR Pulse Width HIGH

t

W

2

120

-

150

-

180

-

ns

4.5

24

-

30

-

36

-

ns

6

20

-

26

-

31

-

ns

Removal Time

MR to SI

t

REM

2

50

-

65

-

75

-

ns

4.5

10

-

13

-

15

-

ns

6

9

-

11

-

13

-

ns

Set-Up Time

Dn to SI

t

SU

2

5

-

5

-

5

-

ns

4.5

5

-

5

-

5

-

ns

6

5

-

5

-

5

-

ns

Hold Time

Dn to SI

t

H

2

125

-

155

-

190

-

ns

4.5

25

-

31

-

38

-

ns

6

21

-

26

-

32

-

ns

Maximum Pulse Frequency

SI, SO

f

MAX

2

3

-

2

-

2

-

MHz

4.5

15

-

12

-

10

-

MHz

6

18

-

14

-

12

-

MHz

HCT TYPES

SI Pulse Width HIGH or LOW

t

W

4.5

16

-

20

-

24

-

ns

SO Pulse Width HIGH or

LOW

t

W

4.5

16

-

20

-

24

-

ns

DIR Pulse Width HIGH or

LOW

t

W

4.5

40

-

50

-

60

-

ns

DOR Pulse Width HIGH or

LOW

t

W

4.5

40

-

50

-

60

-

ns

MR Pulse Width HIGH

t

W

4.5

24

-

30

-

36

-

ns

Removal Time MR to SI

t

REM

4.5

15

-

19

-

22

-

ns

Set-Up Time Dn to SI

t

SU

4.5

0

-

0

-

0

-

ns

Hold Time Dn to SI

t

H

4.5

25

-

31

-

38

-

ns

Maximum Pulse Frequency

SI, SO

f

MAX

4.5

15

-

12

-

10

-

MHz

CD74HC40105, CD74HCT40105

background image

8

Switching Specifications

Input t

r

, t

f

 = 6ns

PARAMETER

SYMBOL

TEST

CONDITIONS

 V

CC

(V)

25

o

C

-40

o

C TO 85

o

C -55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

Propagation Delay

t

PHL,

t

PLH

C

L

= 50pF

2

-

-

175

-

220

-

265

ns

MR to DIR, DOR

C

L

= 50pF

4.5

-

-

35

-

44

-

53

ns

C

L

= 15pF

5

-

15

-

-

-

-

-

ns

C

L

= 50pF

6

-

-

30

-

37

-

45

ns

SI to DIR

t

PHL,

t

PLH

C

L

= 50pF

2

-

-

210

-

265

-

315

ns

C

L

= 50pF

4.5

-

-

42

-

53

-

63

ns

C

L

= 15pF

5

-

18

-

-

-

-

-

ns

C

L

= 50pF

6

-

-

36

-

45

-

54

ns

SO to DOR

t

PHL,

t

PLH

C

L

= 50pF

2

-

-

210

-

265

-

315

ns

C

L

= 50pF

4.5

-

-

42

-

53

-

63

ns

C

L

= 15pF

5

-

18

-

-

-

-

-

ns

C

L

= 50pF

6

-

-

36

-

45

-

54

ns

SO to Qn

t

PHL,

t

PLH

C

L

= 50pF

2

-

-

400

-

500

-

600

ns

C

L

= 50pF

4.5

-

-

80

-

100

-

120

ns

C

L

= 15pF

5

-

35

-

-

-

-

-

ns

C

L

= 50pF

6

-

-

68

-

85

-

102

ns

Propagation Delay/Ripple thru

Delay

SI to DOR

t

PLH

C

L

= 50pF

2

-

-

2000

-

2500

-

3000

ns

4.5

-

-

400

-

500

-

600

ns

6

-

-

340

-

425

-

510

ns

Propagation Delay/Ripple thru

Delay

SO to DIR

t

PLH

C

L

= 50pF

2

-

-

2500

-

3125

-

3750

ns

4.5

-

-

500

-

625

-

750

ns

6

-

-

425

-

532

-

638

ns

Propagation Delay/Ripple thru

Delay

SI to Qn

t

PLH

C

L

= 50pF

2

-

-

1500

-

1900

-

2250

ns

4.5

-

-

300

-

380

-

450

ns

6

-

-

260

-

330

-

380

ns

Three-State Output Enable

OE to Q

n

t

PZH,

t

PZL

C

L

= 50pF

2

-

-

150

-

190

-

225

ns

4.5

-

-

30

-

38

-

45

ns

6

-

-

26

-

33

-

38

ns

Three-State Output Disabe

OE to Qn

t

PHZ,

t

PLZ

C

L

= 50pF

2

-

-

140

-

175

-

210

ns

C

L

= 50pF

4.5

-

-

28

-

35

-

42

ns

C

L

= 50pF

6

-

-

24

-

30

-

36

ns

Output Transition Time

t

TLH

, t

THL

C

L

= 50pF

2

-

-

75

-

95

-

110

ns

4.5

-

-

15

-

19

-

22

ns

6

-

-

13

-

16

-

19

ns

Maximum SI, SO Frequency

f

MAX

C

L

= 15pF

5

-

32

-

-

-

-

-

MHz

Input Capacitance

C

IN

C

L

= 50pF

-

-

-

10

-

10

-

10

pF

Power Dissipation Capacitance

(Notes 4, 5)

C

PD

C

L

= 15pF

5

-

83

-

-

-

-

-

pF

CD74HC40105, CD74HCT40105

background image

9

Three-State Output

Capacitance

C

O

C

L

= 50pF

-

-

-

15

-

15

-

15

pF

HCT TYPES

Propagation Delay Time

t

PLH,

t

PHL

C

L

= 50pF

4.5

-

-

36

-

45

-

54

ns

MR to DIR, DOR

C

L

= 15pF

5

-

15

-

-

-

-

-

ns

SI to DIR

t

PLH,

t

PHL

C

L

= 50pF

4.5

-

-

42

-

53

-

63

ns

C

L

=15pF

5

-

18

-

-

-

-

-

ns

SO to DOR

t

PLH,

t

PHL

C

L

= 50pF

4.5

-

-

42

-

53

-

63

ns

C

L

=15pF

5

-

18

-

-

-

-

-

ns

SO to Qn

t

PLH,

t

PHL

C

L

= 50pF

4.5

-

-

80

-

100

-

120

ns

C

L

=15pF

5

-

35

-

-

-

-

-

ns

Propagation Delay/Ripple thru

Delay

SI to DOR

t

PLH

C

L

= 50pF

4.5

-

-

400

-

500

-

600

ns

Propagation Delay/Ripple thru

Delay

SO to DIR

t

PLH

C

L

= 50pF

4.5

-

-

500

-

625

-

750

ns

Propagation Delay/Ripple thru

Delay

SI to Qn

t

PLH

C

L

= 50pF

4.5

-

-

300

-

380

-

450

ns

Three-State Output Enable

OE to Q

n

t

PZH,

t

PZL

C

L

= 50pF

4.5

-

-

35

-

44

-

53

ns

Three-State Output Disabe

OE to Qn

t

PHZ,

t

PLZ

C

L

= 50pF

4.5

-

-

30

-

38

-

45

ns

Output Transition Time

t

TLH

, t

THL

C

L

= 50pF

4.5

-

-

15

-

19

-

22

ns

Maximum CP Frequency

f

MAX

C

L

=15pF

5

-

32

-

-

-

-

-

MHz

Input Capacitance

C

IN

C

L

= 50pF

-

-

-

10

-

10

-

10

pF

Power Dissipation Capacitance

(Notes 4, 5)

C

PD

C

L

=15pF

5

-

83

-

-

-

-

-

pF

Three-State Output

Capacitance

C

O

C

L

= 50pF

-

-

-

15

-

15

-

15

pF

NOTES:

4. C

PD

 is used to determine the dynamic power consumption, per package.

5. P

D

= C

PD

V

CC

2

f

i

+

Σ

(C

L

V

CC

2

f

o

) where f

i

= Input Frequency, f

o

= Output Frequency, C

L

= Output Load Capacitance, V

CC

= Supply

Voltage.

Switching Specifications

Input t

r

, t

f

 = 6ns  (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

 V

CC

(V)

25

o

C

-40

o

C TO 85

o

C -55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

CD74HC40105, CD74HCT40105

background image

10

Test Circuits and Waveforms

NOTE: Outputs should be switching from 10% V

CC

 to 90% V

CC

 in

accordance with device truth table. For f

MAX

, input duty cycle = 50%.

FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

NOTE: Outputs should be switching from 10% V

CC

 to 90% V

CC

 in

accordance with device truth table. For f

MAX

, input duty cycle = 50%.

FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

FIGURE 5. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

90%

50%

10%

GND

V

CC

t

r

C

L

t

f

C

L

50%

50%

t

WL

t

WH

10%

t

WL

+ t

WH

=

fC

L

I

CLOCK

2.7V

1.3V

0.3V

GND

3V

t

r

C

L

= 6ns

t

f

C

L

= 6ns

1.3V

1.3V

t

WL

t

WH

0.3V

t

WL

+ t

WH

=

fC

L

I

t

PHL

t

PLH

t

THL

t

TLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

V

CC

t

r

 = 6ns

t

f

 = 6ns

90%

t

PHL

t

PLH

t

THL

t

TLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

3V

t

r

 = 6ns

t

f

 = 6ns

90%

CD74HC40105, CD74HCT40105

background image

11

FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 9. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

FIGURE 10. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

NOTE:

Open drain waveforms t

PLZ

and t

PZL

are the same as those for three-state shown on the left. The test circuit is Output R

L

= 1k

to

V

CC

, C

L

 = 50pF.

FIGURE 11. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

Test Circuits and Waveforms

 (Continued)

t

r

C

L

t

f

C

L

GND

V

CC

GND

V

CC

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

V

CC

50%

50%

90%

10%

50%

90%

t

REM

t

PLH

t

SU(H)

t

TLH

t

THL

t

H(L)

t

PHL

IC

C

L

50pF

t

SU(L)

t

H(H)

t

r

C

L

t

f

C

L

GND

3V

GND

3V

1.3V

2.7V

0.3V

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

3V

1.3V

1.3V

1.3V

90%

10%

1.3V

90%

t

REM

t

PLH

t

SU(H)

t

TLH

t

THL

t

H(L)

t

PHL

IC

C

L

50pF

t

SU(L)

1.3V

t

H(H)

1.3V

50%

10%

90%

GND

V

CC

10%

90%

50%

50%

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

6ns

6ns

t

PZH

t

PHZ

t

PZL

t

PLZ

0.3

2.7

GND

3V

10%

90%

1.3V

1.3V

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUTS

ENABLED

t

r

6ns

t

PZH

t

PHZ

t

PZL

t

PLZ

6ns

t

f

1.3

IC WITH

THREE-

STATE

OUTPUT

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

V

CC

 FOR t

PLZ

 AND t

PZL

GND FOR t

PHZ

 AND t

PZH

OUTPUT

R

L

 = 1k

C

L

50pF

CD74HC40105, CD74HCT40105

background image

12

NOTE: Pulse must be applied for cascading by 16 N bits.

FIGURE 13. EXPANSION, 8-BITS WIDE BY 16 N-BITS LONG USING HC/HCT40105

SI DOR

Q0

Q1

Q2

Q3

SO

MR

DIR

D3

D2

D1

D0

SI DOR

Q0

Q1

Q2

Q3

SO

MR

DIR

D3

D2

D1

D0

SI DOR

Q0

Q1

Q2

Q3

SO

MR

DIR

D3

D2

D1

D0

SI DOR

Q0

Q1

Q2

Q3

SO

MR

DIR

D3

D2

D1

D0

DATA OUT

READY

8-BIT

DATA

SHIFT OUT

SHIFT IN

8-BIT

DATA

DATA IN READY

MASTER RESET

(NOTE)

background image

13

NOTES:

6. Data valid goes to high level in advance of the data out by a maximum of 38ns at V

CC

 = 4.5V for C

L

 = 50pF and T

A

 = 25

o

C.

7. At V

CC

 = 4.5V, ripple time from position 1 to position 16.

8. At V

CC

 = 4.5V, ripple time from position 16 to position 1.

FIGURE 14. TIMING DIAGRAM FOR THE CD74HC/HCT40105

SHIFT-IN PULSES

HAVE NO EFFECT

MASTER

RESET

SHIFT IN

(DATA VALID)

INPUTS

SHIFT OUT

OUTPUTS

INPUT READY

(CLEAR OUT)

OUTPUT READY

(DATA VALID)

DATA IN

(Db)

THREE-STATE

(OUTPUT

ENABLE)

DATA OUT

(UNKNOWN)

HIGH Z

INVALID

180ns

(NOTE 8)

180ns

(NOTE 7)

(NOTE 6)

INPUTS

SHIFT-OUT PULSES

HAVE NO EFFECT

1

0 1 1

1

0

1

0

1

1

1 0

0

0

1

1

1

1

1

0

0

0

(NOTE 6)

background image

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

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performed, except those mandated by government requirements.

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Copyright 

©

 1999, Texas Instruments Incorporated