background image

M ITSUBISHI  ELECTRIC

M5M5Y416CWG  -70HI, -85HI

2001.05.08      Ver.  3.0

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI  LSIs

Preliminary

Notice: This is not a final specification.

Some parametric limits are subject to change.

* Typical parameter indicates the value for the center 

   of distribution at 2.0V,  and not 100% tested.

1

DESCRIPTION

 The M5M5Y416C is a f amily   of   low v oltage 4-Mbit static RAMs

organized as 262144-words by   16-bit, f abricated by     Mitsubishi's

high-perf ormance 0.18µm CMOS technology .

  The M5M5Y416C is suitable f or memory   applications where a

simple interf acing , battery   operating and battery   backup are the

important design objectiv es.

  M5M5Y416CWG is packaged in a  CSP (chip scale package),

with the outline of   7.0mm x 8.5mm,  ball matrix of   6 x 8 (48ball)

and ball pitch of   0.75mm.  It giv es the best solution f or

a compaction

of mounting area as well as f lexibility   of   wiring pattern of   printed

circuit boards.

FEATURES

- Single  1.65~2.3V  power  supply

-  Small stand-by   current: 0.2µA (2.0V, ty p.)

-  No  clocks, No  ref resh

-  Data  retention supply   v oltage =1.3V

-  All  inputs  and  outputs are  TTL  compatible.

-  Easy memory   expansion by   S1, S2, BC1 and BC2

-  Common  Data  I/O

-  Three-state  outputs: OR-tie  capability

-  OE  prev ents  data  contention  in  the  I/O  bus

-  Process technology :   0.18µm CMOS

-  Package:  48ball  7.0mm x 8.5mm  CSP

PIN CONFIGURATION 

A0

 

~ A17

DQ1 ~ DQ16

S1

W

OE

BC1

Address input

Data input / output

Chip select input 1

Write control input

Output enable input

Lower  By te  (DQ1 ~ 8)

Pin

Function

Vcc

GND

Power supply

Ground supply

BC2

Upper  By te  (DQ9 ~ 16)

S2

Chip select input 2

(TOP VIEW)

Outline: 

48FJA

NC:  No Connection

*Don't connect E3 ball to v oltage lev el more than 0V

1

2

3

4

5

6

A

B

C

D

E

F

G

DQ3

A7

DQ1

S2

VCC

GND

DQ6

A2

S1

DQ2

DQ4

DQ5

DQ7

A1

A4

A6

A5

A17

A16

A15

A0

A3

NCor

G N D *

A14

OE

BC2

DQ15

DQ13

DQ12

DQ10

BC1

DQ16

DQ14

GND

VCC

DQ11

DQ8

W

A13

A12

N.C.

DQ9

N.C.

A11

A10

A9

A8

H

Those are summarized in the part name table below.

30mA

(10MHz)

3mA

(1MHz)

Version,

Operating

temperature

Part name

Power

Supply

Access time

max.

Stand-by   c urrent (

µA)

Ratings  (max.)

Activ e

current

(2.3V, max)

Icc1 

70°C

85°C

25°C

I-version

-40 ~ +85°C M5M5Y416CWG -85HI 1.65 ~ 2.3V

85ns

*  Ty pical 

40°C

25°C 40°C

15

8

2

1

0.4

0.2

N C

M5M5Y416CWG -70HI 1.65 ~ 2.3V

70ns

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M ITSUBISHI  ELECTRIC

M5M5Y416CWG  -70HI, -85HI

2001.05.08      Ver.  3.0

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI  LSIs

Preliminary

Notice: This is not a final specification.

Some parametric limits are subject to change.

2

FUNCTION

  The M5M5Y416CWG is organized as 262144-words by

16-bit. These dev ices operate on a single +1.65~2.3V

power supply ,   and are directly   TTL compatible to both

input and output. Its f ully static circuit needs no clocks

and no ref resh, and  makes it usef ul.

   The operation mode are determined by   a combination

of   t he dev ice control inputs BC1 , BC2 , S1, S2 , W

and OE. Each mode is summarized in the f unction

table.

  A write operation is executed whenev er the low lev el

W ov erlaps with the low lev el BC1 and/or BC2 and the

low lev el S1 and the high lev el S2. The

address(A0~A17) must be set up bef ore the write cycle

and must be stable during the entire cy c le.

  A read operation is executed by   s etting W at a high

lev el and OE at a low lev el while BC1 and/or BC2 and

S1 and S2 are in an activ e state(S1=L,S2=H).

   When setting BC1 at the high lev el and other pins are

in an activ e stage , upper-by te are in a selectable mode

in which both reading and writing are enabled, and lower-

by t e are in a non-selectable mode. And when setting

BC2 at a high lev el and other pins are in an activ e

stage, lower-by te are in a selectable mode and upper-

by t e are in a non-selectable mode.

 When setting BC1 and BC2 at a high lev el or S1 at a high

lev el or S2 at a low lev el, the chips are in a non-selectable

mode in which both reading and writing are disabled. In this

mode, the output stage is in a high-impedance state,

allowing OR-tie with other chips and memory   expansion by

BC1, BC2 and S1, S2.

  The power supply   current is reduced as low as 0.2µA(25°C,

ty pical), and the memory   data can be held at +1.3V power

supply ,   enabling battery   back-up operation during power

f ailure or power-down operation in the non-selected mode.

BLOCK DIAGRAM

FUNCTION  TABLE

Mode

S2

W

H

X

X

High-Z

BC1 BC2

OE

DQ1~8

X

X

Non selection

DQ9~16

Icc

High-Z Standby

High-Z High-Z

H

X

L

L

H

Din

High-Z

Activ e

H

H

L

H

Read 

High-Z

Dout

Activ e

L

H

H

L

Activ e

H

H

L

Activ e

H

L

High-Z

High-Z

Activ e

H

L

H

H

High-Z

H

L

Dout

H

L

L

Read 

Dout

Activ e

H

L

Din

L

L

X

Write 

Din

Activ e

H

High-Z

H

H

High-Z High-Z

Non selection

X

H

H

X

X

Standby

Write 

H

H

L

L

Write 

Din

Activ e

X

H

L

H

Read 

High-Z

Activ e

L

Dout

H

High-Z

S1

H

L

L

L

L

L

L

L

X

L

L

L

X

X

High-Z

X

X

Non selection

High-Z Standby

L

L

X

X

High-Z

X

X

Non selection

High-Z Standby

H

MEMORY ARRAY

262144   WORDS

x 16   BITS

CLOCK

GENERATOR

A

0

A

1

A

16

A

17

S2

BC1

BC2

W

OE

DQ

8

DQ

1

DQ

16

DQ

9

-

Vcc

GND

S1

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M ITSUBISHI  ELECTRIC

M5M5Y416CWG  -70HI, -85HI

2001.05.08      Ver.  3.0

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI  LSIs

Preliminary

Notice: This is not a final specification.

Some parametric limits are subject to change.

3

ABSOLUTE  MAXIMUM  RATINGS

pF

10

V

I

=GND, V

I

=25mVrms, f =1MHz

V

O

=

GND,V

O

=25mVrms, f =1MHz

C

I

C

O

Symbol

Parameter

Limits

Conditions

Units

µA

mA

mA

V

Icc

1

Icc

2

Icc

4

V

IH

V

IL

I

O

Icc

3

V

OH

I

OH

= -0.1mA

V

OL

I

OL

=0.1mA

I

I

V

=0 

Vcc

BC1 and BC2=VIH or S1=VIH or S2=VIL  or OE=VIH, VI/O=0 ~ Vcc

Vcc+0.2

0.4

0.7 x Vcc

-0.2 *

1.3

0.5

0.2

±1

30

18

±1

3

Max

Ty p

Min

DC  ELECTRICAL CHARACTERISTICS 

f = 10MHz

f = 1MHz

-

-

-

-

-

Supply   v oltage

Input v oltage

Output v oltage

Power dissipation

Operating

temperature

Storage temperature

V

mW

Conditions

Ta=25°C

700

- 65 ~ +150

Ratings

Vcc

V

I

V

O

P

d

T

a

T

stg

-0.5

~ +2.7

-0.2

~  Vcc + 0.2  (max. 2.7V)

0 ~ Vcc 

Symbol

Parameter

Units

- 40 ~ +85

I-v ersion

With respect to GND

f = 10MHz

f = 1MHz

1.5

30

18

3

1.5

-

With respect to GND

With respect to GND

 ( Vcc=1.65~ 2.3V, unless otherwise noted)

High-lev el input v oltage

Low-lev el input v oltage

High-level output voltage

Low-lev el output v oltage

Input leakage current

Output leakage current

Activ e supply   c urrent

         ( AC,MOS lev el )

         ( AC,TTL lev el )

Activ e supply   c urrent

Stand by   s upply   current

         ( AC,MOS lev el )

         ( AC,TTL lev el )

Stand by   s upply   current

Other inputs= 0 ~ Vcc

Note 1: Direction for current flowing into IC is indicated as positive (no mark)

Note 2: Typical parameter indicates the value for the center of distribution at  2.0V,  and not 100% tested.  

 CAPACITANCE

 (Vcc=1.65 ~ 2.3V, unless otherwise noted)

Symbol

Parameter

Conditions

Limits

Max

Ty p

Min

Units

Input capacitance

Output capacitance

* -0.7V in case of   AC (Pulse width    30ns)

BC1 and BC2   0.2V, S1   0.2V, S2   Vcc-0.2V

other  inputs    0.2V  or      Vcc-0.2V

Output - open (duty  100%)

<

=

<

=

>

=

BC1 and BC2=V

IL

 , S1=V

IL

 ,S2=V

IH

<

=

other pins =V

IH  or

  V

IL

 

Output - open (duty  100%)

BC1 and BC2=V

IH

 or S1=V

IH

 or S2=V

IL

* -0.7V in case of   AC (Pulse width    30ns)

<

=

<

=

10

 

°C

°C

µA

0.2

-

~ +85°C

~ +25°C

-

1

~ +40°C

-

0.4

2

-

15

(1)

S1    Vcc - 0.2V,

>

=

other inputs = 0 ~ Vcc

S2    0.2V,

(2)

other inputs = 0 ~ Vcc

BC1 and BC2   Vcc - 0.2V 

S1   0.2V, S2   Vcc - 0.2V

<

=

>

=

(3)

>

=

other inputs = 0 ~ Vcc

S2    Vcc - 0.2V,

>

=

<

=

~ +70°C

-

8

-

background image

M ITSUBISHI  ELECTRIC

M5M5Y416CWG  -70HI, -85HI

2001.05.08      Ver.  3.0

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI  LSIs

Preliminary

Notice: This is not a final specification.

Some parametric limits are subject to change.

AC ELECTRICAL CHARACTERISTICS

 (Vcc=1.65 ~ 2.3V, unless otherwise noted)

Input rise time and f all time

Ref erence lev el

Output loads

1.65~2.3V

V

IH

=0.7 x Vcc+0.2V,  V

IL

=0.2V

Transition is measured ±200mV from 

steady state voltage.(for ten,tdis)

5ns

Fig.1,CL=30pF

         CL=5pF (for ten,tdis)

(1)  TEST CONDITIONS

Supply   v oltage

Input pulse

1TTL

CL

DQ

Fig.1  Output load

Including scope and

jig capacitance

t

CR 

ns

t

a

(S1) 

t

a

(OE)

 

t

dis

(S1)

 

t

dis

(OE)

 

t

en

(S1) 

t

en

(OE)

  

t

V

(A) 

 

t

a

(A)

 

10

35

ns

ns

ns

ns

ns

ns

ns

ns

t

a

(BC1) 

t

a

(BC2) 

t

dis

(BC1) 

t

dis

(BC2) 

t

en

(BC1) 

t

en

(BC2) 

ns

ns

ns

ns

ns

ns

70

25

25

25

25

10

10

5

10

t

a

(S2) 

ns

t

en

(S2) 

10

ns

t

dis

(S2)

 

ns

25

70

70HI

4

t

su

(A-WH) 

 

t

CW

  

t

w

(W)  

t

su

(A)  

t

su

(S1)  

t

su

(D) 

 

t

h

(D) 

 

t

rec

(W) 

 

t

dis

(W)  

t

dis

(OE) 

 

t

en

(W)  

t

en

(OE)

  

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

t

su

(BC1) 

 

t

su

(BC2) 

 

t

su

(S2)  

ns

25

25

70

55

0

65

5

5

65

65

65

30

0

0

65

Symbol

Parameter

Read cy cle time

Limits

Address access time

Chip select 1 access time

Chip select 2 access time

By te control 1 access time

By te control 2 access time

Output enable access time

Output disable time af t er S2 low

Output disable time af t er S1 high

Output disable time af t er BC1 high

Max

Min

Units

(2)  READ CYCLE

Output disable time af t er BC2 high

Output disable time af t er OE high

Output enable time af ter S1 low

Output enable time af ter S2 high

Output enable time af ter BC1 low

Output enable time af ter BC2 low

Output enable time af ter OE low

Data v alid time after address

(3) WRITE CYCLE

Max

Min

Limits

Units

Write cy cle time

Write pulse width

Address setup time

Address setup time with respect to W

By te control 1 setup time

By te control 2 setup time

Chip select 1 setup time

Chip select 2 setup time

Data setup time

Data hold time

Write recov ery   time

Output disable time f rom W low

Output disable time f rom OE high

Output enable time f rom W high

Output enable time f rom OE low

Symbol

Parameter

V

OH

=V

OL

=0.9V

70HI

70

70

70

70

10

45

85

30

30

30

30

10

10

5

10

10

30

85

85HI

Max

Min

85

85

85

85

30

30

85

60

0

70

5

5

70

70

70

35

0

0

70

Max

Min

85HI

background image

M ITSUBISHI  ELECTRIC

M5M5Y416CWG  -70HI, -85HI

2001.05.08      Ver.  3.0

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI  LSIs

Preliminary

Notice: This is not a final specification.

Some parametric limits are subject to change.

S2

(Note3)

(Note3)

 t

su

 

(S2)

t

en

 

(W)

5

t

a

(A)

t

a

(BC1)

t

(A)

t

dis

 (BC1) or 

t

dis

 (BC1)  

t

(OE)

t

en

 

(OE)

t

dis

 

(OE)

t

CR

t

(D)

t

su 

(D)

DQ

1~16

 t

su

 

(BC1)  or  

t

su

(BC2)

t

en

(OE)

t

dis

(OE)

t

w

 (W)

t

rec

 (W)

t

su 

(A)

t

dis 

(W)

t

CW

t

en

 

(S1)

W = "H" lev el

A

0~17

DQ

1~16

A

0~17

OE

OE

W

 (4)TIMING DIAGRAMS

Read cycle

(Note3)

(Note3)

(Note3)

(Note3)

VALID DATA

Write cycle ( W control mode )

DATA IN

STABLE

(Note3)

(Note3)

t

a

(S1)

t

dis

 (S1) 

S1

(Note3)

(Note3)

BC1 ,BC2

t

a

(BC2)

or

t

en

 

(BC2)

t

en

 

(BC1)

t

su 

(A-WH)

S1

(Note3)

(Note3)

 t

su

 

(S1)

BC1,BC2

t

a

(S2)

t

dis

 (S2) 

S2

(Note3)

(Note3)

t

en

 

(S2)

background image

M ITSUBISHI  ELECTRIC

M5M5Y416CWG  -70HI, -85HI

2001.05.08      Ver.  3.0

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI  LSIs

Preliminary

Notice: This is not a final specification.

Some parametric limits are subject to change.

6

Note 3: Hatching indicates the state is "don't care".

Note 4: A Write occurs during S1 low, S2 high ov erlaps BC1 and/or BC2 low and W low. 

Note 6: Don't apply   inv erted phase signal externally   when DQ pin is in output mode.

Note 5: When the f alling edge of   W   is simultaneously   or prior to the f alling edge of   BC1 and/or BC2 or the f alling 

t

(D)

t

su 

(D)

DQ

1~16

 t

su

 

(BC1) or

t

su

 

(BC2)

t

rec

 (W)

t

su 

(A)

t

CW

A

0~17

W

Write cycle (BC control mode)     

DATA IN

STABLE

(Note3)

(Note3)

(Note4)

(Note5)

(Note3)

(Note3)

S1

edge of   S1 or rising edge of   S2, the outputs are maintained in the high impedance state.

BC1 ,BC2

(Note3)

(Note3)

S2

background image

M ITSUBISHI  ELECTRIC

M5M5Y416CWG  -70HI, -85HI

2001.05.08      Ver.  3.0

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI  LSIs

Preliminary

Notice: This is not a final specification.

Some parametric limits are subject to change.

t

(D)

t

su 

(D)

DQ

1~16

 t

su

 

(S1)

t

rec

 (W)

t

su 

(A)

t

CW

A

0~17

W

S1

Write cycle (S1 control mode)

DATA IN

STABLE

(Note3)

(Note3)

(Note4)

(Note5)

(Note3)

(Note3)

BC1,BC2

(Note3)

(Note3)

S2

t

(D)

t

su 

(D)

DQ

1~16

 t

su

 

(S2)

t

rec

 (W)

t

su 

(A)

t

CW

A

0~17

W

S1

Write cycle (S2 control mode)

DATA IN

STABLE

(Note3)

(Note3)

(Note4)

(Note5)

(Note3)

(Note3)

BC1,BC2

(Note3)

(Note3)

S2

7

background image

M ITSUBISHI  ELECTRIC

M5M5Y416CWG  -70HI, -85HI

2001.05.08      Ver.  3.0

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI  LSIs

Preliminary

Notice: This is not a final specification.

Some parametric limits are subject to change.

8

t

su (PD)

t

rec (PD)

ns

ms

0.7 x Vcc

t

su (PD)

1.65V

1.65V

t

rec (PD)

BC1 , BC2   Vcc-0.2V 

Vcc

V

1.3

Vcc

 (PD)

V

I (S1)

Icc 

(PD)

0.7xVcc

BC1

POWER DOWN CHARACTERISTICS

 (1) ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Test conditions

Limits

Min 

Ty p

Max

Units

Power down supply voltage

Chip select input S1

Power down

supply   c urrent

(2) TIMING REQUIREMENTS

Symbol

Parameter

Test conditions

Limits

Min 

Ty p

Max

Units

Power down set up time

Power down recov ery   t ime

(3) TIMING DIAGRAM

BC  control  mode

V

I (BC)

Byte control input BC1 & BC2

V

>

=

BC2

t

su (PD)

1.65V

1.65V

t

rec (PD)

Vcc

S1

S1  control  mode

S1   Vcc-0.2V 

>

=

0

5

V

I (S2)

Chip select input S2

0.2

0.2V

t

su (PD)

1.65V

1.65V

t

rec (PD)

Vcc

S2

S2  control  mode

S2    0.2V

µA

~ +40°C

0.1

-

-

~ +85°C

~ +25°C

-

0.2

0.7

1.5

-

10

(1)

S1    Vcc - 0.2V,

>

=

other inputs = 0 ~ Vcc

S2    0.2V,

(2)

other inputs = 0 ~ Vcc

BC1 and BC2   Vcc - 0.2V 

S1   0.2V, S2   Vcc - 0.2V

<

=

>

=

(3)

>

=

other inputs = 0 ~ Vcc

Vcc=1.3V

0.7 x Vcc

0.7 x Vcc

0.7 x Vcc

1.65V Vcc(PD)

1.3V

Vcc(PD) 1.65V

Vcc(PD)

0.7xVcc

1.65V Vcc(PD)

1.3V

Vcc(PD) 1.65V

Vcc(PD)

V

0.2V

Note 2: Typical parameter of Icc(PD) indicates the value for the

             center of distribution at 1.3V,  and not 100% tested.  

<

=

~ +70°C

-

5

-

V

background image

M ITSUBISHI  ELECTRIC

M5M5Y416CWG  -70HI, -85HI

2001.05.08      Ver.  3.0

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI  LSIs

Preliminary

Notice: This is not a final specification.

Some parametric limits are subject to change.

9

Keep safety first in your circuit designs!

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circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-

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further details on these materials or the products contained therein.

background image

M ITSUBISHI  ELECTRIC

M5M5Y416CWG  -70HI, -85HI

2001.05.08      Ver.  3.0

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI  LSIs

Preliminary

Notice: This is not a final specification.

Some parametric limits are subject to change.

Revision History

Ver. 0.1 / Oct.24.2000                   Initial   (-85HI)

Ver. 0.2 / Oct.26.2000                  min.1.8V --->    85ns

                                                         min.1.7V ---> 100ns   (-85HI)

Ver. 0.3 / Oct.26.2000                  min.1.65V --->    85ns

Ver. 1.0 / Nov.22.2000                 tsu(D)35ns --->   45ns

Ver. 2.0 / Apr.09.2001               Part#: M5M5W416C --->M5M5Y416C

                                                      Address#(Timing Diagram) : A18---> A17(Correct)

                                                      E3 ball: GND ---> NC or GND

                                                      Add comment for safety

Ver. 3.0 / May.08.2001               tdis(BC1) &tdis(BC2) ---> ten(BC1) & ten(BC2) <Correct> P4

                                                      Addition of -70HI spec and  notice as "Preliminary"

                                                      Power down supply voltage : 1.5V to 1.3V 

10