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January 1999 TOKO, Inc.

Page 1

TK75005

OSCILLATOR

FB

CT

ICHG

175 µA

fCLK

SLOPE

COMPENSATION

2.6 V

PWM LATCH

DRV

CURRENT

CONTROL

DETECTOR

OVERVOLTAGE

DETECTOR

GND

BANDGAP

REFERENCE

UVLO

10.0 V

8.0 V

VCC

ICT

1.02 V

S

Q

IDS

1.975 mA

OVP

EAIN

EAOUT

R

2.5 V

GM STAGE

OVP

DRV

EAIN

VCC

GND

EAOUT

FB

CT

OVP

DRV

EAIN

VCC

GND

EAOUT

FB

CT

APPLICATIONS

s

Power Factor Correction Converters

s

Off-Line Power Supplies

s

Industrial Power Supplies

s

Off-Line Battery Charger

FEATURES

s

Can Be Used For Power Factor Correction/Line

Harmonics Reduction to Meet IEC1000-3-2

Requirements

s

Maximum Duty Ratio 89% (typ.)

s

Low Standby Current for Current-Fed Start-Up

s

Current-Mode or Voltage-Mode Control

s

Internal User-Adjustable Slope Compensation

s

Pulse-by-Pulse Current Limiting

TK75005

BLOCK DIAGRAM

DESCRIPTION

The TK75005 is an 8-pin PWM controller suitable for both

voltage-mode and current-mode control. It also has

advanced features not available in controllers with a higher

pin count. One such feature is a sawtooth current flowing

out of the feedback pin (FB), which provides a slope

compensation ramp (in current mode applications) in

proportion to the resistance terminating that FB pin.

The TK75005 offers the same features as the TK75003

with the addition of the Error Amplifier and the Overvoltage

Protection (OVP) functions, and the deletion of the

Overcurrent Frequency Reduction feature.

This PWM has features similar to the UC3842 (please

refer to UC3842 Comparison Section).

ADVANCED

INFORMATION

75005

75005

SOP-8

DIP-8

ORDERING INFORMATION

TAPE/REEL CODE

TL: Tape Left

MG: Magazine

Tape/Reel Code

TK75005

PACKAGE CODE

D: DIP-8

M: SOP-8

TEMPERATURE RANGE

C: -40 TO 80  C

Temp. Range

Package Code

LOW-COST FLEXIBLE PWM CONTROLLER

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Page 2

January 1999 TOKO, Inc.

TK75005

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µ

TK75005 ELECTRICAL CHARACTERISTICS

Test Conditions:  V

CC

 = 13 V, C

CC

 = 4.7 

µ

F, C

T

 = 680 pF, C

DRV

 = 1000 pF, T

= T

j

 = Full Operating Temperature Range,

unless otherwise specified.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (Low Impedance) ............................ 18 V

Supply Voltage (I

CC

 < 30 mA) ...................... Self Limiting

Power Dissipation (Note 1) ................................ 800 mW

Output Energy ........................................................... 5 

µ

J

C

T

 and FB Pins ........................................................ 10 V

Junction Temperature ........................................... 150 

°

C

Storage Temperature Range ................... -55 to +150 

°

C

Operating Temperature Range ................... -20 to +80 

°

C

Extended Temperature Range ................... -40 to +85 

°

C

Lead Soldering Temperature (10 s) ...................... 235 

°

C

background image

January 1999 TOKO, Inc.

Page 3

TK75005

Note 1:  Power dissipation for both packages (TK75005M and TK75005D) is 800 mW when mounted. Derate at 6.4 mW/

°

C for operation above

25 

°

C.

Note 2:  For temperature dependence refer to "Slope Compensation Peak Current vs. Temperature" graph.

Note 3:  Guaranteed by design; not 100% tested.

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1

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TK75005 ELECTRICAL CHARACTERISTICS (CONT.)

Test Conditions:  V

CC

 = 13 V, C

CC

 = 4.7 

µ

F, C

T

 = 680 pF, C

DRV

 = 1000 pF, T

= T

j

 = Full Operating Temperature Range,

unless otherwise specified.

background image

Page 4

January 1999 TOKO, Inc.

TK75005

TEST CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

OVP

DRV

EAIN

VCC

GND

EAOUT

FB

CT

3 k

3 k

100 k

INV AMP IN

CT

680pF

1 nF

CCC

4.7 µF

I CC

 (mA)

12

20

SUPPLY CURRENT vs.

SUPPLY VOLTAGE

VCC (V)

0.4

0          4          8        12        16        20

16

0.8

0.0

DEVICE ON

STANDBY

FREQUENCY (kHz)

FREQUENCY AT DRV PIN 

VS. 

TIMING

CAPACITANCE (-25 TO 85 

°

C)

CT (pF)

100

10000

10

10               100            1000         10000

1000

I SC(PK)

 (µA)

-180

-100

SLOPE COMPENSATION PEAK

CURRENT vs. TEMPERATURE

TEMPERATURE (

°

C)

-220

-50              0              50            100

-140

-260

I CC

 (mA)

20

40

SUPPLY CURRENT vs.

FREQUENCY AT DRV

FREQUENCY (kHz)

10

0           400         800       1200        1600

30

0

50

CDRV = 1 nF

CDRV = 470 pF

CDRV = 0 pF

V

FB

 (mV)

300

600

TIME (µs)

150

0              5           10           15           20

450

0

SLOPE COMPENSATION RAMP

ISC(PK)

ISC(VL)

RFB = 3 k TO GND

CT = 680 pF, EAOUT(HIGH)

ISC(PK) - ISC(VL)

V

ref

 (V)

2.52

2.6

REFERENCE VOLTAGE vs.

TEMPERATURE

TEMPERATURE (

°

C)

2.48

-50              0              50            100

2.56

2.40

2.44

background image

January 1999 TOKO, Inc.

Page 5

TK75005

PIN DESCRIPTIONS

DRIVE PIN (DRV)

This pin drives the external MOSFET with a totem pole

output stage capable of sinking or sourcing a peak current

of about 1 A. In standby mode, the DRV pin can sink about

5 mA while keeping the drive pin pulled down to about 1 V.

This ensures that the external MOSFET can not be

inadvertently turned on by leakage currents. The maximum

duty cycle of the output signal is typically 89%.

GROUND PIN (GND)

This pin provides ground return for the IC.

OVERVOLTAGE PROTECTION INPUT PIN (OVP)

This pin provides a means of turning off the external

transistor drive output independent of the PWM loop. This

pin is normally used for overvoltage protection, but can

also be used to provide a drive disabled function. The pin

is the input to comparator with its other input referenced to

2.6 V, which tracks V

ref

 of error amp over temperature. and

its output controlling the output driver of the IC. Therefore,

if a voltage appears at this pin over 2.6 V,  the voltage at

the DRV pin drops to zero.

TIMING CAPACITOR PIN (C

T

)

The external timing capacitor is connected to the C

pin.

That capacitor is the only component needed for setting

the clock frequency. The frequency measured at the C

T

 pin

is the same frequency as measured at the DRV pin. As the

frequency of operation increases above 200 kHz, the

maximum duty cycle decreases from a typical 89% at

200 kHz to 82% at 1.6 MHz. The maximum recommended

clock frequency of the device is 1.6 MHz. At normal

operation, during the rising section of the timing-capacitor

voltage, a trimmed internal current of 175 

µ

A flows out from

the C

T

 pin and charges the capacitor. During the falling

section of the timing-capacitor voltage, an internal current

of about 1.8 mA discharges the capacitor.

FEEDBACK INPUT PIN (FB)

The feedback pin normally receives the sum of three

signals: the switch current signal,  the error signal (from the

internal error amplifier and the GM stage), and a voltage

ramp (from an internal sawtooth-shaped current with a

peak value of about 205 

µ

A) generated across the external

terminating resistance. The switch current signal is needed

in current-mode controlled converters and in converters

with cycle-by-cycle overload protection. The error signal is

needed for stabilizing the output voltage or current. The

voltage ramp is needed for slope compensation (necessary

for avoiding subharmonic instability in constant-frequency

peak-current controlled current-mode converters above

50% duty ratio), or for Pulse Width Modulation (PWM) (in

voltage-mode controlled converters).

At higher clock frequencies, the bandwidth limitation of the

internally-generated sawtooth-shaped current source

becomes more apparent. The degree to which ramp

bandwidth is tolerable depends on performance

requirements at narrow pulse widths. A low impedance at

the feedback pin can effectively eliminate the internally-

generated ramp effects and an external ramp can be

readily created to attain higher performance at high

frequencies, if desired.

ERROR AMPLIFIER COMPENSATION INPUT PIN  (EA

IN

)

This pin is the inverting input of an operational amplifier

which has its non-inverting input connected to 2.5 V. This

is called the error amp because it amplifies the error

between this pin’s voltage and 2.5 V reference, which

should reflect the error in the power supply’s output

regulation. The error amp provides a high gain stage so

that the voltage loop gain can be high enough to provide

good output voltage regulation.

ERROR AMPLIFIER COMPENSATION OUTPUT PIN (EA

OUT

)

This pin is the output of the operational amplifier mentioned

in the EA

IN

 pin description. By picking the proper resistor

and capacitor network connected between pins 6 and 7,

the gain and frequency response of the error amp block of

the voltage loop can be set, thus providing gain and

frequency compensation into the PWM voltage loop as

needed. This pin also acts as the input to the GM stage of

the voltage control loop.

SUPPLY VOLTAGE PIN (V

CC

)

This pin is connected to the supply voltage. The IC is in a

low-current (250  

µ

A typ.) standby mode before the supply

voltage exceeds 10 V (typ.), which is the upper threshold

of the undervoltage lockout circuit. The IC switches back

to standby mode when the supply voltage drops below 8 V

(typ.).

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Page 6

January 1999 TOKO, Inc.

TK75005

THEORY OF OPERATION

The TK75005 is intended for use as a highly flexible

primary-side PWM controller. The TK75005 is much like

the TK75003 with the addition of an error amplifier, a GM

stage and an overvoltage comparator, and the deletion of

the TK75003 overcurrent frequency reduction feature.

The many features integrated into a simple 8-pin design

allow it to be easily configured for voltage-mode or current-

mode control, fixed frequency or fixed off-time operation,

off-line boot-strapping, and direct drive of a power MOSFET.

Using a control technique referenced in the “Application

Information” section, the TK75005 can be used as a highly

cost-effective controller for power factor correction.

The most noteworthy integrated feature in the TK75005 is

the way in which the feedback control pin is configured to

receive the error signal and the current signal for current-

mode control. Rather than receiving both inputs into a

comparator, a single input receives both signals summed

together and compares them against a fixed internal

reference. This yields two desirable effects: 1) a current-

limit threshold is automatically established, and 2) the

required error-signal polarity is the inverse of that of a

standard two-input current-mode control system. Generally,

the signal summation requires no additional external

components and adds the flexibility to add more control

signals if desired.

Another function is integrated into the FB pin. A current

ramp, which can be used to establish either the slope-

compensation ramp for a current-mode control design or

the voltage-comparison ramp for a voltage-mode control

design, flows out of the FB pin. By adjusting the terminating

resistance at the FB pin, the desired ramp magnitude is

established.

The switching frequency is determined by an internal

current source charging an external timing capacitor. The

timing capacitor is ramped between internally-fixed

thresholds, valley to peak, and then quickly discharged. A

fixed off-time control technique can readily be implemented

by using a small transistor to keep the timing capacitor

discharged during the on-time. When the on-pulse is

terminated, the timing capacitor ramps up to a fixed

threshold at a fixed rate to set the off-time.

The Undervoltage Lockout (UVLO) feature with hysteresis

minimizes the start-up current which allows a low-power

boot-strap technique to be used for the housekeeping

power. The duty ratio of the TK75005 is limited to

approximately 89% by the time required to discharge the

timing ramp.

UC3842  COMPARISON

Similarities to the UC3842

1) a single-ended transistor driver output with similar

drive performance

2) an inverting error amplifier referenced to 2.5 V with

similar electrical characteristics

3) a maximum threshold of ~1V on the current sense

voltage used to terminate the PWM pulse

4) an 8-pin SOP-8 or DIP-8 package

Unique features of the TK75005

1) a multi-signal summation point at the FB pin, instead

of a single function UC1842 C/S pin

2) built-in slope compensation sawtooth current coming

out of the FB pin, reduced parts

3) an overvoltage protection pin compared to 2.6 V

4) switching frequency set using a single capacitor,

reduced parts

5) different UVLO thresholds 10 V / 8 V

6) maximum duty cycle set at 89%

background image

January 1999 TOKO, Inc.

Page 7

TK75005

APPLICATIONS INFORMATION

BOOST POWER FACTOR CORRECTOR APPLICATION

CIRCUIT

Figure 7 shows a universal-input, 100 W boost power

factor corrector application circuit. The control technique is

called “current-clamped control.” Both the control technique

and the application circuit with waveforms are described in

the paper “Low-Cost Power Factor Correction/Line-

Harmonics Reduction with Current-Clamped Boost

Converter,” published in the conference proceedings of

Power Conversion Electronics ’95/Powersystems World™

’95. A copy of the paper can be obtained by contacting

Toko.

For designers who wish to explore other performance

optimizations of the current-clamped boost power factor

corrector, aside from the conference paper Toko offers a

Mathcad© file which can accurately display current

waveforms and predict power factor, harmonic distortion,

and individual harmonic currents. The Mathcad file and the

text which describes how to use it are available from the

Colorado Springs Toko IC Design Center.

The power factor corrector in Figure 7 has been optimized

for general wide-range-input use. In order to obtain the

same performance at power levels other than 100 W, the

control components do not need to change. The power

component values change as follows: C

8

 scales in

proportion to the power level, and L

1

 and R

8

 scales in

inverse proportion to the power level. Typically, although

not directly related to the line-current shaping capability of

the application circuit, C

and C

10

 would scale in proportion

to the power level. All the components in the power stage

should have a current rating as needed to accommodate

the power level.

Below is a step-by-step design example, showing how to

determine the resistance of  R

7

 terminating the feedback

pin and the resistance of the current-sense resistor R

8

, for

the boost corrector of Figure 7.

Assumptions:

Output power:

P

OUT

 = 100 W

Output voltage:

V

OUT

 = 380 Vdc

Minimum line voltage:

V

I(MIN)

 = 85 Vrms

Efficiency at 85 Vrms:

EFF = 0.93

Switching frequency:

f = 100 kHz

Inductance of boost inductor:

L

1

 = 2.5 mH

Maximum duty ratio of TK75005:

D

MAX

 = 0.88

Peak value of ramp current

flowing out of the FB pin:

I

SC(PK)

 = 200 

µ

A

Threshold voltage of the

current-control detector:

V

CCD

 = 0.98 V

Calculations:

Peak value of minimum line voltage:

V

I(MIN)(PK)

 = 

2

 x V

I(MIN)

 = 120 V

PK

Switch duty ratio at peak of minimum line voltage:

D = 1 - V

I(MIN)(PK) 

/ V

OUT

 = 0.684

Peak-to-peak ripple current in inductor L

1

:

I = V

I(MIN)(PK) 

x D / (f x L

1

) = 0.33 A

Input power at minimum line voltage:

P

I

 = P

OUT 

/ EFF = 107.5 W

Peak current in L

1

 (at peak of minimum line voltage):

I

L1(PK)

 =

2

 x P

I

 / V

I(MIN)(PK)

 + I/2 = 1.95 A

Resistance of resistor R

7

 (Note 1):

R

7

 = D

MAX 

x V

CCD 

/ I

SC(PK)

 = 4.312 kohms

background image

Page 8

January 1999 TOKO, Inc.

TK75005

Select for R

7

:

R

7

 = 4.3 kohms

Resistance of current-sense resistor R

8

 (Note 2):

R

8

 = (V

CCD

 - I

SC(PK)

 x R

7

 x D) / I

L1(PK)

 = 0.201 ohms

Select for R

8

:

R

8

 = 0.18 ohms

Note 1:  This value of R

7

 ensures that the line current will be zero around

the zero-crossing of the line voltage, which is the required condition for

low-distortion line current.

Note 2:

  

This value of R

8

 ensures that the sum of the voltage drop across

R

(caused by the peak inductor current) and the voltage drop across R

7

(caused by the instantaneous value of the stabilizing current) is equal to

the threshold voltage of the current-control detector at the peak of the

line voltage.

C1

0.1  F

85-265

VAC

F1

250 V/ 2 A

B1

600 V, 1.5 A

R1a

24 k

0.5 W

R1b

24 k

0.5 W

R2

5.6 k

C10

1 nF

400 V

C2

470  F

R3

5.6 k

R4

150 k

D4

30 V

D2

IN4148

C3

100 nF

C4

100 nF

VCC

FB

GND

CT

DRV

EAOUT

EAIN

OVP

R7

4.3 k

C6

10 nF

R8

0.18

0.5 W

R12

2.43 k

C8

100  F

400 V

R11a

200 k

0.25 W

R11b

200 k

0.25 W

D3

HFA04TB60

C5

680 pF

R5

10

Q1

IRF840

R6

51

R9

100 k

C7

1  F

D1

1N4148

TH1

10 

U1

TK75005

t:9

2.5 mH

t: 220

ETD-29 core

gap in center leg

L1

R10

3 k

380 V DC

100 W

R51a

200 k

0.25 W

R51b

200 k

0.25 W

R52

2.43 k

1

2

3

4

APPLICATIONS INFORMATION (CONT.)

FIGURE 7: BOOST POWER FACTOR CORRECTOR APPLICATION CIRCUIT

background image

January 1999 TOKO, Inc.

Page 9

TK75005

Marking Information

                             Marking

TK75005

xxx

DIP-8

PACKAGE OUTLINE

Printed in the USA

© 1999 Toko, Inc.

All Rights Reserved

TOKO AMERICA REGIONAL OFFICES

Toko America, Inc. Headquarters

1250 Feehanville Drive,  Mount Prospect, Illinois  60056

Tel: (847) 297-0070    Fax: (847) 699-7864

IC-xxx-TK75005

0798O0.0K

Visit our Internet site at http://www.tokoam.com

The information furnished by TOKO, Inc. is believed to be accurate and reliable. However, TOKO reserves the right to make changes or improvements in the design, specification or manufacture of its

products without further notice. TOKO does not assume any liability arising from the application or use of any product or circuit described herein, nor for any infringements of patents or other rights of

third parties which may result from the use of its products. No license is granted by implication or otherwise under any patent or patent rights of TOKO, Inc.

6.4

2.54

0.46

e

3.3

3.8

3.3

0.25

7.62

e1

0 ~15

0.5 min

9.5

5

8

1

4

Dimensions are shown in millimeters

Tolerance: x.x =   0.2 mm (unless otherwise specified)

M

0.25

0.3

+

0.3

+

Marking

Lot Number

Country of Origin

+ 0.15

- 0.05

+ 0.15

- 0.05

0.1

3.9

0.42

1.27

1.45

e

4.89

6.07

0.2

0 ~ 0.25

1.27

0.76

5.4

1.27

e

e

1

0.5

0 ~ 10

1.64

Recommended Mount Pad

8

5

4

1

0.3

+

0.3

+

Dimensions are shown in millimeters

Tolerance: x.x =   0.2 mm (unless otherwise specified)

0.12

l

SOP-8

Western Regional Office

Toko America, Inc.

2480 North First Street , Suite 260

San Jose, CA 95131

Tel: (408) 432-8281

Fax: (408) 943-9790

Midwest Regional Office

Toko America, Inc.

1250 Feehanville Drive

Mount Prospect, IL 60056

Tel: (847) 297-0070

Fax: (847) 699-7864

Eastern Regional Office

Toko America, Inc.

107 Mill Plain Road

Danbury, CT 06811

Tel: (203) 748-6871

Fax: (203) 797-1223

Semiconductor Technical Support

Toko Design Center

4755 Forge Road

Colorado Springs, CO 80907

Tel: (719) 528-2200

Fax: (719) 528-2375