background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

1 A Low-Dropout Voltage Regulator

D

Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V,

3.0-V, 3.3-V, 5.0-V Fixed Output and

Adjustable Versions

D

Dropout Voltage Down to 230 mV at 1 A

(TPS76750)

D

Ultra Low 85 

µ

A Typical Quiescent Current

D

Fast Transient Response

D

2% Tolerance Over Specified Conditions for

Fixed-Output Versions

D

Open Drain Power-On Reset With 200-ms

Delay (See TPS768xx for PG Option)

D

8-Pin SOIC and 20-Pin TSSOP PowerPAD

(PWP) Package

D

Thermal Shutdown Protection

      

description

This device is designed to have a fast transient

response and be stable with 10-

µ

F low ESR

capacitors. This combination provides high

performance at a reasonable cost.

t – Time – 

µ

s

TPS76733

LOAD TRANSIENT RESPONSE

I    – Output Current – 

A

O

V

O

– Change in

Output 

V

oltage – mV

1

0.5

60

40

20

80 100

140

120

160 180 200

0

CL = 100 

µ

F

TA = 25

°

C

0

0

50

100

–50

–100

TA – Free-Air Temperature – 

°

C

–40

0

20

120

103

–60

40

60

80 100

– Dropout V

oltage – mV

V

DO

TPS76733

DROPOUT VOLTAGE

vs

FREE-AIR TEMPERATURE

102

101

100

10–1

10–2

–20

140

IO = 1 A

IO = 10 mA

IO = 0

CO = 10 

µ

F

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright 

©

 1999, Texas Instruments Incorporated

NC – No internal connection

1

2

3

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

GND/HSINK

GND/HSINK

GND

NC

EN

IN

IN

NC

GND/HSINK

GND/HSINK

GND/HSINK

GND/HSINK

NC

NC

RESET

FB/NC

OUT

OUT

GND/HSINK

GND/HSINK

PWP PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

GND

EN

IN

IN

RESET

FB/NC

OUT

OUT

D PACKAGE

(TOP VIEW)

PowerPAD is a trademark of Texas Instruments Incorporated.

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

description (continued)

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 230 mV

at an output current of 1 A for the TPS76750) and is directly proportional to the output current. Additionally, since

the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output

loading (typically 85 

µ

A over the full range of output current, 0 mA to 1 A). These two key specifications yield

a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep

mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to

µ

A at T

J

 = 25

°

C.

The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event

of an undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the

regulator to detect an undervoltage condition on the regulated output voltage.

The TPS767xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V and 5.0-V fixed-voltage versions and

in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified

as a maximum of 2% over line, load, and temperature ranges. The TPS767xx family is available in 8 pin SOIC

and 20 pin PWP packages.

AVAILABLE OPTIONS

TJ

OUTPUT

VOLTAGE

(V)

PACKAGED DEVICES

J

TYP

TSSOP

(PWP)

SOIC

(D)

5.0

TPS76750Q

TPS76750Q

3.3

TPS76733Q

TPS76733Q

3.0

TPS76730Q

TPS76730Q

2.8

TPS76728Q

TPS76728Q

– 40

°

C to 125

°

C

2.7

TPS76727Q

TPS76727Q

– 40 C to 125 C

2.5

TPS76725Q

TPS76725Q

1.8

TPS76718Q

TPS76718Q

1.5

TPS76715Q

TPS76715Q

Adjustable

1.5 V to 5.5 V

TPS76701Q

TPS76701Q

The TPS76701 is programmable using an external resistor divider (see application

information). The D and PWP packages are available taped and reeled. Add an R

suffix to the device type (e.g., TPS76701QDR).

† See application information section for capacitor selection details.

RESET

OUT

OUT

7

6

5

IN

IN

EN

GND

3

16

14

13

VI

0.1 

µ

F

RESET

VO

10 

µ

F

+

TPS767xx

CO

Figure 1. Typical Application Configuration (For Fixed Output Options)

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

functional block diagram—adjustable version

200 ms Delay

_

+

Vref = 1.1834 V

OUT

FB/NC

EN

GND

RESET

_

+

IN

External to the device

R1

R2

functional block diagram—fixed-voltage version

_

+

Vref = 1.1834 V

OUT

EN

GND

R1

R2

RESET

_

+

IN

200 ms Delay

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Terminal Functions – SOIC Package

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

EN

2

I

Enable input

FB/NC

7

I

Feedback input voltage for adjustable device (no connect for fixed options)

GND

1

Regulator ground

IN

3, 4

I

Input voltage

OUT

5, 6

O

Regulated output voltage

RESET

8

O

RESET output

Terminal Functions – PWP Package

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

EN

5

I

Enable input

FB/NC

15

I

Feedback input voltage for adjustable device (no connect for fixed options)

GND

3

Regulator ground

GND/HSINK

1, 2, 9, 10, 11,

12, 19, 20

Ground/heatsink

IN

6, 7

I

Input voltage

NC

4, 8, 17, 18

No connect

OUT

13, 14

O

Regulated output voltage

RESET

16

O

RESET output

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

timing diagram

† Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards

for semiconductor symbology.

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

VI

Vres†

Vres

t

t

t

VO

Threshold

Voltage

RESET

Output

200 ms

Delay

200 ms

Delay

Output

Undefined

Output

Undefined

VIT +‡

VIT –‡

VIT –‡

VIT +‡

Less than 5% of the

output voltage

‡ VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT–

to VIT+ is the hysteresis voltage.

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Ĕ

Input voltage range

, V

I

 

– 0.3 V to 13.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range at EN 

–0.3 V to V

I

 + 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Maximum RESET voltage 

16.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Peak output current 

Internally limited

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output voltage, V

O

 (OUT, FB) 

7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous total power dissipation 

See dissipation rating tables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating virtual junction temperature range, T

J

  – 40

°

C to 125

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

  – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

ESD rating, HBM 

2 kV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡ All voltage values are with respect to network terminal ground.

DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURES

PACKAGE

AIR FLOW

(CFM)

TA < 25

°

C

POWER RATING

DERATING FACTOR

ABOVE TA = 25

°

C

TA = 70

°

C

POWER RATING

TA = 85

°

C

POWER RATING

D

0

568 mW

5.68 mW/

°

C

312 mW

227 mW

D

250

904 mW

9.04 mW/

°

C

497 mW

361 mW

DISSIPATION RATING TABLE 2 – FREE-AIR TEMPERATURES

PACKAGE

AIR FLOW

(CFM)

TA < 25

°

C

POWER RATING

DERATING FACTOR

ABOVE TA = 25

°

C

TA = 70

°

C

POWER RATING

TA = 85

°

C

POWER RATING

PWP#

0

2.9 W

23.5 mW/

°

C

1.9 W

1.5 W

PWP#

300

4.3 W

34.6 mW/

°

C

2.8 W

2.2 W

PWP||

0

3 W

23.8 mW/

°

C

1.9 W

1.5 W

PWP||

300

7.2 W

57.9 mW/

°

C

4.6 W

3.8 W

# This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5-in 

×

 5-in PCB, 1 oz. copper,

2-in 

×

 2-in coverage (4 in2).

|| This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5-in 

×

 2-in PCB, 1 oz. copper

with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer

to TI technical brief SLMA002.

recommended operating conditions

MIN

MAX

UNIT

Input voltage, VI

k

2.7

10

V

Output voltage range, VO

1.5

5.5

V

Output current, IO (Note 1)

0

1.0

 A

Operating virtual junction temperature, TJ (Note 1)

– 40

125

°

C

k

 To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).

NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the

device operate under conditions beyond those specified in this table for extended periods of time.

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,

V

= V

O(typ)

 + 1 V, I

O

 = 1 mA, EN = 0 V, C

O

 = 10 

µ

F (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TPS76701

1.5 V 

 VO 

 5.5 V, 

TJ = 25

°

C

VO

TPS76701

1.5 V 

 VO 

 5.5 V, 

TJ = –40

°

C to 125

°

C

0.98VO

1.02VO

TPS76715

TJ = 25

°

C,

2.7 V < VIN < 10 V

1.5

TPS76715

TJ = –40

°

C to 125

°

C,

2.7 V < VIN < 10 V

1.470

1.530

TPS76718

TJ = 25

°

C,

2.8 V < VIN < 10 V

1.8

TPS76718

TJ = –40

°

C to 125

°

C,

2.8 V < VIN < 10 V

1.764

1.836

TPS76725

TJ = 25

°

C,

3.5 V < VIN < 10 V

2.5

TPS76725

TJ = –40

°

C to 125

°

C,

3.5 V < VIN < 10 V

2.450

2.550

Output voltage 

(10

µ

A to 1 A load)

TPS76727

TJ = 25

°

C,

3.7 V < VIN < 10 V

2.7

V

(10 

µ

A to 1 A load)

(see Note 2)

TPS76727

TJ = –40

°

C to 125

°

C,

3.7 V < VIN < 10 V

2.646

2.754

V

(see Note 2)

TPS76728

TJ = 25

°

C,

3.8 V < VIN < 10 V

2.8

TPS76728

TJ = –40

°

C to 125

°

C,

3.8 V < VIN < 10 V

2.744

2.856

TPS76730

TJ = 25

°

C,

4.0 V < VIN < 10 V

3.0

TPS76730

TJ = –40

°

C to 125

°

C,

4.0 V < VIN < 10 V

2.940

3.060

TPS76733

TJ = 25

°

C,

4.3 V < VIN < 10 V

3.3

TPS76733

TJ = –40

°

C to 125

°

C,

4.3 V < VIN < 10 V

3.234

3.366

TPS76750

TJ = 25

°

C,

6.0 V < VIN < 10 V

5.0

TPS76750

TJ = –40

°

C to 125

°

C,

6.0 V < VIN < 10 V

4.900

5.100

Quiescent current (GND current)

10 

µ

A < IO < 1 A,

TJ = 25

°

C

85

µ

A

(

)

EN = 0V, (see Note 2)

IO = 1 A,

TJ = –40

°

C to 125

°

C

125

µ

A

Output voltage line regulation (

VO/VO

)

(see Notes 2 and 3)

VO + 1 V < VI 

 10 V,

TJ = 25

°

C

0.01

%/V

Load regulation

3

mV

Output noise voltage

BW = 300 Hz to 50 kHz, 

CO = 10 

µ

F, TJ = 25

°

C

190

µ

Vrms

Output current Limit

VO = 0 V

1.7

2

A

Thermal shutdown junction temperature

150

°

C

Standby current

EN = VI,

TJ = 25

°

C,

2.7 V < VI < 10 V

1

µ

A

Standby current

EN = VI,

TJ = –40

°

C to 125

°

C

2.7 V < VI < 10 V

10

µ

A

FB input current

TPS76701

FB = 1.5 V

2

nA

High level enable input voltage

1.7

V

Low level enable input voltage

0.9

V

Power supply ripple rejection (see Note 2)

f = 1 KHz, 

CO = 10 

µ

F, 

TJ = 25

°

C

60

dB

Minimum input voltage for valid RESET

IO(RESET) = 300

µ

A

1.1

V

Trip threshold voltage

VO decreasing

92

98

%VO

Reset

Hysteresis voltage

Measured at VO

0.5

%VO

Reset

Output low voltage

VI = 2.7 V,

 IO(RESET) = 1mA

0.15

0.4

V

Leakage current

V(RESET) = 5 V

1

µ

A

RESET time-out delay

200

ms

NOTE 2: Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 10V.

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,

V

= V

O(typ) 

+ 1 V, I

O

 = 1 mA, EN = 0 V, C

O

 = 10 

µ

F (unless otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input current (EN)

EN = 0 V

–1

0

1

µ

A

Input current (EN)

EN = VI

–1

1

µ

A

TPS76728

IO = 1 A,

TJ = 25

°

C

500

TPS76728

IO = 1 A,

TJ = –40

°

C to 125

°

C

825

TPS76730

IO = 1 A,

TJ = 25

°

C

450

Dropout voltage

(See Note 4)

TPS76730

IO = 1 A,

TJ = –40

°

C to 125

°

C

675

mV

(See Note 4)

TPS76733

IO = 1 A,

TJ = 25

°

C

350

mV

TPS76733

IO = 1 A,

TJ = –40

°

C to 125

°

C

575

TPS76750

IO = 1 A,

TJ = 25

°

C

230

TPS76750

IO = 1 A,

TJ = –40

°

C to 125

°

C

380

NOTES:

3. If VO

 1.8 V then Vimax = 10 V, Vimin = 2.7 V:

Line Reg. (mV)

+ ǒ

%

ń

V

Ǔ  

V

O

ǒ

V

imax

*

2.7 V

Ǔ

100

 

1000

If VO 

 2.5 V then Vimax = 10 V, Vimin = VO + 1 V:

Line Reg. (mV)

+ ǒ

%

ń

V

Ǔ  

V

O

ǒ

V

imax

*

ǒ

V

O

)

1 V

Ǔ

Ǔ

100

 

1000

4. IN voltage equals VO(Typ) – 100 mV; TPS76701 output voltage set to 3.3 V nominal with external resistor divider. TPS76715,

TPS76718, TPS76725, and TPS76727 dropout voltage limited by input voltage range limitations (i.e., TPS76730 input voltage needs

to drop to 2.9 V for purpose of this test).

Table of Graphs

FIGURE

VO

Output voltage

vs Output current

2, 3, 4

VO

Output voltage

vs Free-air temperature

5, 6, 7

Ground current

vs Free-air temperature

8, 9

Power supply ripple rejection

vs Frequency

10

Output noise

vs Frequency

11

Zo

Output impedance

vs Frequency

12

VDO

Dropout voltage

vs Free-air temperature

13

Line transient response

14, 16

Load transient response

15, 17

Output voltage

vs Time

18

Dropout voltage

vs Input voltage

19

Equivalent series resistance (ESR)

vs Output current

21 – 24

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 2

IO – Output Current – A

TPS76733

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

3.2830

3.2815

3.2800

0.1

0.3

3.2825

3.2820

3.2810

0.2

0.8

1

3.2835

0

0.9

– Output V

oltage – V

V

O

3.2805

0.4

0.5

0.6 0.7

VI = 4.3 V

TA = 25

°

C

Figure 3

IO – Output Current – A

1.4975

1.4960

1.4950

1.4970

1.4965

1.4955

1.4985

– Output V

oltage – V

V

O

TPS76715

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

1.4980

0.1

0.3

0.2

0.8

1

0

0.9

0.4

0.5

0.6 0.7

VI = 2.7 V

TA = 25

°

C

Figure 4

IO – Output Current – A

TPS76725

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

2.4955

2.4940

2.4920

0.1

0.3

2.4950

2.4945

2.4935

0.2

0.4

0.6

2.4960

0

0.5

– Output V

oltage – V

V

O

VI = 3.5 V

TA = 25

°

C

2.4930

2.4925

0.8

0.7

0.9

1

Figure 5

TA – Free-Air Temperature – 

°

C

TPS76733

OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

– Output V

oltage – V

V

O

3.31

3.28

3.25

–40

0

3.30

3.29

3.27

–20

100

140

3.32

–60

120

3.26

20

40

60

80

VI = 4.3 V

IO = 1 A

IO = 1 mA

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

10

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 6

TA – Free-Air Temperature – 

°

C

TPS76715

OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

– Output V

oltage – V

V

O

1.515

1.500

1.485

–40

0

1.510

1.505

1.495

–20

100

–60

120

1.490

20

40

60

80

VI = 2.7 V

IO = 1 A

IO = 1 mA

140

Figure 7

TA – Free-Air Temperature – 

°

C

TPS76725

OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

– Output V

oltage – V

V

O

–40

0

–20

100

–60

120

20

40

60

80

2.515

2.500

2.480

2.510

2.505

2.495

2.490

2.485

VI = 3.5 V

IO = 1 A

IO = 1 mA

TA – Free-Air Temperature – 

°

C

TPS76733

GROUND CURRENT

vs

FREE-AIR TEMPERATURE

Ground Current – 

A

µ

92

84

72

90

88

82

80

78

76

74

86

–40

0

–20

100

–60

120

20

40

60

80

140

VI = 4.3 V

IO = 500 mA

IO = 1 A

IO = 1 mA

Figure 8

Figure 9

TA – Free-Air Temperature – 

°

C

TPS76715

GROUND CURRENT

vs

FREE-AIR TEMPERATURE

Ground Current – 

A

µ

–40

0

–20

100

–60

120

20

40

60

80

140

VI = 2.7 V

IO = 1 A

100

95

90

85

80

75

IO = 1 mA

IO = 500 mA

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

11

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TYPICAL CHARACTERISTICS

Figure 10

100k

10k

PSRR – Power Supply Ripple Rejection – dB

f – Frequency – Hz

POWER SUPPLY RIPPLE REJECTION

vs

FREQUENCY

70

60

50

40

30

20

10

0

– 10

TPS76733

90

80

1k

100

10

1M

VI = 4.3 V

CO = 10 

µ

F

IO = 1 A

TA = 25

°

C

TPS76733

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

Figure 11

f – Frequency – Hz

102

103

104

105

10–5

10–6

10–8

10–7

IO = 7 mA

IO = 1 A

VI = 4.3 V

CO = 10 

µ

F

TA = 25

°

C

V

Hz

Output Spectral Noise Density – 

µ

Figure 12

f – Frequency – kHz

– Output Impedance –

Z

o

101

102

105

106

0

10–1

10–2

104

103

IO = 1 mA

IO = 1 A

VI = 4.3 V

CO = 10 

µ

F

TA = 25

°

C

TPS76733

OUTPUT IMPEDANCE

vs

FREQUENCY

Figure 13

TA – Free-Air Temperature – 

°

C

–40

0

20

120

103

–60

40

60

80 100

– Dropout V

oltage – mV

V

DO

TPS76733

DROPOUT VOLTAGE

vs

FREE-AIR TEMPERATURE

102

101

100

10–1

10–2

–20

140

IO = 1 A

IO = 10 mA

IO = 0

CO = 10 

µ

F

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

12

POST OFFICE BOX 655303 

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TYPICAL CHARACTERISTICS

Figure 14

V

O

– Change in

10

0

3.7

2.7

TPS76715

LINE TRANSIENT RESPONSE

V

I

t – Time – 

µ

s

0

60

40

20

80 100

140

120

160 180 200

– Input V

oltage – V

Output 

V

oltage – mV

CL = 10 

µ

F

TA = 25

°

C

–10

Figure 15

t – Time – 

µ

s

TPS76715

LOAD TRANSIENT RESPONSE

I    – Output Current – 

A

O

V

O

– Change in

Output 

V

oltage – mV

CL = 100 

µ

F

TA = 25

°

C

1

0.5

0

0

60

40

20

80 100

140

120

160 180 200

0

50

100

–50

–100

Figure 16

TPS76733

LINE TRANSIENT RESPONSE

t – Time – 

µ

s

V

O

– Change in

V

I

– Input V

oltage – V

Output 

V

oltage – mV

5.3

60

40

20

80 100

140

120

160 180 200

CL = 10 

µ

F

TA = 25

°

C

0

4.3

10

0

–10

Figure 17

t – Time – 

µ

s

TPS76733

LOAD TRANSIENT RESPONSE

I    – Output Current – 

A

O

V

O

– Change in

Output 

V

oltage – mV

1

0.5

60

40

20

80 100

140

120

160 180 200

0

CL = 100 

µ

F

TA = 25

°

C

0

0

50

100

–50

–100

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

13

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 18

t – Time – 

µ

s

TPS76733

OUTPUT VOLTAGE

vs

TIME (AT STARTUP)

3

2

60

40

20

80 100

140

120

160 180 200

0

V

O

– Output V

oltage – V

0

1

4

Enable Pulse – V

0

Figure 19

VI – Input Voltage – V

600

300

0

3

4

500

400

200

3.5

2.5

– Dropout V

oltage – mV

100

4.5

5

V

DO

900

800

700

TA = 125

°

C

TA = –40

°

C

TA = 25

°

C

IO = 1 A

TPS76701

DROPOUT VOLTAGE

vs

INPUT VOLTAGE

IN

EN

OUT

+

GND

CO

ESR

RL

VI

To Load

Figure 20. Test Circuit for Typical Regions of Stability (Figures 21 through 24) (Fixed Output Options)

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

14

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 21

0.1

0

200

400

600

800

1000

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE

vs

OUTPUT CURRENT

10

IO – Output Current – mA

ESR – Equivalent series restance –

1

Vo = 3.3 V

CL = 4.7 

µ

F

VI = 4.3 V

TA = 25

°

C

Region of Stability

Region of Instability

Figure 22

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE

vs

OUTPUT CURRENT

IO – Output Current – mA

ESR – Equivalent Series Resistance –

0.1

0

200

400

600

800

1000

10

1

Vo = 3.3 V

Cl = 4.7 

µ

F

VI = 4.3 V

TJ = 125

°

C

Region of Stability

Region of Instability

Figure 23

0.1

0

200

400

600

800

1000

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE

vs

OUTPUT CURRENT

10

IO – Output Current – mA

ESR – Equivalent series restance –

1

Region of Instability

Region of Stability

Vo = 3.3 V

CL = 22 

µ

F

VI = 4.3 V

TA = 25

°

C

Figure 24

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE

vs

OUTPUT CURRENT

0.1

0

200

400

600

800

1000

10

1

IO – Output Current – mA

Vo = 3.3 V

Cl = 22 

µ

F

VI = 4.3 V

TJ = 125

°

C

Region of Stability

Region of Instability

ESR – Equivalent series restance –

† Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added

externally, and PWB trace resistance to CO.

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

15

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

The TPS767xx family includes eight fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, 2.7 V, 2.8 V, 3.0 V,

3.3 V, and 5.0 V), and an adjustable regulator, the TPS76701 (adjustable from 1.5 V to 5.5 V).

device operation

The TPS767xx features very low quiescent current, which remains virtually constant even with varying loads.

Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the

load current through the regulator (I

B

 = I

C

/

β

). The TPS767xx uses a PMOS transistor to pass current; because

the gate of the PMOS is voltage driven, operating current is low and invariable over the full load range.

Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into

dropout. The resulting drop in 

β

 forces an increase in I

B

 to maintain the load. During power up, this translates

to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,

it means rapid battery discharge when the voltage decays below the minimum required for regulation. The

TPS767xx quiescent current remains low even when the regulator drops out, eliminating both problems.

The TPS767xx family also features a shutdown mode that places the output in the high-impedance state

(essentially equal to the feedback-divider resistance) and reduces quiescent current to 2 

µ

A. If the shutdown

feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated output

voltage is typically reestablished in 120 

µ

s.

minimum load requirements

The TPS767xx family is stable even at zero load; no minimum load is required for operation.

FB - pin connection (adjustable version only)

The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option . The output

voltage is sensed through a resistor divider network to close the loop as it is shown in Figure 26. Normally, this

connection should be as short as possible; however, the connection can be made near a critical circuit to

improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and

noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup

is essential.

external capacitor requirements

An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047 

µ

F or larger) improves

load transient response and noise rejection if the TPS767xx is located more than a few inches from the power

supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load

transients with fast rise times are anticipated.

Like all low dropout regulators, the TPS767xx requires an output capacitor connected between OUT and GND

to stabilize the internal control loop. The minimum recommended capacitance value is 10 

µ

F and the ESR

(equivalent series resistance) must be between 50 m

 and 1.5 

. Capacitor values 10 

µ

F or larger are

acceptable, provided the ESR is less than 1.5 

. Solid tantalum electrolytic, aluminum electrolytic, and

multilayer ceramic capacitors are all suitable, provided they meet the requirements described above. Most of

the commercially available 10 

µ

F surface-mount ceramic capacitors, including devices from Sprague and

Kemet, meet the ESR requirements stated above.

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

16

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

external capacitor requirements (continued)

RESET

OUT

OUT

7

6

5

IN

IN

EN

GND

3

16

14

13

VI

C1

0.1 

µ

F

RESET

VO

10 

µ

F

+

TPS767xx

CO

250 k

Figure 25. Typical Application Circuit (Fixed Versions)

programming the TPS76701 adjustable LDO regulator

The output voltage of the TPS76701 adjustable regulator is programmed using an external resistor divider as

shown in Figure 26. The output voltage is calculated using:

V

O

+

V

ref

 

ǒ

1

)

R1

R2

Ǔ

(1)

Where

V

ref

 = 1.1834 V typ (the internal reference voltage)

Resistors R1 and R2 should be chosen for approximately 50-

µ

A divider current. Lower value resistors can be

used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage

currents at FB increase the output voltage error. The recommended design procedure is to choose

R2 = 30.1 k

 to set the divider current at 50 

µ

A and then calculate R1 using:

R1

+

ǒ

V

O

V

ref

*

1

Ǔ

 

R2

(2)

OUTPUT

VOLTAGE

R1

R2

2.5 V

3.3 V

3.6 V

4.75 V

UNIT

33.2

53.6

61.9

90.8

30.1

30.1

30.1

30.1

k

k

k

k

OUTPUT VOLTAGE

PROGRAMMING GUIDE

VO

VI

RESET

OUT

FB / NC

R1

R2

GND

EN

IN

0.9 V

1.7 V

TPS76701

Reset Output

0.1 

µ

F

250 k

CO

Figure 26. TPS76701 Adjustable LDO Regulator Programming

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

17

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

reset indicator

The TPS767xx features a RESET output that can be used to monitor the status of the regulator. The internal

comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal

regulated value, the RESET output transistor turns on, taking the signal low. The open-drain output requires

a pullup resistor. If not used, it can be left floating. RESET can be used to drive power-on reset circuitry or as

a low-battery indicator. RESET does not assert itself when the regulated output voltage falls outside the

specified 2% tolerance, but instead reports an output voltage low relative to its nominal regulated value (refer

to timing diagram for start-up sequence).

regulator protection

The TPS767xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input

voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the

input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be

appropriate.

The TPS767xx also features internal current limiting and thermal protection. During normal operation, the

TPS767xx limits output current to approximately 1.7 A. When current limiting engages, the output voltage scales

back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device

failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of

the device exceeds 150

°

C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below

130

°

C(typ), regulator operation resumes.

power dissipation and junction temperature

Specified regulator operation is assured to a junction temperature of 125

°

C; the maximum junction temperature

should be restricted to 125

°

C under normal operating conditions. This restriction limits the power dissipation

the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,

calculate the maximum allowable dissipation, P

D(max)

, and the actual dissipation, P

D

, which must be less than

or equal to P

D(max)

.

The maximum-power-dissipation limit is determined using the following equation:

P

D(max)

+

T

J

max

*

T

A

R

q

JA

Where

T

J

max

 

is the maximum allowable junction temperature

T

is the ambient temperature.

R

θ

JA

 is the thermal resistance junction-to-ambient for the package, i.e., 172

°

C/W for the 8-terminal

SOIC and 32.6

°

C/W for the 20-terminal PWP with no airflow.

The regulator dissipation is calculated using:

P

D

+

ǒ

V

I

*

V

O

Ǔ

 

I

O

Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the

thermal protection circuit.

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

18

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**)    

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047 / B 03/95

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A  MIN

A  MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0

°

– 8

°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Four center pins are connected to die mount pad.

E. Falls within JEDEC MS-012

background image

TPS76715Q, TPS76718Q, TPS76725Q, TPS76727Q

TPS76728Q, TPS76730Q  TPS76733Q, TPS76750Q, TPS76701Q

FAST-TRANSIENT-RESPONSE 1-A LOW-DROPOUT VOLTAGE REGULATORS

 

SLVS208C – MAY 1999 – REVISED SEPTEMBER 1999

19

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL DATA

PWP (R-PDSO-G**)    

PowerPAD

 PLASTIC SMALL-OUTLINE PACKAGE

4073225/E 03/97

0,50

0,75

0,25

0,15 NOM

Thermal Pad

(See Note D)

Gage Plane

28

24

7,70

7,90

20

6,40

6,60

9,60

9,80

6,60

6,20

11

0,19

4,50

4,30

10

0,15

20

A

1

0,30

1,20 MAX

16

14

5,10

4,90

PINS **

4,90

5,10

DIM

A  MIN

A  MAX

0,05

Seating Plane

0,65

0,10

M

0,10

0

°

– 8

°

20-PIN SHOWN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusions.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically

and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MO-153

PowerPAD is a trademark of Texas Instruments Incorporated.

background image

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

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 1999, Texas Instruments Incorporated