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Features

® Data retention in the absence of

power

® Automatic write-protection

during power-up/power-down

cycles

® Industry-standard 28-pin 8K x 8

pinout

® Conventional SRAM operation;

unlimited write cycles

® 10-year minimum data retention

in absence of power

® Battery internally isolated until

power is applied

Pin Connections

General Description

The CMOS bq4010 is a nonvolatile

65,536-bit static RAM organized as

8,192 words by 8 bits. The integral

control circuitry and lithium energy

source provide reliable nonvolatility

coupled with the unlimited write

cycles of standard SRAM. 

The control circuitry constantly

monitors the single 5V supply for an

out-of-tolerance condition. When V

CC

falls out of tolerance, the SRAM is

unconditionally write-protected to

prevent inadvertent write operation.

At this time the integral energy

source is switched on to sustain the

memory until after V

CC

 returns valid.

The bq4010 uses an extremely low

st andby current CMOS  SR AM,

coupled with a small lithium coin

cell to provide nonvolatility without

long write-cycle times and the write-

cycle limitations associated with

EEPROM.

The bq4010 requires no external cir-

cuitry and is socket-compatible with

industry-standard SRAMs and most

EPROMs and EEPROMs.

Pin Names

A

0

 –A

12

Address inputs

DQ

0

–DQ

7

Data input/output

CE

Chip enable input

OE

Output enable input

WE

Write enable input

NC

No connect

V

CC

+5 volt supply input

V

SS

Ground

8Kx8 Nonvolatile SRAM

bq4010/bq4010Y

Sept. 1996 D

Block Diagram

Selection Guide

Part

Number

Maximum

Access 

Time (ns)

Negative

 Supply

Tolerance

Part

Number

Maximum

 Access 

Time (ns)

Negative

 Supply

Tolerance

bq4010Y -70

70

-10%

bq4010 -85

85

-5%

bq4010Y -85

85

-10%

bq4010 -150

150

-5%

bq4010Y -150

150

-10%

bq4010 -200

200

-5%

bq4010Y -200

200

-10%

1

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Functional Description

When power is valid, the bq4010 operates as a standard

CMOS SRAM. During power-down and power-up cycles,

the bq4010 acts as a nonvolatile memory, automatically

protecting and preserving the memory contents. 

Power-down/power-up control circuitry constantly

monitors the V

CC

 supply for a power-fail-detect threshold

V

PFD

. The bq4010 monitors for V

PFD

 = 4.62V typical for

use in systems with 5% supply tolerance. The bq4010Y

monitors for V

PFD

 = 4.37V typical for use in systems with

10% supply tolerance. 

When V

CC

 falls below the V

PFD

 threshold, the SRAM

automatically write-protects the data. All outputs

become high impedance, and all inputs are treated as

“don’t care.” If a valid access is in process at the time of

power-fail detection, the memory cycle continues to com-

pletion. If the memory cycle fails to terminate within

time t

WPT

, write-protection takes place.

As V

CC

 falls past V

PFD

 and approaches 3V, the control

circuitry switches to the internal lithium backup supply,

which provides data retention until valid V

CC

 is applied.

When V

CC

 returns to a level above the internal backup

cell voltage, the supply is switched back to V

CC

. After

V

CC

 ramps above the V

PFD

 threshold, write-protection

continues for a time t

CER

 (120ms maximum) to allow for

processor stabilization. Normal memory operation may

resume after this time. 

The internal coin cell used by the bq4010 has an

extremely long shelf life and provides data retention for

more than 10 years in the absence of system power. 

As shipped from Benchmarq, the integral lithium cell is

electrically isolated from the memory. (Self-discharge in

this condition is approximately 0.5% per year.) Following

the first application of V

CC

, this isolation is broken, and

the lithium backup cell provides data retention on

subsequent power-downs.

Truth Table 

Mode

CE

WE

OE

I/O Operation

Power

Not selected

H

X

X

High Z

Standby

Output disable

L

H

H

High Z

Active

Read

L

H

L

D

OUT

Active

Write

L

L

X

D

IN

Active

Absolute Maximum Ratings 

Symbol

Parameter

Value

Unit

Conditions

V

CC

DC voltage applied on V

CC

 relative to V

SS

-0.3 to 7.0

V

V

T

DC voltage applied on any pin excluding V

CC

relative to V

SS

-0.3 to 7.0

V

V

T

 

 V

CC

 + 0.3

T

OPR

Operating temperature

0 to +70

°C

Commercial

-40 to +85

°C

Industrial “N” 

T

STG

Storage temperature

-40 to +70

°C

Commercial

-40 to +85

°C

Industrial “N” 

T

BIAS

Temperature under bias

-10 to +70

°C

Commercial

-40 to +85

°C

Industrial “N” 

T

SOLDER

Soldering temperature

+260

°C

For 10 seconds

Note:  

Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation 

should be limited to the Recommended DC Operating Conditions detailed in this data sheet.  Exposure to con-

ditions beyond the operational limits for extended periods of time may affect device reliability.

bq4010/bq4010Y 

Sept. 1996 D

6-2

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Recommended DC Operating Conditions

 

(TA = TOPR)

 

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Notes

V

CC

Supply voltage

4.5

5.0

5.5

V

bq4010Y/bq4010Y-xxxN

4.75

5.0

5.5

V

bq4010

V

SS

Supply voltage 

0

0

0

V

V

IL

Input low voltage

-0.3

-

0.8

V

V

IH

Input high voltage

2.2

-

V

CC

 + 0.3

V

Note: 

Typical values indicate operation at T

A

 = 25°C. 

DC Electrical Characteristics 

(TA = TOPR, VCCmin  

 VCC  

  VCCmax)

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Conditions/Notes

I

LI

Input leakage current

-

-

±

 1

µ

A

V

IN

 = V

SS

 to V

CC

I

LO

Output leakage current

-

-

±

 1

µ

A

CE = V

IH

  or OE = V

IH

 or

WE = V

IL

V

OH

Output high voltage

2.4

-

-

V

I

OH

 = -1.0 mA

V

OL

Output low voltage

-

-

0.4

V

I

OL

 = 2.1 mA

I

SB1

Standby supply current

-

4

7

mA

CE = V

IH

I

SB2

Standby supply current

-

2.5

4

mA

CE 

 V

CC

 - 0.2V,

0V 

 V

IN

 

 0.2V,

or V

IN

 

 V

CC

 - 0.2V

I

CC

Operating supply current

-

65

75

mA

Min. cycle, duty = 100%, 

CE = V

IL

, I

I/O

 = 0mA

V

PFD

Power-fail-detect voltage

4.55

4.62

4.75

V

bq4010

4.30

4.37

4.50

V

bq4010Y

V

SO

Supply switch-over voltage

-

3

-

V

Note: 

Typical values indicate operation at T

A

 = 25°C, V

CC

 = 5V.

 bq4010/bq4010Y

Sept. 1996 D

Capacitance

 

(TA = 25°C, F = 1MHz, VCC = 5.0V)

 

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Conditions

C

I/O

Input/output capacitance

-

-

10

pF

Output voltage = 0V

C

IN

Input capacitance

-

-

10

pF

Input voltage = 0V

Note:

These parameters are sampled and not 100% tested.

6-3

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AC Test Conditions 

Parameter

Test Conditions

Input pulse levels

0V to 3.0V

Input rise and fall times

5 ns

Input and output timing reference levels

1.5 V (unless otherwise specified)

Output load (including scope and jig)

See Figures 1 and 2

Figure 1. Output Load A

Figure 2. Output Load B

Read Cycle

 

(TA = TOPR, VCCmin  

 VCC  

  VCCmax)

Symbol

Parameter

-70/-70N

-85/-85N

-150/-150N

-200

Unit

Conditions

Min.

Max.

Min.

Max.

Min.

Max. Min.

Max.

t

RC

Read cycle time

70

-

85

-

150

-

200

-

ns

t

AA

Address access time

-

70

-

85

-

150

-

200

ns

Output load A

t

ACE

Chip enable access time

-

70

-

85

-

150

-

200

ns

Output load A

t

OE

Output enable to output

valid

-

35

-

45

-

70

-

90

ns

Output load A

t

CLZ

Chip enable to output

in low Z

5

-

5

-

10

-

10

-

ns

Output  load  B

t

OLZ

Output enable to output

in low Z

5

-

5

-

5

-

5

-

ns

Output  load  B

t

CHZ

Chip disable to output

in high Z

0

25

0

40

0

60

0

70

ns

Output  load  B

t

OHZ

Output disable to

output in high Z

0

25

0

30

0

50

0

70

ns

Output  load  B

t

OH

Output hold from

address change

10

-

10

-

10

-

10

-

ns

Output load A

Sept. 1996 D

bq4010/bq4010Y  

6-4

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Read Cycle No. 2 (CE Access) 

1,3,4

Read Cycle No. 3 (OE Access) 

1,5

Read Cycle No. 1 (Address Access) 

1,2

Sept. 1996 D

 bq4010/bq4010Y

Notes:  

1.

WE is held high for a read cycle.

2.

Device is continuously selected:  CE = OE = V

IL

.

3.   Address is valid prior to or coincident with CE transition low.

4.  OE = V

IL

.

5.

Device is continuously selected:  CE = V

IL

.

6-5

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Write Cycle  

(TA = TOPR, VCCmin  

 VCC  

  VCCmax)

Symbol

Parameter

-70/-70N

-85/-85N

-150/-150N

-200

Units

Conditions/Notes

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

t

WC

Write cycle time

70

-

85

-

150

-

200

-

ns

t

CW

Chip enable to end

of write

55

-

75

-

100

-

150

-

ns

(1)

t

AW

Address valid to end

of write

55

-

75

-

90

-

150

-

ns

(1)

t

AS

Address  setup  time

0

-

0

-

0

-

0

-

ns

Measured from

address valid to

beginning of write. (2)

t

WP

Write pulse width

55

-

65

-

90

-

130

-

ns

Measured from

beginning of write to

end of write. (1)

t

WR1

Write recovery time

(write cycle 1)

5

-

5

-

5

-

5

-

ns

Measured from WE

going high to end of

write cycle. (3)

t

WR2

Write recovery time

(write cycle 2)

15

-

15

-

15

-

15

-

ns

Measured from CE

going high to end of

write cycle. (3)

t

DW

Data valid to end of

write

30

-

35

-

50

-

70

-

ns

Measured from first

low-to-high transition

of either CE or WE.

t

DH1

Data hold time

(write cycle 1)

0

-

0

-

0

-

0

-

ns

Measured from WE

going high to end of

write cycle. (4)

t

DH2

Data hold time

(write cycle 2)

10

-

10

-

0

-

0

-

ns

Measured from CE

going high to end of

write cycle. (4)

t

WZ

Write enabled to

output in high Z

0

25

0

30

0

50

0

70

ns

I/O pins are in output

state. (5)

t

OW

Output active from

end of write

5

-

5

-

5

-

5

-

ns

I/O pins are in output

state. (5)

Notes:

1.

A write ends at the earlier transition of CE going high and WE going high.

2.

A write occurs during the overlap of a low CE and a low WE.  A write begins at the later transition 

of CE going low and WE going low.

3.

Either t

WR1

 or t

WR2

 must be met.

4.

Either t

DH1

 or t

DH2

 must be met.

5.

If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in 

high-impedance state.

Sept. 1996 D

bq4010/bq4010Y 

6-6

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Write Cycle No. 1 (WE-Controlled) 

1,2,3

Write Cycle No. 2 (CE-Controlled) 

1,2,3,4,5

Sept. 1996 D

   bq4010/bq4010Y

Notes: 1.

CE or WE must be high during address transition.

2.

Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the 

outputs must not be applied.

3.

If OE is high, the I/O pins remain in a state of high impedance.

4.

Either t

WR1

 or t

WR2

 must be met.

5.

Either t

DH1

 or t

DH2

 must be met.

6-7

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Power-Down/Power-Up Cycle

 

(TA = TOPR

)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

t

PF

V

CC

 slew, 4.75 to 4.25 V

300

-

-

µ

s

t

FS

V

CC

 slew, 4.25 to V

SO

10

-

-

µ

s

t

PU

V

CC

 slew, V

SO

 to V

PFD

 (max.)

0

-

-

µ

s

t

CER

Chip enable recovery time

40

80

120

ms

Time during which SRAM is

write-protected after V

CC

 passes

V

PFD

 on power-up.

t

DR

Data-retention time in 

absence of V

CC

10

-

-

years

T

A

 = 25°C.  (2)

t

DR-N

Data-retention time in 

absence of V

CC

6

-

-

years

T

A

 = 25°C (2); industrial

temperature range (-N) only.

t

WPT

Write-protect time

40

100

150

µ

s

Delay after V

CC

 slews down past

V

PFD

 before SRAM is write-

protected.

Notes:

1.

Typical values indicate operation at T

A

 = 25°C, V

CC

 = 5V.

2.

Battery is disconnected from circuit until after V

CC

 is applied for the first time. t

DR

 is the

accumulated time in absence of power beginning when power is first applied to the device.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode 

may affect data integrity.

Power-Down/Power-Up Timing

Sept. 1996 D

bq4010/bq4010Y

6-8

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Sept. 1996 D

bq4010/bq4010Y

Change No.

Page No.

Description

1

2, 3, 4, 6, 8, 9

Added industrial temperature range for bq4010YMA-85N and -150N.

2

1, 4, 6, 9

Added 70 ns speed grade for bq4010-70 and bq4010Y-70 and added

industrial temperature range for bq4010YMA-70N.

3

1

Removed 70ns speed grade for bq4010-70.

Notes:

Change 1 = Sept 1991 B changes from Sept. 1990 A.

Change 2 = Feb. 1994 C changes from Sept. 1991 B.

Change 3 = Sept. 1996 D changes from Feb. 1994 C.

Data Sheet Revision History

MA: 28-Pin A-Type Module 

28-Pin MA (A-Type Module)

Dimension

Inches

Millimeters

Min.

Max.

Min.

Max.

A

0.365

0.375

9.27

9.53

A1

0.015

-

0.38

-

B

0.017

0.023

0.43

0.58

C

0.008

0.013

0.20

0.33

D

1.470

1.500

37.34

38.10

E

0.710

0.740

18.03

18.80

e

0.590

0.630

14.99

16.00

G

0.090

0.110

2.29

2.79

L

0.120

0.150

3.05

3.81

S

0.075

0.110

1.91

2.79

6-9

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bq4010/bq4010Y

Sept. 1996 D

Ordering Information

bq4010     MA -            

Speed Options:

 85 =  85 ns

150 = 150 ns

200 = 200 ns

Package Option:

MA = A-type module

Supply Tolerance:

no mark = 5% negative supply tolerance

Y = 10% negative supply tolerance

Device:

bq4010    8K x 8 NVSRAM

Temperature:

blank = Commercial (0 to +70°C)

N = Industrial (-40 to +85°C)*

*Note:  

Only 10% supply (“Y”) version is available in industrial 

temperature range; contact factory for speed grade 

availability.

6-10

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

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Copyright 

©

 1999, Texas Instruments Incorporated