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Features

➤ Data retention for at least 10

years without power

➤ Automatic write-protection during

power-up/power-down cycles

➤ Conventional SRAM operation,

including unlimited write cycles

➤ Internal isolation of battery be-

fore power application

➤ Industry standard 32-pin DIP

pinout

General Description

The CMOS bq4013/Y is a nonvolatile

1,048,576-bit static RAM organized as

131,072 words by 8 bits. The integral

control circuitry and lithium energy

source provide reliable nonvolatility

coupled with the unlimited write cy-

cles of standard SRAM.

The control circuitry constantly

monitors the single 5V supply for an

out-of-tolerance condition.

When

V

CC

falls out of tolerance, the SRAM

is unconditionally write-protected to

prevent inadvertent write operation.

At this time the integral energy

source is switched on to sustain the

memory until after V

CC

returns valid.

The bq4013/Y uses an extremely

low standby current CMOS SRAM,

coupled with a small lithium coin

cell to provide nonvolatility without

long write-cycle times and the

write-cycle limitations associated

with EEPROM.

The bq4013/Y requires no external

circuitry and is socket-compatible

with industry-standard SRAMs and

most EPROMs and EEPROMs.

1

bq4013/Y

Pin Connections

9/96 D

A

0

–A

16

Address inputs

DQ

0

–DQ

7

Data input/output

CE

Chip enable input

OE

Output enable input

WE

Write enable input

NC

No connect

V

CC

Supply voltage input

V

SS

Ground

Selection Guide

Part

Number

Maximum

Access

Time (ns)

Negative

Supply

Tolerance

Part

Number

Maximum

Access

Time (ns)

Negative

Supply

Tolerance

bq4013YMA -70

70

-10%

bq4013MA -85

85

-5%

bq4013YMA -85

85

-10%

bq4013MA-120

120

-5%

bq4013YMA-120

120

-10%

128Kx8 Nonvolatile SRAM

Pin Names

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Functional Description

When power is valid, the bq4013/Y operates as a stan-

dard CMOS SRAM. During power-down and power-up

cycles, the bq4013/Y acts as a nonvolatile memory, auto-

matically protecting and preserving the memory con-

tents.

Power-down/power-up control circuitry constantly moni-

tors the V

CC

supply for a power-fail-detect threshold

V

PFD

. The bq4013 monitors for V

PFD

= 4.62V typical for

use in systems with 5% supply tolerance. The bq4013Y

monitors for V

PFD

= 4.37V typical for use in systems

with 10% supply tolerance.

When V

CC

falls below the V

PFD

threshold, the SRAM au-

tomatically write-protects the data. All outputs become

high impedance, and all inputs are treated as “don’t

care.”

If a valid access is in process at the time of

power-fail detection, the memory cycle continues to com-

pletion. If the memory cycle fails to terminate within

time t

WPT

, write-protection takes place.

As V

CC

falls past V

PFD

and approaches 3V, the control

circuitry switches to the internal lithium backup supply,

which provides data retention until valid V

CC

is applied.

When V

CC

returns to a level above the internal backup

cell voltage, the supply is switched back to V

CC

. After

V

CC

ramps above the V

PFD

threshold, write-protection

continues for a time t

CER

(120ms maximum) to allow for

processor stabilization. Normal memory operation may

resume after this time.

The internal coin cell used by the bq4013/Y has an ex-

tremely long shelf life and provides data retention for

more than 10 years in the absence of system power.

As shipped from Unitrode, the integral lithium cell of

the MA-type module is electrically isolated from the

memory. (Self-discharge in this condition is approxi-

mately 0.5% per year.) Following the first application of

V

CC

, this isolation is broken, and the lithium backup cell

provides data retention on subsequent power-downs.

2

bq4013/Y

OE

CE

BD-42

WE

Power

Lithium

Cell

Power-Fail

Control

128K x 8

SRAM

Block

CE

CON

V

CC

A

0

–A

16

DQ

0

–DQ

7

Block Diagram

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3

bq4013/Y

Truth Table

Mode

CE

WE

OE

I/O Operation

Power

Not selected

H

X

X

High Z

Standby

Output disable

L

H

H

High Z

Active

Read

L

H

L

D

OUT

Active

Write

L

L

X

D

IN

Active

Absolute Maximum Ratings

Symbol

Parameter

Value

Unit

Conditions

V

CC

DC voltage applied on V

CC

relative to V

SS

-0.3 to 7.0

V

V

T

DC voltage applied on any pin excluding V

CC

relative to V

SS

-0.3 to 7.0

V

V

T

≤ V

CC

+ 0.3

T

OPR

Operating temperature

0 to +70

°C

Commercial

-40 to +85

°C

Industrial “N”

T

STG

Storage temperature

-40 to +70

°C

Commercial

-40 to +85

°C

Industrial “N”

T

BIAS

Temperature under bias

-10 to +70

°C

Commercial

-40 to +85

°C

Industrial “N”

T

SOLDER

Soldering temperature

+260

°C

For 10 seconds

Note:

Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation

should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con-

ditions beyond the operational limits for extended periods of time may affect device reliability.

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4

bq4013/Y

Recommended DC Operating Conditions

(TA = TOPR)

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Notes

V

CC

Supply voltage

4.5

5.0

5.5

V

bq4013Y

4.75

5.0

5.5

V

bq4013

V

SS

Supply voltage

0

0

0

V

V

IL

Input low voltage

-0.3

-

0.8

V

V

IH

Input high voltage

2.2

-

V

CC

+ 0.3

V

Note:

Typical values indicate operation at T

A

= 25°C.

DC Electrical Characteristics

(TA = TOPR, VCCmin

≤ VCC ≤ VCCmax)

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Conditions/Notes

I

LI

Input leakage current

-

-

± 1

µA

V

IN

= V

SS

to V

CC

I

LO

Output leakage current

-

-

± 1

µA

CE = V

IH

or OE = V

IH

or

WE = V

IL

V

OH

Output high voltage

2.4

-

-

V

I

OH

= -1.0 mA

V

OL

Output low voltage

-

-

0.4

V

I

OL

= 2.1 mA

I

SB1

Standby supply current

-

4

7

mA

CE = V

IH

I

SB2

Standby supply current

-

2.5

4

mA

CE

≥ V

CC

- 0.2V,

0V

≤ V

IN

≤ 0.2V,

or V

IN

≥ V

CC

- 0.2V

I

CC

Operating supply current

-

75

105

mA

Min. cycle, duty = 100%,

CE = V

IL

, I

I/O

= 0mA

V

PFD

Power-fail-detect voltage

4.55

4.62

4.75

V

bq4013

4.30

4.37

4.50

V

bq4013Y

V

SO

Supply switch-over voltage

-

3

-

V

Note:

Typical values indicate operation at T

A

= 25°C, V

CC

= 5V.

Capacitance

(TA = 25°C, F = 1MHz, VCC = 5.0V)

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Conditions

C

I/O

Input/output capacitance

-

-

10

pF

Output voltage = 0V

C

IN

Input capacitance

-

-

10

pF

Input voltage = 0V

Note:

These parameters are sampled and not 100% tested.

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5

bq4013/Y

AC Test Conditions

Parameter

Test Conditions

Input pulse levels

0V to 3.0V

Input rise and fall times

5 ns

Input and output timing reference levels

1.5 V (unless otherwise specified)

Output load (including scope and jig)

See Figures 1 and 2

Figure 2. Output Load B

Figure 1. Output Load A

Read Cycle

(TA = TOPR, VCCmin

≤ VCC ≤ VCCmax)

Symbol

Parameter

-70/-70N

-85/-85N

-120

Unit

Conditions

Min.

Min.

Min.

Max.

Min.

Max.

t

RC

Read cycle time

70

-

85

-

120

-

ns

t

AA

Address access time

-

70

-

85

-

120

ns

Output load A

t

ACE

Chip enable access time

-

70

-

85

-

120

ns

Output load A

t

OE

Output enable to output valid

-

35

-

45

-

60

ns

Output load A

t

CLZ

Chip enable to output in low Z

5

-

5

-

5

-

ns

Output load B

t

OLZ

Output enable to output in low Z

0

-

0

-

0

-

ns

Output load B

t

CHZ

Chip disable to output in high Z

0

25

0

35

0

45

ns

Output load B

t

OHZ

Output disable to output in high Z

0

25

0

25

0

35

ns

Output load B

t

OH

Output hold from address change

10

-

10

-

10

-

ns

Output load A

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6

bq4013/Y

Notes:

1.

WE is held high for a read cycle.

2.

Device is continuously selected: CE = OE = V

IL

.

3.

Address is valid prior to or coincident with CE transition low.

4.

OE = V

IL

.

5.

Device is continuously selected: CE = V

IL

.

Read Cycle No. 3 (OE Access)

1,5

Read Cycle No. 1 (Address Access)

1,2

Read Cycle No. 2 (CE Access)

1,3,4

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7

bq4013/Y

Write Cycle

(TA =TOPR , VCCmin

≤ VCC ≤ VCCmax)

Symbol

Parameter

-70/-70N

-85/-85N

-120

Units

Conditions/Notes

Min. Max. Min. Max. Min. Max.

t

WC

Write cycle time

70

-

85

-

120

-

ns

t

CW

Chip enable to end of

write

65

-

75

-

100

-

ns

(1)

t

AW

Address valid to end of

write

65

-

75

-

100

-

ns

(1)

t

AS

Address setup time

0

-

0

-

0

-

ns

Measured from address valid

to beginning of write. (2)

t

WP

Write pulse width

55

-

65

-

85

-

ns

Measured from beginning of

write to end of write. (1)

t

WR1

Write recovery time

(write cycle 1)

5

-

5

-

5

-

ns

Measured from WE going high

to end of write cycle. (3)

t

WR2

Write recovery time

(write cycle 2)

15

-

15

-

15

-

ns

Measured from CE going high

to end of write cycle. (3)

t

DW

Data valid to end of

write

30

-

35

-

45

-

ns

Measured to first low-to-high

transition of either CE or WE.

t

DH1

Data hold time

(write cycle 1)

0

-

0

-

0

-

ns

Measured from WE going high

to end of write cycle. (4)

t

DH2

Data hold time

(write cycle 2)

10

-

10

-

10

-

ns

Measured from CE going high

to end of write cycle. (4)

t

WZ

Write enabled to output

in  high Z

0

25

0

30

0

40

ns

I/O pins are in output state. (5)

t

OW

Output active from end

of write

0

-

0

-

0

-

ns

I/O pins are in output state. (5)

Notes:

1.

A write ends at the earlier transition of CE going high and WE going high.

2.

A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition

of CE going low and WE going low.

3.

Either t

WR1

or t

WR2

must be met.

4.

Either t

DH1

or t

DH2

must be met.

5.

If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in

high-impedance state.

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8

bq4013/Y

Write Cycle No. 1 (WE-Controlled)

1,2,3

Write Cycle No. 2 (CE-Controlled)

1,2,3,4,5

Notes:

1.

CE or WE must be high during address transition.

2.

Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the

outputs must not be applied.

3.

If OE is high, the I/O pins remain in a state of high impedance.

4.

Either t

WR1

or t

WR2

must be met.

5.

Either t

DH1

or t

DH2

must be met.

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9

bq4013/Y

Power-Down/Power-Up Cycle

(TA = TOPR)

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Conditions

t

PF

V

CC

slew, 4.75 to 4.25 V

300

-

-

µs

t

FS

V

CC

slew, 4.25 to V

SO

10

-

-

µs

t

PU

V

CC

slew, V

SO

to V

PFD

(max.)

0

-

-

µs

t

CER

Chip enable recovery time

40

80

120

ms

Time during which

SRAM is

write-protected after

V

CC

passes V

PFD

on

power-up.

t

DR

Data-retention time in

absence of V

CC

10

-

-

years

T

A

= 25°C. (2)

t

DR-N

Data-retention time in

absence of V

CC

6

-

-

years

T

A

= 25°C (2); industrial

temperature range only

t

WPT

Write-protect time

40

100

150

µs

Delay after V

CC

slews

down past V

PFD

before

SRAM is

write-protected.

Notes:

1.

Typical values indicate operation at T

A

= 25°C, V

CC

= 5V.

2.

Battery is disconnected from circuit until after V

CC

is applied for the first time. t

DR

is the

accumulated time in absence of power beginning when power is first applied to the device.

Caution:

Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

Power-Down/Power-Up Timing

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10

bq4013/Y

MA: 32-Pin A-Type Module

Dimension

Minimum

Maximum

A

0.365

0.375

A1

0.015

-

B

0.017

0.023

C

0.008

0.013

D

1.670

1.700

E

0.710

0.740

e

0.590

0.630

G

0.090

0.110

L

0.120

0.150

S

0.075

0.110

All dimensions are in inches.

34-Pin LCR LIFETIME LITHIUM Module

Dimension

Minimum

Maximum

A

0.920

0.930

B

0.980

0.995

C

-

0.080

D

0.052

0.060

E

0.045

0.055

F

0.015

0.025

G

0.020

0.030

H

-

0.090

J

0.053

0.073

All dimensions are in inches.

MS: 34-Pin Leaded Chip carrier for LIFETIME LITHIUM Module

1

Centerline of lead within ±0.005 of true position.

2

Leads coplanar within ±0.004 at seating plane.

3

Components and location may vary.

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11

bq4013/Y

MS: LIFETIME LITHIUM Module with LCR attached

LIFETIME LITHIUM Module

Dimension

Minimum

Maximum

A

0.955

0.965

B

0.980

0.995

C

0.240

0.250

D

0.052

0.060

E

0.045

0.055

F

0.015

0.025

All dimensions are in inches.

1

Leads coplanar within ±0.004 at seating plane.

2

Components and location may vary.

MS: LIFETIME LITHIUM Module Housing

LIFETIME LITHIUM Module Housing

Dimension

Minimum

Maximum

A

0.845

0.855

B

0.955

0.965

C

0.210

0.220

D

0.065

0.075

E

0.065

0.075

All dimensions are in inches.

1

Edges coplanar within ±0.025.

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12

Change No.

Page No.

Description

1

2, 3, 4, 6, 8, 9

Added industrial temperature range.

2

1, 4, 6, 9

Added 70ns speed grade for bq4013Y-70.

3

Removed industrial temperature range for bq4013YMA-120N

Notes:

Change 1 = Sept. 1992 B changes from Sept. 1990 A.

Change 2 = Aug. 1993 C changes from Sept. 1991 B.

Change 3 = Sept. 1996 D changes from Aug. 1993 C.

Data Sheet Revision History

Ordering Information

bq4013

xx -

Speed Options:

70 = 70 ns

85 = 85 ns

120 = 120 ns

Package Option:

MA = A-type Module

Supply Tolerance:

no mark = 5% negative supply tolerance

Y = 10% negative supply tolerance

Device:

bq4013 128K x 8 NVSRAM

Temperature:

blank = Commercial (0 to +70°C)

N = Industrial (-40 to +85°C)

1

Notes:

1.

Only 10% supply MA module (“Y-MA”) version  is available in industrial

temperature range; contact factory for speed grade availability.

bq4013/Y

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13

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Copyright © 1999, Texas Instruments Incorporated