background image

1

Data sheet acquired from Harris Semiconductor

SCHS146

Features

• Select One of Eight Data Outputs

- Active Low for CD74HC137 and CD74HCT137

- Active High for CD74HC237 and CD74HCT237

• l/O Port or Memory Selector

• Two Enable Inputs to Simplify Cascading

• Typical Propagation Delay of 13ns at V

CC

 = 5V,

15pF, T

A

 = 25

o

C (CD74HC237)

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs  . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range  . . . -55

o

C to 125

o

C

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

 = 30%, N

IH

 = 30%, of V

CC

at V

CC

 = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

IL

= 0.8V (Max), V

IH

 = 2V (Min)

- CMOS Input Compatibility, I

l

1

µ

A at V

OL

, V

OH

Pinout

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

(PDIP, SOIC)

TOP VIEW

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

A

0

A

1

A

3

LE

OE

1

OE

0

GND

Y

7

V

CC

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

0

March 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

 ©

 Harris Corporation 1998

File Number

1886.1

CD74HC137, CD74HCT137,

CD74HC237, CD74HCT237

High Speed CMOS Logic, 3-to-8 Line Decoder

Demultiplexer with Address Latches

[ /Title

(CD74

HC137

,

CD74

HCT13

7,

CD74

HC237

,

CD74

HCT23

7)

/Sub-

ject

(High

Speed

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2

Description

The Harris CD74HC137, CD74HC237 and CD74HCT137,

CD74HCT237 are high speed silicon gate CMOS decoders

well suited to memory address decoding or data routing

applications. Both circuits feature low power consumption

usually associated with CMOS circuitry, yet have speeds

comparable to low power Schottky TTL logic.

Both circuits have three binary select inputs (A0, A1 and A2)

that can be latched by an active High Latch Enable (LE) sig-

nal to isolate the outputs from select-input changes. A “Low”

LE makes the output transparent to the input and the circuit

functions as a one-of-eight decoder. Two Output Enable

inputs (OE

1

and OE

0

) are provided to simplify cascading

and to facilitate demultiplexing. The demultiplexing function

is accomplished by using the A

0

, A

1

, A

2

inputs to select the

desired output and using one of the other Output Enable

inputs as the data input while holding the other Output

Enable input in its active state. In the CD74HC137 and

CD74HCT137 the selected output is a “Low”; in the

CD74HC237 and CD74HCT237 the selected output is a

“High”.

Ordering Information

PART NUMBER

TEMP. RANGE (

o

C)

PACKAGE

PKG.

NO.

CD74HC137E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT137E

-55 to 125

16 Ld PDIP

E16.3

CD74HC237E

-55 to 125

16 Ld PDIP

E16.3

CD74HC237M

-55 to 125

16 Ld SOIC

M16.15

CD74HCT237E

-55 to 125

16 Ld PDIP

E16.3

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all

electrical specifications. Please contact your local sales office or

Harris customer service for ordering information.

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

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3

Functional Diagram

CD74HC137, CD74HCT137 TRUTH TABLE

INPUTS

OUTPUTS

LE

OE

0

OE

1

A

2

A

1

A

0

Y

0

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

7

X

X

H

X

X

X

H

H

H

H

H

H

H

H

X

L

X

X

X

X

H

H

H

H

H

H

H

H

L

H

L

L

L

L

L

H

H

H

H

H

H

H

L

H

L

L

L

H

H

L

H

H

H

H

H

H

L

H

L

L

H

L

H

H

L

H

H

H

H

H

L

H

L

L

H

H

H

H

H

L

H

H

H

H

L

H

L

H

L

L

H

H

H

H

L

H

H

H

L

H

L

H

L

H

H

H

H

H

H

L

H

H

L

H

L

H

H

L

H

H

H

H

H

H

L

H

L

H

L

H

H

H

H

H

H

H

H

H

H

L

H

H

L

X

X

X

Depends upon the address previously applied while LE was at a logic low.

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

CD74HC237, CD74HCT237 TRUTH TABLE

INPUTS

OUTPUTS

LE

OE

0

OE

1

A

2

A

1

A

0

Y

0

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

7

X

X

H

X

X

X

L

L

L

L

L

L

L

L

X

L

X

X

X

X

L

L

L

L

L

L

L

L

L

H

L

L

L

L

H

L

L

L

L

L

L

L

L

H

L

L

L

H

L

H

L

L

L

L

L

L

L

H

L

L

H

L

L

L

H

L

L

L

L

L

L

H

L

L

H

H

L

L

L

H

L

L

L

L

L

H

L

H

L

L

L

L

L

L

H

L

L

L

L

H

L

H

L

H

L

L

L

L

L

H

L

L

L

H

L

H

H

L

L

L

L

L

L

L

H

L

L

H

L

H

H

H

L

L

L

L

L

L

L

H

H

H

L

X

X

X

Depends upon the address previously applied while LE was at a logic low.

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

15

14

13

12

10

7

9

11

1

Y

0

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

7

3

Y

0

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

7

237

137

6

2

4

5

A

0

A

1

A

2

LE

OE

1

OE

0

3-BIT

LATCH

1 OF 8

DECODER

GND = 8

V

CC

= 16

HC/HCT HC/HCT

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

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4

Functional Block Diagram

A1 LATCH

A2 LATCH

A

0

A

1

A

2

LE

OE

1

OE

0

LE

LE

LE

LE

p

n

p

n

LE

LE

A

0

A

0

A

1

A

0

A

2

A

2

15

14

13

12

11

10

9

7

Y

0

Y

1

Y

2

Y

3

Y

4

Y

5

Y

6

Y

7

1

2

3

4

5

6

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

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5

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage, V

CC

. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For V

I

 < -0.5V or V

I

 > V

CC

 + 0.5V

. . . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Diode Current, I

OK

For V

O

 < -0.5V or V

O

 > V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

20mA

DC Output Source or Sink Current per Output Pin, I

O

For V

O

 > -0.5V or V

O

 < V

CC

 + 0.5V

 . . . . . . . . . . . . . . . . . . . .±

25mA

DC V

CC

 or Ground Current, I

CC

 . . . . . . . . . . . . . . . . . . . . . . . . .±

50mA

Operating Conditions

Temperature Range (T

A

)  . . . . . . . . . . . . . . . . . . . . . -55

o

C to 125

o

C

Supply Voltage Range, V

CC

HC Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, V

I

, V

O

 . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3)

θ

JA

 (

o

C/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

90

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

160

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150

o

C

Maximum Storage Temperature Range  . . . . . . . . . .-65

o

C to 150

o

C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300

o

C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3.

θ

JA

 is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C -55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

High Level Input

Voltage

V

IH

-

-

2

1.5

-

-

1.5

-

1.5

-

V

4.5

3.15

-

-

3.15

 -

3.15

-

V

6

4.2

-

-

4.2

-

4.2

-

V

Low Level Input

Voltage

V

IL

-

-

2

-

-

0.5

-

0.5

-

0.5

V

4.5

-

-

1.35

-

1.35

-

1.35

V

6

-

-

1.8

-

1.8

-

1.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

or V

IL

-0.02

2

1.9

-

-

1.9

-

1.9

-

V

-0.02

4.5

4.4

-

-

4.4

 -

4.4

-

V

-0.02

6

5.9

-

-

5.9

-

5.9

-

V

High Level Output

Voltage

TTL Loads

-

-

-

-

-

-

-

-

-

V

-4

4.5

3.98

-

-

3.84

-

3.7

-

V

-5.2

6

5.48

-

-

5.34

-

5.2

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

or V

IL

0.02

2

-

-

0.1

-

0.1

-

0.1

V

0.02

4.5

-

-

0.1

-

0.1

-

0.1

V

0.02

6

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

-

-

-

-

-

-

-

-

-

V

4

4.5

-

-

0.26

-

0.33

-

0.4

V

5.2

6

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

 or

GND

-

6

-

-

±

0.1

-

±

1

-

±

1

µ

A

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

background image

6

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

6

-

-

8

-

80

-

160

µ

A

HCT TYPES

High Level Input

Voltage

V

IH

-

-

4.5 to

5.5

2

-

-

2

-

2

-

V

Low Level Input

Voltage

V

IL

-

-

4.5 to

5.5

-

-

0.8

-

0.8

-

0.8

V

High Level Output

Voltage

CMOS Loads

V

OH

V

IH

or V

IL

-0.02

4.5

4.4

-

-

4.4

-

4.4

-

V

High Level Output

Voltage

TTL Loads

-4

4.5

3.98

-

-

3.84

-

3.7

-

V

Low Level Output

Voltage

CMOS Loads

V

OL

V

IH

or V

IL

0.02

4.5

-

-

0.1

-

0.1

-

0.1

V

Low Level Output

Voltage

TTL Loads

4

4.5

-

-

0.26

-

0.33

-

0.4

V

Input Leakage

Current

I

I

V

CC

and

GND

0

5.5

-

-

±

0.1

-

±

1

-

±

1

µ

A

Quiescent Device

Current

I

CC

V

CC

 or

GND

0

5.5

-

-

8

-

80

-

160

µ

A

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

I

CC

(Note)

V

CC

-2.1

-

4.5 to

5.5

-

100

360

-

450

-

490

µ

A

NOTE: For dual-supply systems theoretical worst case (V

I

 = 2.4V, V

CC

 = 5.5V) specification is 1.8mA.

DC Electrical Specifications

 (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C -55

o

C TO 125

o

C

UNITS

V

I

(V)

I

O

(mA)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HCT Input Loading Table

INPUT

UNIT LOADS

All

1.5

NOTE: Unit Load is

I

CC

limit specified in DC Electrical Table, e.g.,

360

µ

A max at 25

o

C.

Prerequisite For Switching Specifications

PARAMETER

SYMBOL

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

A

n

to LE Setup Time

t

SU

2

50

-

-

65

-

75

-

ns

4.5

10

-

-

13

-

15

-

ns

6

9

-

-

11

-

13

-

ns

A

n

 to LE Hold Time

t

H

2

30

-

-

40

-

45

-

ns

4.5

6

-

-

8

-

9

-

ns

6

5

-

-

7

-

8

-

ns

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

background image

7

LE Pulse Width

t

W

2

50

-

-

65

-

75

-

ns

4.5

10

-

-

13

-

15

-

ns

6

9

-

-

1

-

13

-

ns

HCT TYPES

An to LE Setup Time

t

SU

4.5

10

-

-

13

-

15

-

ns

An to LE Hold Time

t

H

CD74HCT137

4.5

7

-

-

9

-

11

-

ns

CD74HCT237

t

H

4.5

5

-

-

5

-

5

-

ns

LE Pulse Width

t

W

4.5

10

-

-

13

-

15

-

ns

Switching Specifications

Input t

r

, t

f

 = 6ns

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO

85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

Propagation Delay

CD74HC137, CD74HCT137

t

PLH,

t

PHL

C

L

= 50pF

2

-

-

180

-

225

-

270

ns

An to any Y

4.5

-

-

36

-

45

-

54

ns

6

-

-

31

-

38

-

46

ns

Propagation Delay

CD74HC237, CD74HCT237

t

PLH,

t

PHL

C

L

= 50pF

2

-

-

160

-

200

-

240

ns

An to any Y

4.5

-

-

32

-

40

-

48

ns

6

-

-

27

-

34

-

41

ns

Address to Output

CD74HC137

t

PLH

, t

PHL

C

L

 = 15pF

5

5

15

-

-

-

-

-

ns

CD74HC237

t

PLH

, t

PHL

C

L

 = 15pF

5

-

13

-

-

-

-

-

ns

OE

0

 to any Y or Y

t

PLH,

t

PHL

C

L

= 50pF

2

-

-

145

-

180

-

220

ns

4.5

-

-

29

-

36

-

44

ns

6

-

-

25

-

31

-

38

ns

OE

1

 to any Y or Y

t

TLH

, t

THL

C

L

= 50pF

2

-

-

145

-

180

-

220

ns

4.5

-

-

29

-

36

-

44

ns

6

-

-

25

-

31

-

38

ns

LE to any Y or Y

t

TLH

, t

THL

C

L

 = 50pF

2

-

-

190

-

240

-

285

ns

4.5

-

-

38

-

48

-

57

ns

6

-

-

32

-

41

-

48

ns

Power Dissipation

Capacitance, (Notes 4, 5)

CD74HC137

C

PD

C

L

 = 15pF

5

-

19

-

-

-

-

-

pF

CD74HC237

C

PD

C

L

 = 15pF

5

-

23

-

-

-

-

-

pF

Output Transition Time

t

TLH

, t

THL

C

L

= 50pF

2

-

-

75

-

95

-

110

ns

4.5

-

-

15

-

19

-

22

ns

6

-

-

13

-

16

-

19

ns

Input Capacitance

C

I

-

-

-

-

10

-

10

-

10

pF

Prerequisite For Switching Specifications

 (Continued)

PARAMETER

SYMBOL

V

CC

(V)

25

o

C

-40

o

C TO 85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

background image

8

HCT TYPES

Propagation Delay

An to any Y or Y

Address to Output

t

PLH

, t

PHL

C

L

 = 50pF

4.5

-

-

38

-

48

-

57

ns

t

PLH

, t

PHL

C

L

 = 15pF

5

-

16

-

-

-

-

-

ns

OE

0

to any Y (HC137)

t

PLH

, t

PHL

C

L

 = 50pF

4.5

-

-

35

-

44

-

53

ns

OE

0

to any Y (HC237)

t

PLH

, t

PHL

C

L

 = 50pF

4.5

-

-

33

-

41

-

60

ns

OE

1

to any Y (HC137)

t

TLH

, t

THL

C

L

= 50pF

4.5

-

-

37

-

46

-

56

ns

OE

1

to any Y (HC237)

t

TLH

, t

THL

C

L

= 50pF

4.5

-

-

35

-

44

-

53

ns

LE to any Y (HC137)

t

TLH

, t

THL

CL = 50pF

4.5

-

-

44

-

55

-

66

ns

LE to any Y (HC237)

t

TLH

, t

THL

C

L

= 50pF

4.5

-

-

42

-

53

-

63

ns

Power Dissipation

Capacitance, (Notes 4, 5)

CD74HC137

C

PD

C

L

 = 15pF

5

-

19

-

-

-

-

-

pF

CD74HC237

C

PD

C

L

= 15pF

5

-

23

-

-

-

-

-

pF

Output Transition Time

t

TLH

, t

THL

C

L

= 50pF

4.5

15

19

22

ns

Input Capacitance

C

I

-

-

-

-

10

-

10

-

10

pF

NOTES:

4. C

PD

 is used to determine the dynamic power consumption, per gate.

5. P

D

 = V

CC

2

 f

i

(C

PD

 + C

L

) where: f

i

 = Input Frequency, C

L

 = Output Load Capacitance, V

CC

 = Supply Voltage.

Switching Specifications

Input t

r

, t

f

 = 6ns (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40

o

C TO

85

o

C

-55

o

C TO 125

o

C

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Test Circuits and Waveforms

NOTE: Outputs should be switching from 10% V

CC

 to 90% V

CC

 in

accordance with device truth table. For f

MAX

, input duty cycle = 50%.

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

NOTE: Outputs should be switching from 10% V

CC

 to 90% V

CC

 in

accordance with device truth table. For f

MAX

, input duty cycle = 50%.

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

90%

50%

10%

GND

V

CC

t

r

C

L

t

f

C

L

50%

50%

t

WL

t

WH

10%

t

WL

+ t

WH

=

fC

L

I

CLOCK

2.7V

1.3V

0.3V

GND

3V

t

r

C

L

= 6ns

t

f

C

L

= 6ns

1.3V

1.3V

t

WL

t

WH

0.3V

t

WL

+ t

WH

=

fC

L

I

t

PHL

t

PLH

t

THL

t

TLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

V

CC

t

r

 = 6ns

t

f

 = 6ns

90%

t

PHL

t

PLH

t

THL

t

TLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

3V

t

r

 = 6ns

t

f

 = 6ns

90%

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

background image

9

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

Test Circuits and Waveforms

 (Continued)

t

r

C

L

t

f

C

L

GND

V

CC

GND

V

CC

50%

90%

10%

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

V

CC

50%

50%

90%

10%

50%

90%

t

REM

t

PLH

t

SU(H)

t

TLH

t

THL

t

H(L)

t

PHL

IC

C

L

50pF

t

SU(L)

t

H(H)

t

r

C

L

t

f

C

L

GND

3V

GND

3V

1.3V

2.7V

0.3V

GND

CLOCK

INPUT

DATA

INPUT

OUTPUT

SET, RESET

OR PRESET

3V

1.3V

1.3V

1.3V

90%

10%

1.3V

90%

t

REM

t

PLH

t

SU(H)

t

TLH

t

THL

t

H(L)

t

PHL

IC

C

L

50pF

t

SU(L)

1.3V

t

H(H)

1.3V

background image

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©

 1999, Texas Instruments Incorporated