The UCC561 LVD Regulator set is designed to provide the correct refer-
ences voltages and bias currents for LVD termination resistor networks
(475 , 121
and 475 ). The device also provides a 1.3V output for Diff
Sense signaling. With the proper resistor network, the UCC561 solution will
meet the common mode bias impedance, differential bias, and termination
impedance requirements of SPI-2 (Ultra2) and SPI-3 (Ultra3).
This device incorporates into a single monolith, two sink/source reference
voltage regulators, a 1.3V buffered output and protection features. The pro-
tection features include thermal shut down and active current limiting cir-
cuitry. The UCC561 is offered in 16-pin SOIC(DP) package.
Low Voltage Differential SCSI (LVD) 27 Line Regulator Set
SCSI SPI-2 LVD SCSI 27 Line Low
Voltage Differential Regulator
2.7V to 5.25V Operation
Integrated Regulator Set for LVD
Differential Failsafe Bias
SLUS413 - MAY 1999
1.3V +/– 0.1V
2.7V < 5.25V
SOIC-16 (TOP VIEW)
ABSOLUTE MAXIMUM RATINGS
TERMPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
Package Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2W
Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.
RECOMMENDED OPERATING CONDITIONS
TERMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.25V
Unless otherwise specified these specifications apply for TA = 0°C to 70°C,
TERMPWR = 3.3V.
TERMPWR Supply Current Section
TERMPWR Supply Current
1.75 Volt Regulator
1.3 Volt Regulator
DIFSENS , No Load
0.75 Volt Regulator
1.75 Volt Regulator Source Current
1.75 Volt Regulator Sink Current
1.75 Volt Sink Current Limit
1.75 Volt Source Current Limit
1.3 Volt Regulator Source Current
1.3 Volt Regulator Sink Current
0.75 Volt Regulator Source Current
0.75 Volt Regulator Sink Current
0.75 Source Current Limit
0.75 Sink Current Limit
Note 1: Guaranted by design. Not 100% tested in production.
DIFSENS: SOURCE ONLY
1.3V ± 0.1V
1.75V ± –50mV
0.75V ± –50mV
2.7V TO 5.25V
Figure 1. LVD SCSI discrete resistor stack.
Table I. Resistor stack vs. standard.
112.9mV Diff Bias
100mV to 125mV
1.25V Common Mode
1.2V to 1.30V
Application Note: The resistor stack with the 1.75V and 0.75V
reference will give the correct differential impedance, bias volt-
age, common mode differential impedance and common mode
voltage as show in Table 1.
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
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