background image

SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS262H – JULY 1997 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Meets or Exceeds the Requirements of

ANSI TIA/EIA-644 Standard

D

Operates with a Single 3.3-V Supply

D

Designed for Signaling Rate of Up To

400 Mbps

D

Differential Input Thresholds 

±

100 mV Max

D

Typical Propagation Delay Time of 2.1 ns

D

Power Dissipation 60 mW Typical per

Receiver at 200 MHz

D

Bus-Terminal ESD Protection Exceeds 8 kV

D

Low-Voltage TTL (LVTTL) Logic Output

Levels

D

Pin-Compatible with the AM26LS32,

MC3486, and 

µ

A9637

D

Open-Circuit Fail Safe

     

description

The SN55LVDS32, SN65LVDS32,

SN65LVDS3486, and SN65LVDS9637 are

differential line receivers that implement the

electrical characteristics of low-voltage differential

signaling (LVDS). This signaling technique lowers

the output voltage levels of 5-V differential

standard levels (such as EIA/TIA-422B) to reduce

the power, increase the switching speeds, and

allow operation with a 3.3-V supply rail. Any of the

four differential receivers provides a valid logical

output state with a 

±

100 mV differential  input

voltage within the input common-mode voltage

range. The input common-mode voltage range

allows 1 V of ground potential difference between

two LVDS nodes.

The intended application of these devices and

signaling technique is both point-to-point and

multidrop (one driver and multiple receivers) data

transmission over controlled impedance media of

approximately 100 

. The transmission media

may be printed-circuit board traces, backplanes,

or cables. The ultimate rate and distance of data

transfer is dependent upon the attenuation

characteristics of the media and the noise

coupling to the environment.

The SN65LVDS32, SN65LVDS3486, and

SN65LVDS9637 are characterized for operation

from – 40

°

C to 85

°

C. The SN55LVDS32 is

characterized for operation from – 55

°

C to 125

°

C.

Copyright 

©

 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

19

20

1

3

2

17

18

16

15

14

13

12

11

9

10

5

4

6

7

8

4A

4Y

NC

G

3Y

1Y

G

NC

2Y

2A

1A

1B

NC

V

4B

GND

NC

3B

3A

2B

SN55LVDS32FK

(TOP VIEW)

CC

1

2

3

5

6

7

8

16

15

14

13

12

11

10

9

1B

1A

1Y

G

2Y

2A

2B

GND

V

CC

4B

4A

4Y

G

3Y

3A

3B

SN55LVDS32 . . . J  OR  W

SN65LVDS32D

(Marked as LVDS32 or 65LVDS32)

(TOP VIEW)

1

2

3

5

6

7

8

16

15

14

13

12

11

10

9

1B

1A

1Y

1,2EN

2Y

2A

2B

GND

V

CC

4B

4A

4Y

3,4EN

3Y

3A

3B

 SN65LVDS3486D (Marked as LVDS3486)

(TOP VIEW)

1

2

3

4

8

7

6

5

V

CC

1Y

2Y

GND

1A

1B

2A

2B

 SN65LVDS9637D (Marked as DK637 or LVDS37)

 SN65LVDS9637DGN (Marked as L37)

(TOP VIEW)

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS262H – JULY 1997 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGE

TA

SMALL OUTLINE

(D)

MSOP

(DGN)

CHIP CARRIER

(FK)

CERAMIC DIP

(J)

FLAT PACK

(W)

SN65LVDS32D

– 40

°

C to 85

°

C

SN65LVDS3486D

SN65LVDS9637D

SN65LVDS9637DGN

– 55

°

C to 125

°

C

SN55LVDS32FK

SN55LVDS32J

SN55LVDS32W

G

G

1A

1B

2A

2B

3A

3B

4A

4B

4

12

2

1

6

7

10

9

14

15

3

5

11

13

1Y

2Y

3Y

4Y

’LVDS32 logic diagram 

(positive logic)

1A

1B

2A

2B

3A

3B

4A

4B

4

12

2

1

6

7

10

9

14

15

3

5

11

13

1Y

2Y

3Y

4Y

3,4EN

1,2EN

’LVDS3486D logic diagram 

(positive logic)

1A

1B

2A

2B

8

7

6

5

2

3

1Y

2Y

’LVDS9637D logic diagram 

(positive logic)

background image

logic symbol

2Y

1Y

2B

2A

1B

1A

5

6

7

8

3

2

† This symbol is in accordance with ANSI/IEEE Std

91-1984 and IEC Publication 617-12.

SN65LVDS9637

SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS262H – JULY 1997 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Function Tables

SN55LVDS32, SN65LVDS32

SN65LVDS3486

DIFFERENTIAL INPUT

ENABLES

OUTPUT

DIFFERENTIAL INPUT

ENABLE

OUTPUT

A, B

G

G

Y

A, B

EN

Y

VID 

 100 mV

H

X

X

L

H

H

VID 

 100 mV

H

X

H

H

–100 mV < VID < 100 mV

H

X

X

L

?

?

–100 mV < VID < 100 mV

H

X

?

?

VID 

 –100 mV

H

X

X

L

L

L

VID 

 –100 mV

H

X

L

L

X

L

H

Z

X

L

Z

Open

H

X

X

L

H

H

Open

H

X

H

H

H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate

logic symbol

EN

 1

G

G

1A

1B

2A

2B

3A

3B

4A

4B

3

5

11

13

1Y

2Y

3Y

4Y

4

12

2

1

6

7

10

9

14

15

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

EN

EN

4B

4A

3B

3A

3, 4EN

13

11

4Y

3Y

15

14

9

10

12

2Y

1Y

2B

2A

1B

1A

1, 2EN

7

6

1

2

4

5

3

SN65LVDS3486

SN55LVDS32, SN65LVDS32

Function Table

SN65LVDS9637

DIFFERENTIAL INPUT

OUTPUT

A, B

Y

VID 

 100 mV

H

–100 mV < VID < 100 mV

?

VID 

 –100 mV

L

Open

H

H = high level, L = low level,  ? = indeterminate

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS262H – JULY 1997 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

equivalent input and output schematic diagrams

300 k

300 k

VCC

7 V

7 V

A Input

B Input

7 V

50 

VCC

Input

VCC

7 V

Y Output

EQUIVALENT OF EACH A OR B INPUT

EQUIVALENT OF G, G, 1,2EN OR

3,4EN INPUTS

TYPICAL OF ALL OUTPUTS

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

CC

 (see Note 1)

–0.5 V to 4 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

I

–0.5 V to V

CC

 + 0.5  V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage range, V

(A or B)

–0.5 V to 4  V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous total power dissipation

See Dissipation Rating Table

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

– 65

_

C to 150

_

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

260

_

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.

DISSIPATION RATING TABLE

PACKAGE

TA 

 25

°

C

POWER RATING

DERATING FACTOR‡

ABOVE TA = 25

°

C

TA = 70

°

C

POWER RATING

TA = 85

°

C

POWER RATING

TA = 125

°

C

POWER RATING

D (8)

725 mW

5.8 mW/

°

C

464 mW

377 mW

D (16)

950 mW

7.6 mW/

°

C

608 mW

494 mW

DGN

2.14 W

17.1 mW/

°

C

1.37 W

1.11 W

FK

1375 mW

11.0 mW/

°

C

880 mW

715 mW

275 mW

J

1375 mW

11.0 mW/

°

C

880 mW

715 mW

275 mW

W

1000 mW

8.0 mW/

°

C

640 mW

520 mW

200 mW

‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS262H – JULY 1997 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VCC

3

3.3

3.6

V

High-level input voltage, VIH

G, G, 1,2EN, or 3,4EN

2

V

Low-level input voltage, VIL

G, G, 1,2EN, or 3,4EN

0.8

V

Magnitude of differential input voltage, |VID|

0.1

0.6

V

Common-mode input voltage, VIC (see Figure 1)

| V

ID

|

2

2.4

*

| V

ID

|

2

V

VCC – 0.8

V

Operating free air temperature TA

SN65 prefix

– 40

85

°

C

Operating free-air temperature, TA

SN55 prefix

– 55

125

°

C

Max at VCC = 3 V

Max at VCC >3.15 V

Min

1

0.5

0

0

0.1

0.2

0.3

– Common Mode Input V

oltage – V

1.5

2

COMMON-MODE INPUT VOLTAGE RANGE

vs

DIFFERENTIAL INPUT VOLTAGE

2.5

0.4

0.5

0.6

ÁÁ

ÁÁ

ÁÁ

V

IC

VID – Differential Input Voltage – V

Figure 1. V

IC

 Versus V

ID

 and V

CC

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS262H – JULY 1997 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

SN65LVDSxxxx electrical characteristics over recommended operating conditions (unless

otherwise noted)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

TEST CONDITIONS

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

SN65LVDS32,

SN65LVDS3486,

SN65LVDS9637

ÁÁÁ

Á

Á

Á

ÁÁÁ

UNIT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

MIN

ÁÁÁ

ÁÁÁ

TYP†

ÁÁÁ

ÁÁÁ

MAX

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

VITH+

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Positive-going differential input voltage threshold

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

See Figure 2 and Table 1

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

100

ÁÁÁ

ÁÁÁ

mV

ÁÁÁÁ

ÁÁÁÁ

VITH–

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Negative-going differential input voltage threshold‡

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

See Figure 2 and Table 1

ÁÁÁ

ÁÁÁ

–100

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

mV

ÁÁÁÁ

ÁÁÁÁ

VOH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High-level output voltage

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

IOH = –8 mA

ÁÁÁ

ÁÁÁ

2.4

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

V

ÁÁÁÁ

ÁÁÁÁ

VOL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Low-level output voltage

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

IOL = 8 mA

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

0.4

ÁÁÁ

ÁÁÁ

V

ÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

SN65LVDS32,

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Enabled,

No load

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

10

ÁÁÁ

ÁÁÁ

18

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

ICC

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Supply current

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

,

SN65LVDS3486

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Disabled

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

0.25

ÁÁÁ

ÁÁÁ

0.5

ÁÁÁ

ÁÁÁ

mA

ÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁ

SN65LVDS9637

ÁÁÁÁÁÁÁÁ

No load

ÁÁÁ

ÁÁÁ

5.5

ÁÁÁ

10

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

II

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input current (A or B inputs)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VI = 0

ÁÁÁ

ÁÁÁ

– 2

ÁÁÁ

ÁÁÁ

–10

ÁÁÁ

ÁÁÁ

– 20

ÁÁÁ

ÁÁÁ

µ

A

ÁÁÁÁ

ÁÁÁÁ

II

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input current (A or B inputs)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VI = 2.4 V

ÁÁÁ

ÁÁÁ

– 1.2

ÁÁÁ

ÁÁÁ

– 3

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

µ

A

ÁÁÁÁ

ÁÁÁÁ

II(OFF)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power-off input current (A or B inputs)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VCC = 0,

VI = 3.6 V

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

6

ÁÁÁ

ÁÁÁ

20

ÁÁÁ

ÁÁÁ

µ

A

ÁÁÁÁ

ÁÁÁÁ

IIH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High-level input current (EN, G, or G inputs)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VIH = 2 V

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

10

ÁÁÁ

ÁÁÁ

µ

A

ÁÁÁÁ

ÁÁÁÁ

IIL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Low-level input current (EN, G, or G inputs)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VIL = 0.8 V

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

10

ÁÁÁ

ÁÁÁ

µ

A

ÁÁÁÁ

ÁÁÁÁ

IOZ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High-impedance output current

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VO = 0 or VCC

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

±

10

ÁÁÁ

ÁÁÁ

µ

A

† All typical values are at TA = 25

°

C and with VCC = 3.3 V.

‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for the negative-going

differential input voltage threshold only.

SN65LVDSxxxx switching characteristics over recommended operating conditions (unless

otherwise noted)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

TEST CONDITIONS

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

SN65LVDS32,

SN65LVDS3486,

SN65LVDS9637

ÁÁÁ

Á

Á

Á

ÁÁÁ

UNIT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

MIN

ÁÁÁ

ÁÁÁ

TYP

ÁÁÁ

ÁÁÁ

MAX

ÁÁÁ

ÁÁÁ

ÁÁÁÁ

ÁÁÁÁ

tpLH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, low-to-high-level output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

1.5

ÁÁÁ

ÁÁÁ

2.1

ÁÁÁ

ÁÁÁ

3

ÁÁÁ

ÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁ

tpHL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, high-to-low-level output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

1.5

ÁÁÁ

ÁÁÁ

2.1

ÁÁÁ

ÁÁÁ

3

ÁÁÁ

ÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁ

tsk(p)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Pulse skew (|tPHL – tPLH|)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

0

ÁÁÁ

ÁÁÁ

0.4

ÁÁÁ

ÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁ

tsk(o)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Channel-to-channel output skew†

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

CL = 10 pF,    See Figure 3

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

0.1

ÁÁÁ

ÁÁÁ

0.3

ÁÁÁ

ÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁ

tsk(pp)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Part-to-part skew‡

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

1

ÁÁÁ

ÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁ

tr

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output signal rise time, 20% to 80%

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

0.6

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ns

ÁÁÁÁ

tf

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output signal fall time, 80% to 20%

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

0.7

ÁÁÁ

ÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁ

tpHZ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, high-level-to-high-impedance output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

6.5

ÁÁÁ

ÁÁÁ

12

ÁÁÁ

ÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁ

tpLZ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, low-level-to-high-impedance output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

See Figure 4

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

5.5

ÁÁÁ

ÁÁÁ

12

ÁÁÁ

ÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁ

tpZH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, high-impedance-to-high-level output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

See Figure 4

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

8

ÁÁÁ

ÁÁÁ

12

ÁÁÁ

ÁÁÁ

ns

ÁÁÁÁ

ÁÁÁÁ

tpZL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, high-impedance-to-low-level output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

3

ÁÁÁ

ÁÁÁ

12

ÁÁÁ

ÁÁÁ

ns

† tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same

direction while driving identical specified loads.

‡ tsk(pp) is the magnitude of the different in propagation delay times between any specified terminals of two devices when both devices operate

with the same supply voltages, same temperature, and have identical packages and test circuits.

background image

SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS262H – JULY 1997 – REVISED MARCH 2000

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

SN55LVDS32 Selectrical characteristics over recommended operating conditions (unless

otherwise noted)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TEST CONDITIONS

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

SN55LVDS32

ÁÁÁ

ÁÁÁ

UNIT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TEST CONDITIONS

ÁÁÁ

ÁÁÁ

MIN

ÁÁÁ

ÁÁÁ

TYP†

ÁÁÁ

ÁÁÁ

MAX

ÁÁÁ

ÁÁÁ

UNIT

ÁÁÁ

ÁÁÁ

VITH+

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Positive-going differential input voltage threshold

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

See Figure 2, Table 1, and

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

100

ÁÁÁ

ÁÁÁ

mV

ÁÁÁ

ÁÁÁ

VITH–

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Negative-going differential input voltage threshold‡

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

g

,

,

Note 2

ÁÁÁ

ÁÁÁ

–100

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

mV

ÁÁÁ

ÁÁÁ

VOH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High-level output voltage

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

IOH = –8 mA

ÁÁÁ

ÁÁÁ

2.4

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

V

ÁÁÁ

ÁÁÁ

VOL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Low-level output voltage

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

IOL = 8 mA

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

0.4

ÁÁÁ

ÁÁÁ

V

ÁÁÁ

ICC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Supply current

ÁÁÁÁÁÁÁÁ

Enabled,

No load

ÁÁÁ

ÁÁÁ

10

ÁÁÁ

18

ÁÁÁ

mA

ÁÁÁ

ÁÁÁ

ICC

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Supply current

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

Disabled

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

0.25

ÁÁÁ

ÁÁÁ

0.5

ÁÁÁ

ÁÁÁ

mA

ÁÁÁ

ÁÁÁ

II

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input current (A or B inputs)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VI = 0

ÁÁÁ

ÁÁÁ

– 2

ÁÁÁ

ÁÁÁ

–10

ÁÁÁ

ÁÁÁ

– 20

ÁÁÁ

ÁÁÁ

µ

A

ÁÁÁ

ÁÁÁ

II

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Input current (A or B inputs)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VI = 2.4 V

ÁÁÁ

ÁÁÁ

– 1.2

ÁÁÁ

ÁÁÁ

– 3

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

µ

A

ÁÁÁ

ÁÁÁ

II(OFF)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Power-off input current (A or B inputs)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VCC = 0,

VI = 2.4 V

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

6

ÁÁÁ

ÁÁÁ

20

ÁÁÁ

ÁÁÁ

µ

A

ÁÁÁ

ÁÁÁ

IIH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High-level input current (EN, G, or G inputs)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VIH = 2 V

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

10

ÁÁÁ

ÁÁÁ

µ

A

ÁÁÁ

ÁÁÁ

IIL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Low-level input current (EN, G, or G inputs)

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VIL = 0.8 V

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

10

ÁÁÁ

ÁÁÁ

µ

A

ÁÁÁ

ÁÁÁ

IOZ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

High-impedance output current

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

VO = 0 or VCC

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

±

12

ÁÁÁ

ÁÁÁ

µ

A

† All typical values are at TA = 25

°

C and with VCC = 3.3 V.

‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for the negative-going

differential input voltage threshold only.

NOTE 2: |VITH| = 200 mV for operation at – 55

°

C.

SN55LVDS32 switching characteristics over recommended operating conditions (unless

otherwise noted)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TEST CONDITIONS

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

SN55LVDS32

ÁÁÁ

ÁÁÁ

UNIT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

PARAMETER

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

TEST CONDITIONS

ÁÁÁ

ÁÁÁ

MIN

ÁÁÁ

ÁÁÁ

TYP

ÁÁÁ

ÁÁÁ

MAX

ÁÁÁ

ÁÁÁ

UNIT

ÁÁÁ

tpLH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, low-to-high-level output

ÁÁÁÁÁÁÁÁ

ÁÁÁ

1.3

ÁÁÁ

2.3

ÁÁÁ

6

ÁÁÁ

ns

ÁÁÁ

ÁÁÁ

tpHL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, high-to-low-level output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

CL = 10 pF,    See Figure 3

ÁÁÁ

ÁÁÁ

1.4

ÁÁÁ

ÁÁÁ

2.2

ÁÁÁ

ÁÁÁ

6.1

ÁÁÁ

ÁÁÁ

ns

ÁÁÁ

ÁÁÁ

tsk(o)

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Channel-to-channel output skew†

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

0.1

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ns

ÁÁÁ

ÁÁÁ

tr

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output signal rise time, 20% to 80%

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

CL = 10 pF See Figure 3

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

0.6

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ns

ÁÁÁ

ÁÁÁ

tf

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Output signal fall time, 80% to 20%

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

CL = 10 pF,   See Figure 3

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

0.7

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ns

ÁÁÁ

ÁÁÁ

tpHZ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, high-level-to-high-impedance output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

6.5

ÁÁÁ

ÁÁÁ

12

ÁÁÁ

ÁÁÁ

ns

ÁÁÁ

ÁÁÁ

tpLZ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, low-level-to-high-impedance output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

See Figure 4

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

5.5

ÁÁÁ

ÁÁÁ

12

ÁÁÁ

ÁÁÁ

ns

ÁÁÁ

ÁÁÁ

tpZH

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, high-impedance-to-high-level output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

See Figure 4

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

8

ÁÁÁ

ÁÁÁ

14

ÁÁÁ

ÁÁÁ

ns

ÁÁÁ

ÁÁÁ

tpZL

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Propagation delay time, high-impedance-to-low-level output

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

ÁÁÁ

3

ÁÁÁ

ÁÁÁ

12

ÁÁÁ

ÁÁÁ

ns

† tsk(o) is the maximum delay time difference between drivers on the same device.

background image

SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS262H – JULY 1997 – REVISED MARCH 2000

8

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PARAMETER MEASUREMENT INFORMATION

VID

A

B

Y

VO

VIB

VIA

VIC

(VIA + VIB)/2

Figure 2. Voltage Definitions

Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

APPLIED

VOLTAGES

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

RESULTING DIFFERENTIAL 

INPUT VOLTAGE

ÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁ

RESULTING COMMON-

MODE INPUT VOLTAGE

ÁÁÁÁ

VIA

ÁÁÁÁ

VIB

ÁÁÁÁÁÁÁÁ

VID

ÁÁÁÁÁÁÁÁ

VIC

ÁÁÁÁ

ÁÁÁÁ

1.25 V

ÁÁÁÁ

ÁÁÁÁ

1.15 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

100 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

1.2 V

ÁÁÁÁ

ÁÁÁÁ

1.15 V

ÁÁÁÁ

ÁÁÁÁ

1.25 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

–100 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

1.2 V

ÁÁÁÁ

ÁÁÁÁ

2.4 V

ÁÁÁÁ

ÁÁÁÁ

2.3 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

100 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

2.35 V

ÁÁÁÁ

ÁÁÁÁ

2.3 V

ÁÁÁÁ

ÁÁÁÁ

2.4 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

–100 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

2.35 V

ÁÁÁÁ

ÁÁÁÁ

0.1 V

ÁÁÁÁ

ÁÁÁÁ

0 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

100 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

0.05 V

ÁÁÁÁ

ÁÁÁÁ

0 V

ÁÁÁÁ

ÁÁÁÁ

0.1 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

–100 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

0.05 V

ÁÁÁÁ

ÁÁÁÁ

1.5 V

ÁÁÁÁ

ÁÁÁÁ

0.9 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

600 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

1.2 V

ÁÁÁÁ

0.9 V

ÁÁÁÁ

1.5 V

ÁÁÁÁÁÁÁÁ

–600 mV

ÁÁÁÁÁÁÁÁ

1.2 V

ÁÁÁÁ

ÁÁÁÁ

2.4 V

ÁÁÁÁ

ÁÁÁÁ

1.8 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

600 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

2.1 V

ÁÁÁÁ

ÁÁÁÁ

1.8 V

ÁÁÁÁ

ÁÁÁÁ

2.4 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

–600 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

2.1 V

ÁÁÁÁ

ÁÁÁÁ

0.6 V

ÁÁÁÁ

ÁÁÁÁ

0 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

600 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

0.3 V

ÁÁÁÁ

ÁÁÁÁ

0 V

ÁÁÁÁ

ÁÁÁÁ

0.6 V

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

–600 mV

ÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

0.3 V

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS262H – JULY 1997 – REVISED MARCH 2000

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PARAMETER MEASUREMENT INFORMATION

VID

VO

VIB

VIA

CL 10 pF

tPHL

tPLH

tf

tr

80%

20%

80%

20%

VIA

VIB

VID

VO

1.4 V

1 V

0.4 V

0

–0.4 V

VOH

1.4 V

VOL

NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf 

 1 ns, pulse repetition rate

(PRR) = 50 Mpps, pulse width = 10 

±

 0.2 ns.

B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.

Figure 3. Timing Test Circuit and Wave Forms

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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PARAMETER MEASUREMENT INFORMATION

B

A

G

G

VO

±

500 

VTEST

10 pF

(see Note B)

1.2 V

tPZL

tPLZ

tPZL

tPLZ

tPZH

tPHZ

tPZH

tPHZ

2.5 V

1 V

2 V

1.4 V

0.8 V

2 V

1.4 V

0.8 V

2.5 V

1.4 V

VOL +0.5 V

VOL

0

1.4 V

2 V

1.4 V

0.8 V

2 V

1.4 V

0.8 V

VOH

VOH –0.5 V

1.4 V

0

VTEST

A

G, 1,2EN,

or 3,4EN

G

Y

VTEST

A

G

Y

Inputs

(see Note A)

1,2EN or 3,4EN

G, 1,2EN,

or 3,4EN

NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf 

 1 ns, pulse repetition rate

(PRR) = 0.5 Mpps, pulse width = 500 

±

 10 ns.

B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.

Figure 4. Enable/Disable Time Test Circuit and Wave Forms

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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TYPICAL CHARACTERISTICS

Figure 5

55

45

25

15

50

100

65

75

f – Frequency – MHz

SN55LVDS32, SN65LVDS32

SUPPLY CURRENT

vs

FREQUENCY

85

150

200

35

Four Receivers, Loaded

Per Figure 3, Switching

Simultaneously

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

– Supply Current – mA(rms)

I CC

Figure 6

2.1

1.9

1.7

1.5

–50

0

50

– Low-T

o-High Propagation Delay T

ime – ns

2.3

2.5

LOW-TO-HIGH PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

2.7

100

TA – Free-Air Temperature – 

°

C

t PLH(D)

VCC = 3.3 V

VCC = 3 V

VCC = 3.6 V

Figure 7

2.1

1.9

1.7

1.5

–50

0

50

– High-T

o-Low Propagation Delay T

ime – ns

2.3

2.5

HIGH-TO-LOW PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

2.7

100

t PHL(D)

TA – Free-Air Temperature – 

°

C

VCC = 3.3 V

VCC = 3.6 V

VCC = 3 V

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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APPLICATION INFORMATION

using an LVDS receiver with RS-422 data

Receipt of data from a TIA/EIA-422 line driver may be accomplished using a TIA/EIA-644 line receiver with the

addition of an attenuator circuit. This technique gives the user a very high-speed and low-power 422 receiver.

If the ground noise between the transmitter and receiver is not a concern (less than 

±

1 V), the answer can be

as simple as shown below in Figure 8. The use of a resistor divider circuit in front of the LVDS receiver attenuates

the 422 differential signal to LVDS levels.

The resistors present a total differential load of 100 

 to match the characteristic impedance of the transmission

line and to reduce the signal 10:1. The maximum 422 differential output signal or 6 V is reduced to 600 mV. The

high input impedance of the LVDS receiver prevents input bias offsets and maintains a better than 200-mV

differential input voltage threshold at the inputs to the divider. This circuit is used in front of each LVDS channel

that also receives 422 signals.

R1

45.3 

R2

45.3 

R3

5.11 

R4

5.11 

A

B

Y

’LVDS32

NOTE A: The components used were standard values. 

R1, R2 = NRC12F45R3TR, NIC Components, 45.3 Ohm, 1/8W, 1%, 1206 Package

R3, R4 = NRC12F5R11TR, NIC Components, 5.11 Ohm, 1/8W, 1%, 1206 Package

The resistor values do not need to be 1% tolerance. However, it can be difficult locating a supplier of resistors

having values less than 100 

 in stock and readily available. The user may find other suppliers with

comparable parts having tolerances of 5% or even 10%. These parts are adequate for use in this circuit.

Figure 8. RS-422 Data Input to an LVDS Receiver Under Low Ground Noise Conditions

If ground noise between the RS-422 driver and LVDS receiver is a concern, then the common-mode voltage

must be attenuated. The circuit must then be modified to connect the node between R3 and R4 to the LVDS

receiver ground. This modification to the circuit increases the common-mode voltage from 

±

1 V to greater than

±

4.5 V.

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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APPLICATIONS INFORMATION

The devices are generally used as building blocks for high-speed point-to-point data transmission where ground

differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers

approach ECL speeds without the power and dual supply requirements.

10

1

0.1

T

ransmission Distance – m

100

Signaling Rate – Mbps

TRANSMISSION DISTANCE

vs

SIGNALING RATE

10

100

1000

5% Jitter

(see Note A)

30% Jitter

(see Note A)

24 AWG UTP 96 

 

(PVC Dielectric)

NOTE A: This parameter is the percentage of distortion of the unit interval (UI) with a pseudo-random data pattern.

Figure 9. Typical Transmission Distance Versus Signaling Rate

1B

1A

1Y

G

2Y

2A

2B

GND

VCC

4B

4A

4Y

G

3Y

3A

3B

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

100 

100 

100 

(see Note B)

100 

3.3 V

0.1 

µ

F

(see Note A)

0.001 

µ

F

(see Note A)

VCC

See Note C

NOTES: A. Place a 0.1 

µ

F and a 0.001 

µ

F Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground

plane. The capacitors should be located as close as possible to the device terminals.

B. The termination resistance value should match the nominal characteristic impedance of the transmission media with 

±

10%.

C. Unused enable inputs should be tied to VCC or GND as appropriate.

Figure 10. Typical Application Circuit Schematic

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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APPLICATION INFORMATION

1/4 ’LVDS31

’LVDS32

500 

500 

20 k

20 k

3.3 V

500 

500 

20 k

20 k

3.3 V

7 k

7 k

10 k

3.3 k

Twisted-Pair B Only

Strb/Data_TX

Strb/Data_Enable

Data/Strobe

1 Arb_RX

2 Arb_RX

Port_Status

TpBias on

Twisted-Pair A

 55 

 55 

5 k

VG on

Twisted-Pair B

TP

TP

3.3 V

NOTES: A. Resistors are leadless thick-film (0603) 5% tolerance.

B. Decoupling capacitance is not shown but recommended.

C. VCC is 3 V to 3.6 V.

D. The differential output voltage of the ’LVDS31 can exceed that allowed by IEEE1394.

Figure 11. 100-Mbps IEEE 1394 Transceiver

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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APPLICATION INFORMATION

fail safe

One of the most common problems with differential signaling applications is how the system responds when

no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in

that its output logic state can be indeterminate when the differential input voltage is between –100 mV and

100 mV if it is within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how

it handles the open-input circuit situation, however.

Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be

when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver

will pull each line of the signal pair to near V

CC

 through 300-k

 resistors as shown in Figure 11. The fail-safe

feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the

output to a high level, regardless of the differential input voltage.

Rt

300 k

300 k

VCC

VIT 

 2.3 V

A

B

Y

Figure 12. Open-Circuit Fail Safe of the LVDS Receiver

It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential

input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as

long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that

could defeat the pull-up currents from the receiver and the fail-safe feature.

background image

SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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APPLICATION INFORMATION

1B

1A

1Y

G

2Y

2A

2B

GND

VCC

4B

4A

4Y

G

3Y

3A

3B

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

100 

100 

100 

(see Note B)

100 

VCC

See Note C

3.6 V

0.1 

µ

F

(see Note A)

1N645

(2 places)

0.01 

µ

F

5 V

NOTES: A. Place a 0.1 

µ

F Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The

capacitor should be located as close as possible to the device terminals.

B. The termination resistance value should match the nominal characteristic impedance of the transmission media with 

±

10%.

C. Unused enable inputs should be tied to VCC or GND as appropriate.

Figure 13. Operation with 5-V Supply

related information

IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at 

www.ti.com

for more information.

For more application guidelines, please see the following documents:

D

Low-Voltage Differential Signalling Design Notes (TI literature number SLLA014)

D

Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)

D

Reducing EMI with LVDS (SLLA030)

D

Slew Rate Control of LVDS Circuits (SLLA034)

D

Using an LVDS Receiver with RS-422 Data (SLLA031)

D

Evaluating the LVDS EVM (SLLA033)

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

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MECHANICAL INFORMATION

D (R-PDSO-G**)    

PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047 / D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A  MIN

A  MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0

°

– 8

°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-012

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

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MECHANICAL INFORMATION

DGN (S-PDSO-G8)    

PowerPAD

 PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

Thermal Pad

(See Note D)

0,15 NOM

Gage Plane

4073271/A 01/98

4,98

0,25

5

3,05

4,78

2,95

8

4

3,05

2,95

1

0,38

0,15

0,05

1,07 MAX

Seating Plane

0,10

0,65

M

0,25

0

°

– 6

°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions include mold flash or protrusions.

D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically

and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MO-187

PowerPAD is a trademark of Texas Instruments Incorporated.

background image

SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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MECHANICAL INFORMATION

FK (S-CQCC-N**)     

LEADLESS CERAMIC CHIP CARRIER

4040140 / D 10/96

28 TERMINAL SHOWN

B

0.358

(9,09)

MAX

(11,63)

0.560

(14,22)

0.560

0.458

0.858

(21,8)

1.063

(27,0)

(14,22)

A

NO. OF

MIN

MAX

0.358

0.660

0.761

0.458

0.342

(8,69)

MIN

(11,23)

(16,26)

0.640

0.739

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)

0.938

(28,99)

1.141

(24,43)

(29,59)

(19,32)

(18,78)

**

20

28

52

44

68

84

0.020 (0,51)

TERMINALS

0.080 (2,03)

0.064 (1,63)

(7,80)

0.307

(10,31)

0.406

(12,58)

0.495

(12,58)

0.495

(21,6)

0.850

(26,6)

1.047

0.045 (1,14)

0.045 (1,14)

0.035 (0,89)

0.035 (0,89)

0.010 (0,25)

12

13

14

15

16

18

17

11

10

8

9

7

5

4

3

2

0.020 (0,51)

0.010 (0,25)

6

1

28

26

27

19

21

B SQ

A SQ

22

23

24

25

20

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

background image

SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

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20

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 DALLAS, TEXAS 75265

MECHANICAL INFORMATION

J (R-GDIP-T**)    

CERAMIC DUAL-IN-LINE PACKAGE

1

20

0.290

(7,87)

0.310

0.975

(24,77)

(23,62)

0.930

(7,37)

0.245

(6,22)

(7,62)

0.300

18

16

14

PINS **

0.290

(7,87)

0.310

0.785

(19,94)

(19,18)

0.755

(7,37)

0.310

(7,87)

(7,37)

0.290

0.755

(19,18)

(19,94)

0.785

0.245

(6,22)

(7,62)

0.300

A

0.300

(7,62)

(6,22)

0.245

A  MIN

A  MAX

B  MAX

B  MIN

C  MIN

C  MAX

DIM

0.310

(7,87)

(7,37)

0.290

(23,10)

0.910

0.300

(7,62)

(6,22)

0.245

0

°

–15

°

Seating Plane

0.014 (0,36)

0.008 (0,20)

4040083/D 08/98

C

8

7

0.020 (0,51) MIN

B

0.070 (1,78)

0.100 (2,54)

0.065 (1,65)

0.045 (1,14)

14 PIN SHOWN

14

0.015 (0,38)

0.023 (0,58)

0.100 (2,54)

0.200 (5,08) MAX

0.130 (3,30) MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.

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SN55LVDS32, SN65LVDS32, SN65LVDS3486, SN65LVDS9637

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS262H – JULY 1997 – REVISED MARCH 2000

21

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL INFORMATION

W (R-GDFP-F16)   

CERAMIC DUAL FLATPACK

0.235 (5,97)

0.355 (9,02)

0.355 (9,02)

0.235 (5,97)

9

8

16

1

0.745 (18,92)

0.245 (6,22)

0.004 (0,10)

0.026 (0,66)

0.015 (0,38)

0.015 (0,38)

0.045 (1,14)

0.371 (9,42)

0.006 (0,15)

0.045 (1,14)

Base and Seating Plane

0.025 (0,64)

0.019 (0,48)

0.440 (11,18)

0.285 (7,24)

0.085 (2,16)

1.025 (26,04)

4040180-3 / B 03/95

0.275 (6,99)

0.305 (7,75)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only.

E. Falls within MIL-STD-1835 GDFP1-F16 and JEDEC MO-092AC

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©

 2000, Texas Instruments Incorporated