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SN65LVDT2

HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SLLS374B – JULY 1999 – REVISED JANUARY 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Meets or Exceeds ANSI TIA/EIA-644-1995

Standard

D

Integrated Line Termination Resistor

D

Designed for Signaling Rates up to

400 Mbps

D

Operates From a 2.4-V to 3.6-V Supply

D

Available in the SOT23-5 Package

D

Differential Input Voltage Threshold Less

Than 100 mV

D

Propagation Delay Times, 2.5 ns Typical

D

Power Dissipation at 200 MHz is Typically

60 mW

D

Bus-Pin ESD Protection Exceeds 15 kV

D

Open-Circuit Fail Safe

D

Outputs High Impedance With V

CC 

< 1.5 V

     

description

The SN65LVDT2 is a single low-voltage differen-

tial line receiver in a small-outline transistor

package. The inputs comply with the TIA/EIA-644

standard and provide a maximum differential input

threshold of 100 mV over an input common-mode

voltage range of 0 V to 2.5 V.

When used with a low-voltage differential

signaling (LVDS) driver (such as the SN65LVDS1)

in a point-to-point connection, data or clocking signals can be transmitted over printed-circuit board traces or

cables at very high rates with very low electromagnetic emissions and power consumption.

The high-speed switching of LVDS signals requires the use of a line impedance matching resistor at the

receiving-end of the cable or transmission media. TI offers both the SN65LVDT2, which integrates the

terminating resistor for point-to-point applications, and its companion the SN65LVDS2, which requires an

external resistor. The packaging, low power, low EMI, high ESD tolerance, and wide supply voltage range make

these devices ideal for battery-powered applications.

The SN65LVDT2 is characterized for operation from –40

°

C to 85

°

C.

Copyright 

©

 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

3

2

4

5

(TOP VIEW)

1

VCC

GND

A

R

B

SN65LVDT2

DBV PACKAGE

logic diagram

INPUTS

OUTPUT

R

H

?

L

Function Table

A

B

3

4

R

5

110 

VID = VA – VB

VID  

 100 mV

–100 mV < VID < 100 mV

VID 

 –100 mV

Open

H

H = high level, L = low level , ? = indeterminate

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SN65LVDT2

HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SLLS374B – JULY 1999 – REVISED JANUARY 2000

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

equivalent input and output schematic diagrams

7 V

VCC

7 V

R Output

VCC

B Input

A Input

300 k

300 k

7 V

110 

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

CC

 (see Note 1) 

–0.5 V to 4 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range (A, B, or R) 

–0.5 V to V

CC

+ 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Electrostatic discharge: A, B , and GND (see Note 2) 

CLass 3, A:15 kV, B:600 V

. . . . . . . . . . . . . . . . . . . . . . . 

Continuous total power dissipation 

See dissipation rating table

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range 

–65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 

250

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.

2. Tested in accordance with MIL-STD-883C Method 3015.7.

DISSIPATION RATING TABLE

PACKAGE

TA 

 25

°

C

POWER RATING

DERATING FACTOR

ABOVE TA = 25

°

C†

TA = 85

°

C

POWER RATING

DBV

385 mW

3.1 mW/

°

C

200 mW

† This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-K) and with

no air flow.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VCC

2.4

3.3

3.6

V

Magnitude of differential input voltage, 

VID

0.1

0.6

V

Common–mode input voltage, VIC (see Figure 6)

0

2.4

*

Ť

V

ID

Ť

2

V

g

IC (

g

)

VCC–0.8

Operating free–air temperature, TA

–40

85

°

C

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SN65LVDT2

HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SLLS374B – JULY 1999 – REVISED JANUARY 2000

3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

|VID|– Differential Input Voltage – V

COMMON-MODE INPUT VOLTAGE

vs

DIFFERENTIAL INPUT VOLTAGE

1

0

0.1

0.3

2

1.5

0.5

0.2

0.4

0.6

2.5

0

0.5

VCC = 2.4 V

– Common-Mode Input V

oltage – V

V

IC

MIN

VCC = 2.7 V

VCC = 3.6 V

Figure 1. V

IC

 vs V

ID

 and V

CC

electrical characteristics over recommended operating conditions, V

CC

 = 2.4 V to 3 V (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VITH+

Positive-going differential input voltage threshold

See Figure 2 and Table 1

100

mV

VITH–

Negative-going differential input voltage threshold

See Figure 2 and Table 1

–100

mV

VOH

High-level output voltage

IOH = –8 mA

1.9

2.4

V

VOL

Low-level output voltage

IOL = 8 mA

0.25

0.4

V

ICC

Supply current

No load,

Steady state

4

7

mA

II

Input current (A or B inputs)

VI = 0 V

±

40

µ

A

II

Input current (A or B inputs)

VI = 2.4 V or VCC – 0.8

–2.4

µ

A

IID

Differential input current (IIA – IIB)

VIA = 0.4 V,  VIB = 0 V

VIA = 2.4 V,  VIB = 2 V

3

3.6

4.4

mA

II(OFF)

Power-off input current (A or B inputs)

VCC = 0 V,

VI = 2.4 V,

Other input open

40

µ

A

† All typical values are at 25

°

C and with a 2.7-V supply.

receiver switching characteristics over recommended operating conditions, V

CC

 = 2.4 V to 3 V

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

tPLH

Propagation delay time, low-to-high-level output

1.4

2.6

3.6

ns

tPHL

Propagation delay time, high-to-low-level output

C

10 F

1.4

2.5

3.6

ns

tsk(p)

Pulse skew (|tpHL – tpLH|)‡

CL = 10 pF,

See Figure 3

0.1

0.6

ns

tr

Output signal rise time

See Figure 3

0.8

1.4

ns

tf

Output signal fall time

0.8

1.4

ns

† All typical values are at 25

°

C and with a 2.7-V.

‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.

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SN65LVDT2

HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SLLS374B – JULY 1999 – REVISED JANUARY 2000

4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, V

CC

 = 3 V to 3.6 V (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VITH+

Positive-going differential input voltage threshold

See Figure 2 and Table 1

100

mV

VITH–

Negative-going differential input voltage threshold

See Figure 2 and Table 1

–100

mV

VOH

High-level output voltage

IOH = –8 mA

2.4

3

V

VOL

Low-level output voltage

IOL = 8 mA

0.25

0.4

V

ICC

Supply current

No load,

Steady state

5

8

mA

II

Input current (A or B inputs)

VI = 0 V,

Other input open

±

40

µ

A

II

Input current (A or B inputs)

VI = 2.4 V,

Other input open

–2.4

µ

A

IID

Differential input current (IIA – IIB)

VIA = 0.4 V, VIB = 0 V

VIA = 2.4 V, VIB = 2 V

3

3.6

4.4

mA

II(OFF)

Power-off input current (A or B inputs)

VCC = 0 V,

VI = 2.4 V,

Other input open

40

µ

A

† All typical values are at 25

°

C and with a 3.3-V supply.

receiver switching characteristics over recommended operating conditions, V

CC

 = 3 V to 3.6 V

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

tPLH

Propagation delay time, low-to-high-level output

1.4

2.6

3.1

ns

tPHL

Propagation delay time, high-to-low-level output

C

10 F

1.4

2.5

3.1

ns

tsk(p)

Pulse skew (|tpHL – tpLH|)‡

CL = 10 pF,

See Figure 3

0.1

0.5

ns

tr

Output signal rise time

See Figure 3

0.7

1.1

ns

tf

Output signal fall time

0.7

1.1

ns

† All typical values are at 25

°

C and with a 3.3-V.

‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.

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SN65LVDT2

HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SLLS374B – JULY 1999 – REVISED JANUARY 2000

5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

VIB

VID

VIA

VIC

VO

A

B

R

V

IA

)

V

IB

2

Figure 2. Receiver Voltage Definitions

Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages

APPLIED VOLTAGES

(V)

RESULTING DIFFERENTIAL

INPUT VOLTAGE

(mV)

RESULTING COMMON-

MODE INPUT VOLTAGE

(V)

VIA

VIB

VID

VIC

1.25

1.15

100

1.2

1.15

1.25

– 100

1.2

2.4

2.3

100

2.35

2.3

2.4

– 100

2.35

0.1

0

100

0.05

0

0.1

– 100

0.05

1.5

0.9

600

1.2

0.9

1.5

– 600

1.2

2.4

1.8

600

2.1

1.8

2.4

– 600

2.1

0.6

0

600

0.3

0

0.6

– 600

0.3

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SN65LVDT2

HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SLLS374B – JULY 1999 – REVISED JANUARY 2000

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

VIB

VID

VIA

VO

CL

10 pF

VOH

VOL

1.4 V

VO

VIA

VIB

VID

1.4 V

1 V

0.4 V

0 V

– 0.4 V

tPHL

tPLH

tr

tf

0.4 V

2.4 V

With VCC = 3.3 V

VOH

VOL

1.2 V

VO

tr

tf

20%

80%

With VCC = 2.7 V

NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf 

 1 ns, pulse repetition rate (PRR) = 50 Mpps,

pulse width = 10 

±

 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.

Figure 3. Timing Test Circuit and Waveforms

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SN65LVDT2

HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SLLS374B – JULY 1999 – REVISED JANUARY 2000

7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 4

IOH – High-Level Output Current – mA

  – High-Level Output V

oltage – V

3

2.5

2

1.5

1

0.5

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

– 40

– 50

– 30

–60

V

OH

– 20

0

–70

4

3.5

0

– 10

VCC = 2.7 V

VCC = 3.3 V

Figure 5

3

2.5

2

1.5

1

0.5

30

20

40

10

50

70

0

4

3.5

0

IOL – Low-Level Output Current – mA

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

  – Low-Level Output V

oltage – V

OL

V

60

VCC = 2.7 V

VCC = 3.3 V

Figure 6

TA – Free-Air Temperature – 

°

C

2.6

2.5

2.4

2.7

2.65

2.55

2.45

–20

0

40

–40

20

t PHL

– High-to-Low Level Propagation Delay T

ime – ns

HIGH-TO-LOW LEVEL

PROPAGATION DELAY TIMES

vs

FREE-AIR TEMPERATURE

60

80

2.75

VCC = 3 V

VCC = 2.4 V

2.8

VCC = 3.6 V

VCC = 2.7 V

2.85

2.9

VCC = 3.3 V

Figure 7

TA – Free-Air Temperature – 

°

C

2.6

2.4

2.2

2.8

2.7

2.5

2.3

–20

0

40

–40

20

60

80

100

2.9

VCC = 2.4 V

VCC = 2.7 V

VCC = 3.6 V

3

VCC = 3.3 V

VCC = 3 V

LOW-TO-HIGH LEVEL

PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

t PLH

– Low-to-High Level Propagation Delay T

ime – ns

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SN65LVDT2

HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SLLS374B – JULY 1999 – REVISED JANUARY 2000

8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

APPLICATION INFORMATION

fail safe

One of the most common problems with differential signaling applications is how the system responds when

no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in

that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100

mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it

handles the open-input circuit situation, however.

Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be

when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver

will pull each line of the signal pair to near V

CC

 through 300-k

 resistors as shown in Figure 10. The fail-safe

feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the

output to a high-level regardless of the differential input voltage.

Rt = 100 

 (Typ)

300 k

300 k

VCC

VIT 

 2.3 V

A

B

Y

Figure 8. Open-Circuit Fail Safe of the LVDS Receiver

It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential

input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as

long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that

could defeat the pullup currents from the receiver and the fail-safe feature.

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SN65LVDT2

HIGH-SPEED DIFFERENTIAL LINE RECEIVER

SLLS374B – JULY 1999 – REVISED JANUARY 2000

9

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

MECHANICAL INFORMATION

DBV (R-PDSO-G5)

PLASTIC SMALL-OUTLINE

0,10

M

0,20

0,95

0

°

–8

°

0,25

0,35

0,55

Gage Plane

0,15 NOM

4073253-4/E 05/99

2,60

3,00

0,50

0,30

1,50

1,70

4

5

3

1

2,80

3,00

0,95

1,45

0,05 MIN

Seating Plane

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-178

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 2000, Texas Instruments Incorporated