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SN65LVDS95

LVDS SERDES TRANSMITTER

 

 

SLLS297F – MAY 1998 – REVISED FEBRUARY 2000

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

21:3 Data Channel Compression at up to

1.36 Gigabits per Second Throughput

D

Suited for Point-to-Point Subsystem

Communication With Very Low EMI

D

21 Data Channels Plus Clock in

Low-Voltage TTL and 3 Data Channels Plus

Clock Out Low-Voltage Differential

D

Operates From a Single 3.3-V Supply and

250 mW (Typ)

D

5-V Tolerant Data Inputs

D

’LVDS95 Has Rising Clock Edge Triggered

Inputs

D

Bus Pins Tolerate 6-kV HBM ESD

D

Packaged in Thin Shrink Small-Outline

Package With 20 Mil Terminal Pitch

D

Consumes <1 mW When Disabled

D

Wide Phase-Lock Input Frequency Range

20 MHz to 65 MHz

D

No External Components Required for PLL

D

Inputs Meet or Exceed the Requirements of

ANSI EIA/TIA-644 Standard

D

Industrial Temperature Qualified

T

A

 = – 40

°

C to 85

°

C

D

Replacement for the National DS90CR215

     

description

The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out

shift registers, a 7

×

 clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single

integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted

over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.

When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising

edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to

serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT)

are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN65LVDS95 requires no external components and little or no control. The data bus appears the same

at the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The

only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock

and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal

registers to a low level.

The SN65LVDS95 is characterized for operation over ambient air temperatures of – 40

°

C to 85

°

C.

Copyright 

©

 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

 

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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34

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32

31

30

29

28

27

26

25

D4

V

CC

D5

D6

GND

D7

D8

V

CC

D9

D10

GND

D11

D12

V

CC

D13

D14

GND

D15

D16

D17

V

CC

D18

D19

GND

D3

D2

GND

D1

D0

NC

LVDSGND

Y0M

Y0P

Y1M

Y1P

LVDSV

CC

LVDSGND

Y2M

Y2P

CLKOUTM

CLKOUTP

LVDSGND

PLLGND

PLLV

CC

PLLGND

SHTDN

CLKIN

D20

DGG PACKAGE

(TOP VIEW)

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SN65LVDS95

LVDS SERDES TRANSMITTER

 

 

SLLS297F – MAY 1998 – REVISED FEBRUARY 2000

2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

functional block diagram

Serial/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

D0–6

Serial/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

D7–13

Serial/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

D14–20

CLKINH

7

×

CLK

7

×

 Clock/PLL

CLKIN

Control Logic

SHTDN

CLK

A,B, ...G

A,B, ...G

A,B, ...G

7

7

7

Y0M

Y0P

Y1M

Y1P

Y2M

Y2P

CLKOUTM

CLKOUTP

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SN65LVDS95

LVDS SERDES TRANSMITTER

 

 

SLLS297F – MAY 1998 – REVISED FEBRUARY 2000

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CLKOUT

D0-1

D6

D5

D4

D3

D2

D1

D0

D6+1

D7-1

D13

D12

D11

D10

D9

D8

D7

D13+1

D14-1

D20

D19

D18

D17

D16

D15

D14

D20+1

Current Cycle

Next

Previous Cycle

Y2

Y1

Y0

CLKIN

’LVDS95

Dn

Figure 1. ’LVDS95 Load and Shift Sequences

equivalent input and output schematic diagrams

VCC

7 V

300 k

50 

D or

SHTDN

50 

VCC

YnP or

YnM

7 V

10 k

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SN65LVDS95

LVDS SERDES TRANSMITTER

 

 

SLLS297F – MAY 1998 – REVISED FEBRUARY 2000

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 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

CC

 (see Note 1) 

–0.5 V to 4 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range at any output terminal, V

O

 

–0.5 V to V

CC 

+ 0.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Voltage range at any input terminal, V

I

 

–0.5 V to 5.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Electrostatic discharge (see Note 2): Bus pins (Class 3A) 

6 KV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Bus pins (Class 2B) 

400 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

All pins (Class 3A) 

6 KV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

All pins (Class 2B) 

200 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous total power dissipation 

(see Dissipation Rating Table)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range, T

A

  – 40

°

C to 85

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 

260

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. All voltage values are with respect to the GND terminals.

2. This rating is measured using MIL-STD-883C Method, 3015.7.

DISSIPATION RATING TABLE

PACKAGE

TA 

 25

°

C

POWER RATING

DERATING FACTOR‡

ABOVE TA = 25

°

C

TA = 70

°

C

POWER RATING

TA = 85

°

C

POWER RATING

DGG

1316 mW

13.1 mW/

°

C

724 mW

526 mW

‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VCC

3

3.3

3.6

V

High-level input voltage, VIH

2

V

Low-level input voltage, VIL

0.8

V

Differential load impedance, ZL

90

132

Operating free-air temperature, TA

– 40

85

°

C

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SN65LVDS95

LVDS SERDES TRANSMITTER

 

 

SLLS297F – MAY 1998 – REVISED FEBRUARY 2000

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POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIT

Input voltage threshold

1.4

V

|VOD|

Differential steady-state output voltage magnitude

247

454

|VOD|

Change in the steady-state differential output

voltage magnitude between opposite binary states

RL = 100 

,

See Figure 3

50

mV

VOC(SS)

Steady-state common-mode output voltage

See Figure 3

1.125

1.375

V

VOC(PP)

Peak-to-peak common-mode output voltage

See Figure 3

80

150

mV

IIH

High-level input current

VIH = VCC

20

µ

A

IIL

Low-level input current

VIL = 0 V

±

10

µ

A

IOS

Short circuit output current

VOY = 0 V

±

24

mA

IOS

Short-circuit output current

VOD = 0 V

±

12

mA

IOZ

High-impedance state output current

VO = 0 V to VCC

±

10

µ

A

Disabled, all inputs at GND

280

µ

A

ICC(AVG) Quiescent current (average)

Enabled, RL = 100 

 (4 places),

Worst-case pattern (see Figure 4),

tc = 15.38 ns

85

110

mA

Ci

Input capacitance

3

pF

† All typical values are VCC = 3.3 V, TA = 25

°

C.

timing requirements

MIN

NOM

MAX

UNIT

tc

Input clock period

15.4

tc

50

ns

tw

High-level input clock pulse width duration

0.4tc

0.6tc

ns

tt

Input signal transition time

5

ns

tsu

Data setup time, D0 through D27 before CLKIN

 (’95) (see Figure 2)

3

ns

th

Data hold time, D0 through D27 after CLKIN

 (’95) (see Figure 2)

1.5

ns

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SN65LVDS95

LVDS SERDES TRANSMITTER

 

 

SLLS297F – MAY 1998 – REVISED FEBRUARY 2000

6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

t0

Delay time, CLKOUT serial bit position 0

–0.20

0

0.20

ns

t1

Delay time, CLKOUT

 serial bit position 1

1/7tc–0.20

1/7tc+0.20

ns

t2

Delay time, CLKOUT

 serial bit position 2

2/7tc–0.20

2/7tc+0.20

ns

t3

Delay time, CLKOUT

 serial bit position 3

tc = 15.38 ns (

±

0.2%),

|Input clock jitter| < 50 ps‡

3/7tc–0.20

3/7tc+0.20

ns

t4

Delay time, CLKOUT

 serial bit position 4

|Input clock jitter| < 50 ps‡,

See Figure 5

4/7tc–0.20

4/7tc+0.20

ns

t5

Delay time, CLKOUT

 serial bit position 5

See Figure 5

5/7tc–0.20

5/7tc+0.20

ns

t6

Delay time, CLKOUT

 serial bit position 6

6/7tc–0.20

6/7tc+0.20

ns

tsk(o)

Output skew, tn –n/7 tc

–0.20

0.20

ns

t7

Delay time, CLKIN

 to CLKOUT

tc = 15.38 ns (

±

0.2%),

|Input clock jitter| < 50 ps‡,

See Figure 5

4.2

ns

tC(O) Output clock cycle to cycle jitter§

tc = 15.38 ns + 0.75 sin(2

π

500E3t)

±

0.05 ns,    See Figure 6

±

80

ps

tC(O) Output clock cycle-to-cycle jitter§

tc = 15.38 ns + 0.75 sin(2

π

2E6t)

±

0.05 ns,    See Figure 6

±

300

ps

tw

High-level output clock pulse duration

4/7 tc

ns

tt

Differential output voltage transition time (tr or tf)

See Figure 3

260

700

1500

ps

ten

Enable time, SHTDN

 to phase lock (Yn valid)

See Figure 7

1

ms

tdis

Disable time, SHTDN

 to off-state (CLKOUT low)

See Figure 8

250

ns

† All typical values are VCC = 3.3 V, TA = 25

°

C.

‡ |Input clock jitter| is the magnitude of the change in the input clock period.

§ The output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles.

PARAMETER MEASUREMENT INFORMATION

ÉÉÉÉ

ÉÉÉÉ

ÉÉÉÉÉÉ

ÉÉÉÉÉÉ

Dn

tsu

CLKIN

th

CLKSEL HIGH

NOTE: All input timing is defined at 1.4 V on an input signal with a 10% to 90% rise or fall time of less than 5 ns.

Figure 2. Setup and Hold Time Definition

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SN65LVDS95

LVDS SERDES TRANSMITTER

 

 

SLLS297F – MAY 1998 – REVISED FEBRUARY 2000

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 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

0 V

YP

YM

VID

49.9 

Ω ±

1%

(2 Places)

VOC

CL = 10 pF MAX

(2 Places)

VOD(L)

VOD(H)

VOC(PP)

0 V

VOC(SS)

VOC(SS)

tf

tr

100%

80%

20%

0%

NOTE: The lumped instrumentation capacitance for any single ended voltage

measurement is less than or equal to 10 pF. When making measurements

at YP or YM, the complementary output shall be similarly loaded.

Figure 3. Test Load and Voltage Definitions for LVDS Outputs

CLKIN

EVEN Dn

ODD Dn

T

VIH = 2 V and VIL = 0.8 V

Figure 4. Worst-Case

 Power Test Pattern

‡ The worst-case test pattern produces nearly the maximum switching frequency for all of the LV-TTL outputs.

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SN65LVDS95

LVDS SERDES TRANSMITTER

 

 

SLLS297F – MAY 1998 – REVISED FEBRUARY 2000

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PARAMETER MEASUREMENT INFORMATION

CLKIN

VOD(H)

0 V

t7

t0

t6

t5

t4

t3

t2

t1

VOD(L)

1.4 V

t7

t0–t6

CLKOUT

Yn

CLKIN

CLKOUT

or Xn

Figure 5. Timing Definitions

HP8656B Signal

Generator,

0.1 MHz–990 MHz

RF Output

Output

Modulation Input

CLKOUT

HP8665A Synthesized

Signal Generator,

0.1 MHz–4200 MHz

Device Under

Test

CLKIN

Input

DTS2070C

Digital Time

Scope

Device

Under

Test

VCO

Reference

Modulation

v(t) = A sin(2

π

fmodt)

Σ

+

+

Figure 6. Clock Jitter Test Setup

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SN65LVDS95

LVDS SERDES TRANSMITTER

 

 

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PARAMETER MEASUREMENT INFORMATION

CLKIN

Dn

SHTDN

Yn

ten

Invalid

Valid

Figure 7. Enable Time Measurement Definition

tdis

CLKIN

SHTDN

CLKOUT

Figure 8. Disable Time Measurement Definition

TYPICAL CHARACTERISTICS

ÁÁ

ÁÁ

I CC

60

40

20

0

30

40

50

60

70

80

100

f – Frequency – MHz

– Supply Current – mA

WORST-CASE SUPPLY CURRENT

vs

FREQUENCY

VCC = 3 V

VCC = 3.3 V

VCC = 3.6 V

Figure 9

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SN65LVDS95

LVDS SERDES TRANSMITTER

 

 

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APPLICATION INFORMATION

16-bit bus extension

In a 16-bit bus application (Figure 10), TTL data and clock coming from bus transceivers that interface the

backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus

is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input. The

data is then multiplexed into three different line drivers which perform the TTL to LVDS conversion. The clock

is also converted to LVDS and presented to a separate driver. This synchronized LVDS data and clock at the

receiver, which recovers the LVDS data and clock, performs a conversion back to TTL. Data is then

demultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data, and

then all are presented to the parallel output port of the receiver.

SN74FB2032

8

D0–D7

8

D8–D15

SN65LVDS95

LVDS

Interface

0 To 10 Meters

(Media Dependent)

TTL

Interface

16-Bit

BTL Bus

Interface

CLK

Backplane

Bus

8

D0–D7

8 D8–D15

CLK

Backplane

Bus

TTL

Interface

16-Bit

BTL Bus

Interface

XMIT Clock

RCV Clock

SN74FB2032

SN65LVDS96

SN74FB2032

SN74FB2032

Figure 10. 16-Bit Bus Extension

16-bit bus extension with parity

In the previous application we did not have a checking bit that would provide assurance that the data crosses

the link. If we add a parity bit to the previous example, we would have a diagram similar to the one in Figure 11.

The device following the SN74FB2032 is a low cost parity generator. Each transmit-side transceiver/parity

generator takes the LVTTL data from the corresponding transceiver, performs a parity calculation over the byte,

and then passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter.

Again, the on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16 data + 2 parity) at the

input. The synchronized LVDS data/parity and clock arrive at the receiver.

The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs the

parity calculations. These devices compare their corresponding input bytes with the value received on the parity

bit. The transceiver/parity generator will assert its parity error output if a mismatch is detected.

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LVDS SERDES TRANSMITTER

 

 

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APPLICATION INFORMATION

SN74FB2032

8

D0–D7

8

D8–D15

SN65LVDS95

LVDS

Interface

0 To 10 Meters

(Media Dependent)

TTL

Interface

W/Parity

16-Bit

BTL Bus

Interface

CLK

Backplane

Bus

8

D0–D7

8

D8–D15

CLK

Backplane

Bus

TTL

Interface

16-Bit

BTL Bus

Interface

XMIT Clock

RCV Clock

9 Bit Latchable

Transceiver/ With

Parity Generator

Parity

Parity

TTL

Interface

Parity

Parity

Parity

Error

TTL

Interface

W/Parity

SN74FB2032

9 Bit Latchable

Transceiver/ With

Parity Generator

SN74FB2032

SN74FB2032

9 Bit Latchable

Transceiver/ With

Parity Generator

9 Bit Latchable

Transceiver/ With

Parity Generator

SN65LVDS96

Figure 11. 16-Bit Bus Extension With Parity

low cost virtual backplane transceiver

Figure 12 represents LVDS serdes in an application as a virtual backplane transceiver (VBT). The concept of

a VBT can be achieved by implementing individual LVDS serdes chipsets in both directions of subsystem

serialized links.

Depending on the application, the designer will face varying choices when implementing a VBT. In addition to

the devices shown in Figure 12, functions such as parity and delay lines for control signals could be included.

Using additional circuitry, half-duplex or full-duplex operation can be achieved by configuring the clock and

control lines properly.

The designer may choose to implement an independent clock oscillator at each end of the link and then use

a PLL to synchronize LVDS serdes’s parallel I/O to the backplane bus. Resynchronizing FIFOs may also be

required.

Bus

Transceivers

LVDS Serdes

Transmitter

LVDS Serdes

Receiver

Bus

Transceivers

TTL

Inputs

Up To

21 or 28

Bits

LVDS

Serial Links

4 or 5

Pairs

TTL

Outputs

Up To

21 or 28

Bits

Bus

Transceivers

LVDS Serdes

Transmitter

LVDS Serdes

Receiver

Bus

Transceivers

Backplane

Bus

Backplane

Bus

Figure 12. Virtual Backplane Transceiver

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LVDS SERDES TRANSMITTER

 

 

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MECHANICAL DATA

DGG (R-PDSO-G**)      

PLASTIC SMALL-OUTLINE PACKAGE

4040078 / F 12/97

48 PIN SHOWN

0,25

0,15 NOM

Gage Plane

6,00

6,20

8,30

7,90

0,75

0,50

Seating Plane

25

0,27

0,17

24

A

48

1

1,20 MAX

M

0,08

0,10

0,50

0

°

– 8

°

56

14,10

13,90

48

DIM

A  MAX

A  MIN

PINS **

12,40

12,60

64

17,10

16,90

0,15

0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 

©

 2000, Texas Instruments Incorporated