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1

          PS8115B       02/03/98

Product Description

Pericom Semiconductor’s PI74ALVCH series of logic circuits are

produced in the Company’s advanced 0.5 micron CMOS technology,

achieving industry leading speed.

The PI74ALVCH1622601 uses D-type latches and  D-type flip-

flops with 3-state outputs to allow data flow in transparent, latched,

and clocked modes.

Data flow in each direction is controlled by Output Enable (OEAB

and OEBA), Latched Enable (LEAB and LEBA), and Clock

(CLKAB and CLKBA) inputs. The clock can be controlled by the

Clock Enable (CLKENAB and CLKENBA) inputs. For A-to-B

data flow, the device operates in the transparent mode when LEAB

is HIGH. When LEAB is LOW, the A data is latched if CLKAB is

held at a high or low logic level. If LEAB is low, the A-bus is stored

in the latch/flip-flop on the low-to-high transition of CLKAB.

When OEAB is low, the outputs are active. When OEAB is HIGH,

the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA,

LEBA, CLKBA, and CLKENBA.

To reduce overshoot and undershoot, the inputs/outputs include

26

 series resistors.

To ensure the high-impedance state during power up or power

down, OE should be tied to Vcc through a pull-up resistor; the

minimum value of the resistor is determined by the current-sinking

capability of the driver.

The PI74ALVCH1622601 has “Bus Hold” which retains the data

input’s last state whenever the data input goes to high-impedance

preventing “floating” inputs and eliminating the need for pullup/

down resistors.

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Product Features

PI74ALVCH1622601is designed for low voltage operation

V

CC

 = 2.3V to 3.6V

Hysteresis on all inputs

Typical V

OLP

 (Output Ground Bounce)

< 0.8V at V

CC

 = 3.3V, T

A

 = 25°C

Typical V

OHV

 (Output V

OH

 Undershoot)

 < 2.0V at V

CC

 = 3.3V, T

A

 = 25°C

Inputs/Outputs have equivalent 26

 series resistors,

no external resistors are required.

Bus Hold retains last active bus state during 3-state

eliminates the need for external pullup resistors

Industrial operation at –40°C to +85°C

Packages available:

– 56-pin 240 mil wide plastic TSSOP (A)

– 56-pin 300 mil wide plastic SSOP (V)

PI74ALVCH1622601

18-Bit Universal Bus Transceiver

With 3-State Outputs

Logic Block Diagram

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PI74ALVCH1622601

 18-BIT UNIVERSAL BUS TRANSCEIVER

2

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        PS8115B       02/03/98

Pin Name

Description

CLKEN

Clock Enable Input (Active LOW)

OE

Output Enable Input (Active LOW)

LE

Latch Enable (Active HIGH)

CLK

Clock Input (Active HIGH)

Ax

Data I/O

Bx

Data I/O

GND

Ground

V

CC

Power

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

25

26

27

28

32

31

30

29

Product Pin Description

Truth Table

(1)

Notes:

 1. H = High Signal Level

L = Low Signal Level

Z = High Impedance

 = LOW-to-HIGH Transition

† A-to-B data flow is shown:

B-to-A flow is similar but uses OEBA, LEBA,

CLKBA, and CLKENBA.

‡ Output level before the indicated steady-state input

conditions were established.

§ Output level before the indicated steady-state input

conditions were established, provided that CLKAB is

LOW before LEAB goes LOW.

Product Pin Configuration

56-PIN

A-56

V-56

s

t

u

p

n

I

t

u

p

t

u

O

B

B

A

N

E

K

L

C

B

A

E

O

B

A

E

L

B

A

K

L

C

A

X

H

X

X

X

Z

X

L

H

X

L

L

X

L

H

S

H

H

H

L

L

X

X

B

0

‡

H

L

L

X

X

B

0

‡

L

L

L

­

L

L

L

L

L

­

H

H

L

L

L

L

X

B

0

‡

L

L

L

H

X

B

0

§

OEAB

LEAB

A1

GND

A2

A3

VCC

A4

A5

A6

GND

A7

A8

A9

A10

A11

A12

GND

A13

A14

A15

VCC

A16

A17

GND

A18

OEBA

LEBA

CLKENAB

CLKAB

B1

GND

B2

B3

VCC

B4

B5

B6

GND

B7

B8

B9

B10

B11

B12

GND

B13

B14

B15

VCC

B16

B17

GND

B18

CLKBA

 CLKENBA

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PI74ALVCH1622601

 18-BIT UNIVERSAL BUS TRANSCEIVER

3

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PS8115B       02/03/98

Storage Temperature .................................................. –65°C to +150°C

Ambient Temperature with Power Applied ................. –40°C to +85°C

Input Voltage Range, V

IN

..................................... –0.5V to V

CC 

+0.5V

Output Voltage Range, V

OUT

............................... –0.5V to V

CC 

+0.5V

DC Input Voltage .......................................................... –0.5V to +5.0V

DC Output Current ...................................................................... 100mA

Power Dissipation .......................................................................... 1.0W

Note:

Stresses greater than those listed under MAXIMUM

RATINGS may cause permanent damage to the device.

This is a stress rating only and functional operation of the

device at these or any other conditions above those indi-

cated in the operational sections of this specification is not

implied.  Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

Maximum Ratings

(Above which the useful life may be impaired.  For user guidelines, not tested.)

Note:

1. Unused control inputs must be held HIGH or LOW to prevent them from floating.

Recommended Operating Conditions

(1)

s

r

e

t

e

m

a

r

a

P

n

o

it

p

i

r

c

s

e

D

s

n

o

it

i

d

n

o

C

t

s

e

T

.

n

i

M

.

p

y

T

.

x

a

M

s

ti

n

U

V

C

C

e

g

a

tl

o

V

y

l

p

p

u

S

3

.

2

6

.

3

V

V

H

I

e

g

a

tl

o

V

H

G

I

H

t

u

p

n

I

V

C

C

V

7

.

2

o

t

V

3

.

2

=

7

.

1

V

C

C

V

6

.

3

o

t

V

7

.

2

=

0

.

2

V

L

I

e

g

a

tl

o

V

W

O

L

t

u

p

n

I

V

C

C

V

7

.

2

o

t

V

3

.

2

=

7

.

0

V

C

C

V

6

.

3

o

t

V

7

.

2

=

8

.

0

V

N

I

e

g

a

tl

o

V

t

u

p

n

I

0

V

CC

V

T

U

O

e

g

a

tl

o

V

t

u

p

t

u

O

0

V

CC

I

H

O

t

n

e

rr

u

C

t

u

p

t

u

O

l

e

v

el

-

h

g

i

H

V

C

C

V

3

.

2

=

6

-

A

m

V

C

C

V

7

.

2

=

8

-

V

C

C

V

0

.

3

=

2

1

-

I

L

O

t

n

e

rr

u

C

t

u

p

t

u

O

l

e

v

el

-

w

o

L

V

C

C

V

3

.

2

=

6

V

C

C

V

7

.

2

=

8

V

C

C

V

0

.

3

=

2

1

T

A

e

r

u

t

a

r

e

p

m

e

T

ri

A

-

e

e

r

F

g

n

it

a

r

e

p

O

0

4

-

5

8

C

°

background image

PI74ALVCH1622601

 18-BIT UNIVERSAL BUS TRANSCEIVER

4

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        PS8115B       02/03/98

DC Electrical Characteristics 

(Over the Operating Range, T

A

 = –40°C to +85°C, V

CC

 = 3.3V ± 10%)

s

r

e

t

e

m

a

r

a

P

s

n

o

it

i

d

n

o

C

t

s

e

T

V

C

C )

1

(

.

n

i

M

.

p

y

T

)

2

(

.

x

a

M

s

ti

n

U

V

H

O

I

H

O

0

0

1

-

=

mA

.

x

a

M

o

t

.

n

i

M

V

C

C

2

.

0

-

V

I

H

O

4

-

=

mA

V

H

I

=

V

7

.

1

V

3

.

2

9

.

1

I

H

O

6

-

=

mA

V

H

I

=

V

7

.

1

V

3

.

2

7

.

1

V

H

I

0

.

2

=

V

V

0

.

3

4

.

2

I

H

O

8

-

=

mA

V

H

I

V

0

.

2

=

V

7

.

2

0

.

2

I

H

O

2

1

-

=

mA

V

H

I

V

0

.

2

=

V

0

.

3

0

.

2

V

L

O

I

L

O

0

0

1

=

mA

.

x

a

M

o

t

.

n

i

M

V

C

C

- 2

.

0

2

.

0

I

L

O

=

A

m

4

V

L

I

=

V

7

.

0

V

3

.

2

4

.

0

I

L

O

6

= mA

V

L

I

=

V

7

.

0

V

3

.

2

5

5

.

0

V

L

I

=

V

8

.

0

V

0

.

3

5

5

.

0

I

L

O

=

A

m

8

V

L

I

=

V

8

.

0

V

7

.

2

6

.

0

I

L

O

=

A

m

2

1

V

L

I

=

V

8

.

0

V

0

.

3

8

.

0

I

I

V

I

= V

C

C

D

N

G

r

o

V

6

.

3

5

±

mA

I

I

)

d

l

o

H

(

)

3

(

V

I

=

V

7

.

0

V

3

.

2

5

4

V

I

=

V

7

.

1

5

4

-

V

I

=

V

8

.

0

V

0

.

3

5

7

V

I

=

V

0

.

2

5

7

-

V

I

=

V

6

.

3

o

t

0

V

6

.

3

0

0

5

±

I

Z

O

)

4

(

V

O

= V

C

C

D

N

G

r

o

V

6

.

3

0

1

±

I

C

C

V

I

= V

C

C

D

N

G

r

o

I

O

0

=

V

6

.

3

0

4

DI

C

C

V

t

a

t

u

p

n

i

e

n

O

C

C

V

t

a

st

u

p

n

i

r

e

h

t

o

,

V

6

.

0

-

C

C

D

N

G

r

o

V

6

.

3

o

t

V

3

0

5

7

C

I

st

u

p

n

I

l

o

rt

n

o

C

V

I

= V

C

C

D

N

G

r

o

V

3

.

3

4

F

p

C

O

I

st

r

o

p

B

r

o

A

V

O

= V

C

C

D

N

G

r

o

V

3

.

3

8

Notes:

1. For  Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at V

CC

 = 3.3V, +25°C ambient and maximum loading.

3. Bus Hold maximum dynamic current required to switch the input from one state to another.

4. For I/O ports, the I

OZ

 includes the input leakage current.

Operating Characteristics, T

A

 = 25°C

r

e

t

e

m

a

r

a

P

t

s

e

T

s

n

o

it

i

d

n

o

C

V

2

.

0

±

V

5

.

2

=

c

c

V

V

3

.

0

±

V

3

.

3

=

c

c

V

s

ti

n

U

l

a

c

i

p

y

T

l

a

c

i

p

y

T

C

D

P

n

o

it

a

p

i

s

si

D

r

e

w

o

P

e

c

n

a

ti

c

a

p

a

C

d

el

b

a

n

E

st

u

p

t

u

O

C

L

,

F

p

0

5

=

z

H

M

0

1

=

F

1

4

0

5

F

p

d

el

b

a

si

D

st

u

p

t

u

O

6

6

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PI74ALVCH1622601

 18-BIT UNIVERSAL BUS TRANSCEIVER

5

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PS8115B       02/03/98

Timing Requirements over Operating Range

Switching Characteristics over Operating Range

(1)

Pericom Semiconductor Corporation

2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com

s

r

e

t

e

m

a

r

a

P

m

o

r

F

)

T

U

P

N

I

(

o

T

)

T

U

P

T

U

O

(

V

C

C

V

2

.

0

±

V

5

.

2

=

V

C

C

V

7

.

2

=

V

C

C

V

3

.

0

±

V

3

.

3

U

=

s

ti

n

U

.

n

i

M

)

2

(

.

x

a

M

.

n

i

M

)

2

(

.

x

a

M

.

n

i

M

)

2

(

.

x

a

M

f

X

A

M

0

4

1

0

5

1

0

5

1

z

H

M

t

D

P

A

B

8

.

1

4

.

5

2

.

5

6

.

1

5

.

4

s

n

t

D

P

B

A

8

.

1

4

.

5

2

.

5

6

.

1

5

.

4

t

D

P

B

A

E

L

B

5

.

1

1

.

6

9

.

5

5

.

1

1

.

5

t

D

P

A

B

E

L

A

5

.

1

1

.

6

9

.

5

5

.

1

1

.

5

t

D

P

B

A

K

L

C

B

2

7

.

6

3

.

6

6

.

1

5

.

5

t

D

P

A

B

K

L

C

A

2

.

1

7

.

6

3

.

6

6

.

1

5

.

5

t

N

E

B

A

E

O

B

7

.

1

6

.

6

7

.

6

6

.

1

7

.

5

t

S

I

D

B

A

E

O

B

5

.

2

9

.

5

3

.

5

8

.

1

8

.

4

t

N

E

A

B

E

O

A

7

.

1

6

.

6

7

.

6

6

.

1

7

.

5

t

S

I

D

A

B

E

O

A

5

.

2

9

.

5

3

.

5

8

.

1

8

.

4

Notes:

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

s

r

e

t

e

m

a

r

a

P

n

o

it

p

i

r

c

s

e

D

V

C

C

V

2

.

0

±

V

5

.

2

=

V

C

C

V

7

.

2

=

V

C

C

V

3

.

0

±

V

3

.

3

=

s

ti

n

U

.

n

i

M

.

x

a

M

.

n

i

M

.

x

a

M

.

n

i

M

.

x

a

M

f

K

C

O

L

C

y

c

n

e

u

q

e

rf

k

c

o

l

C

0

0

4

1

0

0

5

1

0

0

5

1

z

H

M

t

W

e

sl

u

P

n

o

it

a

r

u

D

h

g

i

h

E

L

3

.

3

3

.

3

3

.

3

s

n

w

o

l

r

o

h

g

i

h

K

L

C

3

.

3

3

.

3

3

.

3

t

U

S

p

u

t

e

S

e

m

it

h

g

i

h

K

L

C

e

r

o

f

e

b

a

t

a

D

3

.

2

4

.

2

1

.

2

h

g

i

h

K

L

C

,

w

o

l

E

L

e

r

o

f

e

b

a

t

a

D

0

.

2

6

.

1

6

.

1

w

o

l

K

L

C

,

w

o

l

E

L

e

r

o

f

e

b

a

t

a

D

3

.

1

2

.

1

1

.

1

h

g

i

h

K

L

C

e

r

o

f

e

b

N

E

K

L

C

0

.

2

0

.

2

7

.

1

t

H

d

l

o

H

e

m

it

h

g

i

h

K

L

C

r

e

tf

a

a

t

a

D

7

.

0

7

.

0

8

.

0

h

g

i

h

K

L

C

,

w

o

l

E

L

r

e

tf

a

a

t

a

D

3

.

1

6

.

1

4

.

1

w

o

l

K

L

C

,

w

o

l

E

L

r

e

tf

a

a

t

a

D

7

.

1

0

.

2

7

.

1

h

g

i

h

K

L

C

r

e

tf

a

N

E

K

L

C

3

.

0

5

.

0

6

.

0

D /tDv

)

1

(

ll

a

F

r

o

e

si

R

n

o

it

i

s

n

a

r

T

t

u

p

n

I

0

0

1

0

0

1

0

0

1

V

/

s

n

Note:

1. Unused control inputs must be held HIGH or LOW to prevent them from floating.