background image

1

Z86C21 MCU

WITH

 8K ROM

P

RODUCT

 S

PECIFICA

TION

s

8-Bit CMOS MCU with 8 Kbytes of ROM

s

256 Byte Register File

- 236 Bytes of General-Purpose RAM

- 16 Bytes Control/Status Registers

- 4 Bytes for Ports

s

40-Pin DIP, 44-Pin PLCC or 44-Pin QFP Package

s

4.5V to 5.5V Operating Range

s

Low Power Consumption:  220 mW (max) @ 16 MHz

s

Fast instruction pointer:  1.0 

µ

s @ 12 MHz

s

Two Standby Modes:  STOP and HALT

s

32 Input/Output Lines

FEATURES

Z86C21

8K ROM Z8

® 

CMOS

M

ICROCONTROLLER

s

Full-Duplex UART

s

All Digital Inputs are TTL Levels

s

Auto Latches

s

RAM and ROM Protect

s

Two Programmable 8-Bit Counter/Timers each with

6-Bit Programmable Prescaler.

s

Six Vectored, Priority Interrupts from Eight Different

Sources

s

Clock Speeds:  12 and 16 MHz

s

On-Chip Oscillator that Accepts a Crystal, Ceramic

Resonator, LC, or External Clock Drive.

GENERAL DESCRIPTION

The Z86C21 microcontroller  is a member of the Z8 single-

chip microcontroller family with 8 Kbytes of ROM and

236 bytes of RAM. The device is packaged in a 40-pin DIP,

44-pin PLCC, or a 44-pin QFP with a ROMless pin option

available on the 44-pin versions only. With the ROM/

ROMless feature selectively, the Z86C21 offers both exter-

nal memory and preprogrammed ROM, making it well-

suited for high-volume applications or where code flexibil-

ity is required.

Zilog’s CMOS microcontroller offers fast execution, effi-

cient use of memory, sophisticated interrupts, input/output

bit manipulation capabilities, and easy hardware/software

system expansion along with low cost and low power

consumption.

The Z86C21 architecture is characterized by Zilog’s 8-bit

microcontroller core. The device offers a flexible I/O

scheme, an efficient register and address space structure,

multiplexed capabilities between address/data, I/O, and a

number of ancillary features that are useful in many indus-

trial and advanced scientific applications.

For applications demanding powerful I/O capabilities,  the

Z86C21 provides 32 pins dedicated to input and output.

These lines are grouped into four ports. Each port consists

of eight lines, and is configurable under software control to

provide timing, status signals, serial or parallel

I/O with or without handshake, and an address/data bus

for interfacing external memory. There are three basic

address spaces available to support this configuration:

Program Memory, Data Memory, and 236 general-pur-

pose registers.

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\2

Z86C21 MCU

WITH

 8K ROM

GENERAL DESCRIPTION 

(Continued)

To unburden the program from coping with the real-time

tasks, such as counting/timing and serial data communi-

cation, the Z86C21 offers two on-chip counter/timers with

a large number of user selectable modes, and an on-board

UART.

Port 3

UART

Counter/ 

Timers

(2)

Interrupt

Control

Port 2

I/O

(Bit Programmable)

ALU

FLAGS

Register

Pointer

Register File

256 x 8-Bit

Machine Timing and  

Instruction Control

Prg. Memory

8192 x 8-Bit

Program

Counter

Vcc

GND

XTAL

4

4

Port 0

Output

Input

Address or I/O

(Nibble Programmable)

8

Port 1

Address/Data or I/O

(Byte Programmable)

/AS /DS R//W /RESET

Figure 1.  Z86C21 Functional Block Diagram

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.,

B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection

Circuit

Device

Power

V

CC

V

DD

Ground

GND

V

SS

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3

Z86C21 MCU

WITH

 8K ROM

PIN DESCRIPTION

Pin #

Symbol

Function

Direction

1

V

CC

Power Supply

Input

2

XTAL2

Crystal, Oscillator Clock

Output

3

XTAL1

Crystal, Oscillator Clock

Input

4

P37

Port 3, Pin 7

Output

5

P30

Port 3, Pin 0

Input

6

/RESET

Reset

Input

7

R//W

Read/Write

Output

8

/DS

Data Strobe

Output

9

/AS

Address Strobe

Output

10

P35

Port 3, Pin 5

Output

Pin #

Symbol

Function

Direction

11

GND

Ground

Input

12

P32

Port 3, Pin 2

Input

13-20

P00-P07

Port 0, Pins 0,1,2,3,4,5,6,7 In/Output

21-28

P10-P17

Port 1, Pins 0,1,2,3,4,5,6,7 In/Output

29

P34

Port 3, Pin 4

Output

30

P33

Port 3, Pin 3

Input

31-38

P20-P27

Port 2, Pins 0,1,2,3,4,5,6,7 In/Output

39

P31

Port 3, Pin 1

Input

40

P36

Port 3, Pin 6

Output

Table 1.  40-Pin DIP Pin Identification

1

2

9

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

P36

P31

P21

P27

P26

P25

P24

P23

P22

VCC

XTAL2

P37

P30

/RESET

R//W

/DS

31

30

29

28

27

14

10

11

12

13

XTAL1

GND

P32

P00

P01

P20

P33

P34

P17

P16

Z86C21

DIP

15

26

25

24

23

22

21

20

16

17

18

19

/AS

P35

P02

P03

P06

P07

P05

P04

P13

P15

P14

P12

P11

P10

Figure 2.  40-Pin DIP Pin Assignments

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\4

Z86C21 MCU

WITH

 8K ROM

PIN DESCRIPTION 

(Continued)

N/C

P30

P37

XTAL1

XTAL2

VCC

P36

P31

P27

P26

P25

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

N/C

N/C

P24

P23

P22

P21

P20

P33

P34

P17

P16

P15

/RESET

R//W

/DS

/AS

P35

GND

P32

P00

P01

P02

R//RL

7

8

9

10

11

12

13

14

15

16

17

38

37

36

35

34

33

32

31

30

29

39

Z86C21

PLCC

6

5

4

3

2

1

44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

Table 2.  44-Pin PLCC Pin Identification

Pin #

Symbol

Function

Direction

14-16

P00-P02

Port 0, Pins 0,1,2

In/Output

17

R//RL

ROM/ROMless control

Input

18-22

P03-P07

Port 0, Pins 3,4,5,6,7

In/Output

23-27

P10-P14

Port 1, Pins 0,1,2,3,4

In/Output

28

N/C

Not Connected

Input

29-31

P15-P17

Port 1, Pins 5,6,7

In/Output

32

P34

Port 3, Pin 4

Output

33

P33

Port 3, Pin 3

Input

34-38

P20-P24

Port 2, Pins 0,1,2,3,4

In/Output

39

N/C

Not Connected

Input

40-42

P25-P27

Port 2, Pins 5,6,7

In/Output

43

P31

Port 3, Pin 1

Input

44

P36

Port 3, Pin 6

Output

Pin #

Symbol

Function

Direction

1

V

CC

Power Supply

Input

2

XTAL2

Crystal, Oscillator Clock

Output

3

XTAL1

Crystal, Oscillator Clock

Input

4

P37

Port 3, Pin 7

Output

5

P30

Port 3, Pin 0

Input

6

N/C

Not Connected

Input

7

/RESET

Reset

Input

8

R//W

Read/Write

Output

9

/DS

Data Strobe

Output

10

/AS

Address Strobe

Output

11

P35

Port 3, Pin 5

Output

12

GND

Ground

Input

13

P32

Port 3, Pin 2

Input

Figure 3.  44-Pin PLCC Pin Assignments

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5

Z86C21 MCU

WITH

 8K ROM

34

35

36

37

38

39

40

41

42

43

44

21

20

19

18

17

16

15

14

13

12

22

33 32 31 30 29 28 27 26 25 24 23

1

2

3

4

5

6

7

8

9

10

11

GND

P30

P37

XTAL1

XTAL2

VCC

P36

P31

P27

P26

P25

/RESET

R//W

/DS

/AS

P35

GND

P32

P00

P01

P02

R//RL

GND

P24

P23

P22

P21

P20

P33

P34

P17

P16

P15

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

GND

Z86C21

QFP

Table 3.  44-Pin QFP Pin Identification

Pin #

Symbol

Function

Direction

1-5

P03-P07

Port 0, Pins 3,4,5,6,7

In/Output

6

GND

Ground

Input

7-14

P10-P17

Port 1, Pins 0 through 7

In/Output

15

P34

Port 3, Pin 4

Output

16

P33

Port 3, Pin 3

Input

17-21

P20-P24

Port 2, Pins 0,1,2,3,4

In/Output

22

GND

Ground

Input

23-25

P25-P27

Port 2, Pins 5,6,7

In/Output

26

P31

Port 3, Pin 1

Input

27

P36

Port 3, Pin 6

Output

28

GND

Ground

Input

29

V

CC

Power Supply

Input

30

XTAL2

Crystal, Oscillator Clock

Output

Pin #

Symbol

Function

Direction

31

XTAL1

Crystal, Oscillator Clock

Input

32

P37

Port 3, Pin 7

Output

33

P30

Port 3, Pin 0

Input

34

/RESET

Reset

Input

35

R//W

Read/Write

Output

36

/DS

Data Strobe

Output

37

/AS

Address Strobe

Output

38

P35

Port 3, Pin 5

Output

39

GND

Ground

Input

40

P32

Port 3, Pin 2

Input

41-43

P00-P02

Port 0, Pins 0,1,2

In/Output

44

R//RL

ROM/ROMless control

Input

Figure 4.  44-Pin QFP Pin Assignments

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\6

Z86C21 MCU

WITH

 8K ROM

PIN FUNCTIONS

/ROMless

 (input, active Low). This pin, when connected to

GND, disables the internal ROM and forces the device to

function as a Z86C91 ROMless Z8. For more details on the

ROMless version, refer to the Z86C91 product specifica-

tion. (

Note:

  When left unconnected or pulled high to V

CC

,

the part functions as a normal Z86C21 ROM version). This

pin is only available on the 44-pin versions of the Z86C21.

/DS

 (output, active Low). Data Strobe is activated once for

each external memory transfer. For a READ operation,

data must be available prior to the trailing edge of /DS. For

WRITE operations, the falling edge of /DS indicates that

output data is valid.

/AS

 (output, active Low). Address Strobe is pulsed once at

the beginning of each machine cycle. Address output is

through Port 1 for all external programs. Memory address

transfers are valid at the trailing edge of /AS. Under

program control, /AS is placed in the high-impedance

state along with Ports 0 and 1, Data Strobe, and Read/

Write.

XTAL1, XTAL2 

Crystal 1, Crystal 2 (time-based input and

output, respectively). These pins connect a parallel-reso-

nant crystal, ceramic resonator, LC, or any external single-

phase clock to the on-chip oscillator and buffer.

R//W

 (output, write Low). The Read/Write signal is Low

when the MCU is writing to the external program or data

memory.

/RESET

 (input, active Low). To avoid asynchronous and

noisy reset problems, the Z86C21 is equipped with a reset

filter of four external clocks (4TpC). If the external /RESET

signal is less than 4TpC in duration, no reset occurs.

On the fifth clock after the /RESET is detected, an internal

RST signal is latched and held for an internal register count

of 18 external clocks, or for the duration of the external

/RESET, whichever is longer. During the reset cycle, /DS is

held active Low while /AS cycles at a rate of TpC2. When

/RESET is deactivated, program execution begins at loca-

tion 000C (HEX). Power-up reset time must be held Low for

50 ms, or until V

CC

 is stable, whichever is longer.

Port 0

 (P07-P00). Port 0 is an 8-bit, nibble programmable,

bidirectional, TTL compatible port. These eight I/O lines

can be configured under software control as a nibble I/O

port, or as an address port for interfacing external memory.

When used as an I/O port, Port 0 may be placed under

handshake control. In this configuration, Port 3, lines P32

and P35 are used as the handshake control /DAV0 and

RDY0 (Data Available and Ready). Handshake signal

assignment is dictated by the I/O direction of the upper

nibble P07-P04. The lower nibble must have the same

direction as the upper nibble to be under handshake

control.

For external memory references, Port 0 can provide ad-

dress bits A11-A8 (lower nibble) or A15-A8 (lower and

upper nibble) depending on the required address space.

If the address range requires 12 bits or less, the upper

nibble of Port 0 is programmed independently as I/O while

the lower nibble is used for addressing. If one or both

nibbles are needed for I/O operation, they must be config-

ured by writing to the Port 0 Mode register.

In ROMless mode, after a hardware reset, Port 0 lines are

defined as address lines A15-A8, and extended timing is

set to accommodate slow memory access. The initializa-

tion routine includes reconfiguration to eliminate this ex-

tended timing mode (Figure 5).

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7

Z86C21 MCU

WITH

 8K ROM

OEN

Out

In

PAD

Port 0 (I/O)

Handshake Controls

/DAV0 and  RDY0 

(P32 and P35)

Z86C21

MCU

4

TTL Level Shifter

Auto Latch

 500 K

 

4

Figure 5.  Port 0 Configuration

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\8

Z86C21 MCU

WITH

 8K ROM

PIN FUNCTIONS 

(Continued)

Port 1 

(P17-P10). Port 1 is an 8-bit, byte programmable,

bidirectional, TTL compatible port. It has multiplexed Ad-

dress (A7-A0) and Data (D7-D0) ports. For Z86C21, these

eight I/O lines can be programmed as Input or Output lines

or can be configured under software control as an ad-

dress/data port for interfacing external memory. When

used as an I/O port, Port 1 can be placed under handshake

control. In this configuration, Port 3 line P33 and P34 are

used as the handshake controls RDY1 and /DAV1.

Memory locations greater than 8192 are referenced through

Port 1. To interface external memory, Port 1 is programmed

for the multiplexed Address/Data mode. If more than 256

external locations are required, Port 0 must output the

additional lines.

Port 1 can be placed in a high-impedance state along with

Port 0, /AS, /DS and R//W, allowing the MCU to share

common resource in multiprocessor and DMA applica-

tions. Data transfers are controlled by assigning P33 as a

Bus Acknowledge input, and P34 as a Bus request output

(Figure 6).

OEN

Out

In

PAD

Port 1

(AD7-AD0)

Z86C21

MCU

TTL Level Shifter

Auto Latch

 500 K

 

8

Handshake Controls

/DAV1 and  RDY1 

(P33 and P34)

Figure 6.  Port 1 Configuration

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9

Z86C21 MCU

WITH

 8K ROM

Port 2 

(P27-P20). Port 2 is an 8-bit, bit programmable,

bidirectional, CMOS compatible port. Each of these eight

I/O lines can be independently programmed as an input or

output or globally as an open-drain output. Port 2 is always

available for I/O operation. When used as an I/O port,

Port 2 may be placed under handshake control. In this

configuration, Port 3 lines P31 and P36 are used as the

handshake control lines /DAV2 and RDY2. The handshake

signal assignment for Port 3 lines P31 and P36 is dictated

by the direction (input or output) assigned to P27

(Figure 7).

OEN

Out

In

PAD

Port 2 (I/O)

Handshake Controls

/DAV2 and  RDY2 

(P31 and P36)

Z86C21

MCU

TTL Level Shifter

Auto Latch

 500 K

 

Open-Drain

Figure 7.  Port 2 Configuration

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\10

Z86C21 MCU

WITH

 8K ROM

PIN FUNCTIONS 

(Continued)

Port 3

 (P37-P30). Port 3 is an 8-bit, CMOS compatible four-

fixed-input and four-fixed-output port. These eight I/O lines

have four-fixed input (P33-P30) and four fixed output

(P37-P34) ports. Port 3, when used as serial I/O, is pro-

grammed as serial in and serial out, respectively (Figure 8

and Table 4) Port 3 pins have Auto Latches only.

Port 3 is configured under software control to provide the

following control functions: handshake for Ports 0 and 2

(/DAV and RDY); four external interrupt request signals

(IRQ3-IRQ0); timer input and output signals (T

IN

 and T

OUT

),

and Data Memory Select (/DM).

UART Operation.

 Port 3 lines P30 and P37, are be pro-

grammed as serial I/O lines for full-duplex serial asynchro-

Out

In

PAD

Z86C21

MCU

Port 3

(I/O or Control)

Auto Latch

 500 K

 

PAD

Port 3 Output Configuration

Port 3 Input Configuration

Figure 8.  Port 3 Configuration

nous receiver/transmitter operation. The bit rate is con-

trolled by the Counter/Timer0.

The Z86C21 automatically adds a start bit and two stop bits

to transmitted data (Figure 9). Odd parity is also available

as an option. Eight data bits are always transmitted,

regardless of parity selection. If parity is enabled, the

eighth bit is the odd parity bit. An interrupt request (IRQ4)

is generated on all transmitted characters.

Received data must have a start bit, eight data bits and at

least one stop bit. If parity is on, bit 7 of the received data

is replaced by a parity error flag. Received characters

generate the IRQ3 interrupt request.

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11

Z86C21 MCU

WITH

 8K ROM

Table 4.  Port 3 Pin Assignments

Pin

I/O

CTC1

Int.

P0 HS

P1 HS

P2 HS

UART

Ext

P30

IN

IRQ3

Serial In

P31

IN

T

IN

IRQ2

D/R

P32

IN

IRQ0

D/R

P33

IN

IRQ1

D/R

P34

OUT

R/D

DM

P35

OUT

R/D

P36

OUT

T

OUT

R/D

P37

OUT

Serial Out

T0

IRQ4

T1

IRQ5

Notes:

HS = Handshake Signals; D = Data Available; R = Ready

Auto Latch.

 The Auto Latch puts valid CMOS levels on all

CMOS inputs that are not externally driven. This reduces

excessive supply current flow in the input buffer when it is

not been driven by any source.

Low EMI Option.

  The Z86C21 is available in a Low EMI

option.  This option is mask-programmable, to be selected

by the customer at the time when the ROM code is

submitted.  Use of this feature results in:

s

The pre-drivers slew rate reduced to 10 ns typical.

s

Low EMI output drivers have resistance of 200 Ohms

typical.

s

Oscillator divide-by-two circuitry is eliminated.

s

Internal SCLK/TCLK operation is limited to a maximum

of 4 MHz (250 ns cycle time)

P

D6

D5

D4

D3

D2

D1

D0

Start Bit

Seven Data Bits

Received Data (With Parity)

Parity Error Flag

One Stop Bit

ST

SP

P

D6

D5

D4

D3

D2

D1

D0

Start Bit

Seven Data Bits

Transmitted Data (With Parity)

Odd Parity

Two Stop Bits

SP SP

ST

D7

D6

D5

D4

D3

D2

D1

D0

Start Bit

Eight Data Bits

Transmitted Data (No Parity)

Two Stop Bits

SP SP

ST

D7

D6

D5

D4

D3

D2

D1

D0

Start Bit

Eight Data Bits

Received Data (No Parity)

One Stop Bit

SP

ST

Figure 9.  Serial Data Formats

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\12

Z86C21 MCU

WITH

 8K ROM

FUNCTIONAL DESCRIPTION

Address Space

Program Memory.

 The Z86C21 can address up to 56K

bytes of external program memory (Figure 10). The first 12

bytes of program memory are reserved for the interrupt

vectors. These locations contain six 16-bit vectors that

correspond to the six available interrupts. For ROM mode,

byte 13 to byte 8191 consists of on-chip ROM. At ad-

dresses 8192 and greater, the Z86C21 executes external

program memory fetches. In the ROMless mode, the

Z86C21 can address up to 64K bytes of external program

memory. Program execution begins at external location

000C (HEX) after a reset.

Data Memory 

(/DM). The ROM version can address up to

56K bytes of external data memory space beginning at

location 8192. The ROMless version can address up to

64K bytes of external data memory. External data memory

can be included with, or separated from, the external

program memory space. /DM, an optional I/O function that

can be programmed to appear on P34, is used to distin-

guish between data and program memory space (Figure

11). The state of the /DM signal is controlled by the type

instruction being executed. An LDC opcode references

PROGRAM (/DM inactive) memory, and an LDE instruction

references DATA (/DM active Low) memory.

12

11

10

9

8

7

6

5

4

3

2

1

0

External 

ROM and RAM

Location of

First Byte of

Instruction

Executed

After RESET

Interrupt

Vector

(Lower Byte)

Interrupt

Vector

(Upper Byte)

IRQ5

IRQ4

IRQ4

IRQ3

IRQ3

IRQ2

IRQ2

IRQ1

IRQ1

IRQ0

IRQ0

IRQ5

65535

On-Chip ROM

8192

8191

Figure 10.  Program Memory Configuration

65535

8192

8191

0

External

Data

Memory

Not Addressable

Figure 11.  Data Memory Configuration

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13

Z86C21 MCU

WITH

 8K ROM

Register File.

 The Register File consists of four I/O port

registers, 236 general-purpose registers and 16 control

and status registers (Figure 12). The instructions can

access registers directly or indirectly through an 8-bit

address field. The Z86C21 also allows short 4-bit register

addressing using the Register Pointer (Figure 13). In the

4-bit mode, the Register File is divided into 16 working

The upper nibble of the register file address

provided by the register pointer specifies

the active working-register group.

r7

r6

r5

r4

R253

(Register Pointer)

I/O Ports

Specified Working

Register Group

The lower nibble

of the register

file address

provided by the

instruction points

to the specified

register.

r3

r2

r1

r0

Register Group 1

Register Group 0

R15 to R0

Register Group F

R15 to R4

R3 to R0

R15 to R0

FF

F0

0F

00

1F

10

2F

20

Stack Pointer (Bits 7-0)

R255

Stack Pointer (Bits 15-8)

Register Pointer

Program Control Flags

Interrupt Mask Register

Interrupt Request Register

Interrupt Priority Register

Ports 0-1 Mode

Port 3 Mode

Port 2 Mode

T0 Prescaler

Timer/Counter0

T1 Prescaler

Timer/Counter1

Timer Mode

Serial I/O

General-Purpose

Registers

Port 3

Port 2

Port 1

Port 0

R254

R253

R252

R251

R250

R249

R248

R247

R246

R245

R244

R243

R242

R241

R240

R239

R3

R2

R1

R0

SPL

SPH

RP

FLAGS

IMR

IRQ

IPR

P01M

P3M

P2M

PRE0

T0

PRE1

T1

TMR

SIO

P3

P2

P1

P0

R4

LOCATION

IDENTIFIERS

register groups, each occupying 16 continuous locations.

The Register Pointer addresses the starting location of the

active working-register group. For the reset and power-up

conditions of the Register File, see Figure 14.

Note:

 Register Bank E0-EF can only be accessed through

working registers and indirect addressing modes.

Figure 12.  Register File

Figure 13.  Register Pointer

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\14

Z86C21 MCU

WITH

 8K ROM

FUNCTIONAL DESCRIPTION 

(Continued)

D7 D6 D5 D4

0

0

0

0

Working Register

Group Pointer 

%FF

%F0

%7F

%0F

%00

Z8 REGISTER FILE

REGISTER POINTER

% FF

% FE

% FD

% FC

% FB

% FA

% F9

% F8

 % F7

 % F6

% F5

% F4

% F3

% F2

% F1

% F0

SPL

SPH

RP

FLAGS

IMR

IRQ

IPR

P01M

P3M

P2M

PRE0

T0

PRE1

T1

TMR

U

U

U

0

0

U

0

0

1

U

U

U

U

0

U

U

U

U

0

U

1

0

1

U

U

U

U

0

U

U

U

U

0

U

0

0

1

U

U

U

U

0

U

U

U

U

0

U

0

0

1

U

U

U

U

0

U

U

U

U

0

U

1

0

1

U

U

U

U

0

U

U

U

U

0

U

1

0

1

U

U

U

U

0

U

U

U

U

0

U

0

0

1

U

U

0

U

0

U

U

U

U

0

U

1

0

1

0

U

0

U

0

1

1

1

1

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

REGISTER

RESET  CONDITION

REGISTER

Z8  STANDARD CONTROL REGISTERS

RESET  CONDITION

% (0) 03

P3

% (0) 02

P2

% (0) 01

P1

% (0) 00

P0

U = Unknown

D7 D6 D5 D4 D3 D2 D1 D0

S10

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

U

† = For ROMless (Z86C91) reset condition = 10110110

Notes:

1.  General-purpose registers are not reset

     after Stop-Mode Recovery or after a Reset.

2.  General-purpose registers are undefined

     after Power-up.

RAM Protect.

 The upper portion of the RAM’s address

spaces 80FH to EFH (excluding the control registers) can

be protected from reading and writing. The RAM Protect bit

option is mask-programmable and is selected by the

customer when the ROM code is submitted. After the mask

option is selected, the user activates from the internal ROM

code to turn off/on the RAM Protect by loading a bit D6 in

the IMR register to either a 0 or a 1, respectively. A 1 in D6

indicates RAM Protect enabled.

ROM Protect. 

The first 8 Kbytes of program memory is

mask programmable. A ROM protect feature prevents

dumping of the ROM contents by inhibiting execution of

LDC, LDCI, LDE, and LDEI instructions to Program Memory

in all modes.

The ROM Protect option is mask-programmable, to be

selected by the customer at the time when the ROM code

is submitted.

Note:

 With RAM/ROM protect on, the Z86C21 cannot

access the memory space.

Stack. 

The Z86C21 has a 16-bit Stack Pointer (R254-

R255) used for external stack that resides anywhere in the

data memory for the ROMless mode, but only from 8192

to 65535 in the ROM mode. An 8-bit Stack Pointer (R255)

is used for the internal stack that resides within the 236

general-purpose registers (R4-R239). The high byte of the

Stack Pointer (SPH-Bit 8-15) is used as a general-purpose

register when using internal stack only.

Figure 14.  RAM Register File Reset Condition

background image

15

Z86C21 MCU

WITH

 8K ROM

Counter/Timers.

 There are two 8-bit programmable

counter/timers (T0-T1), each driven by its own 6-bit pro-

grammable prescaler. The T1 prescaler is driven by inter-

nal or external clock sources; however, the T0 prescaler is

driven by the internal clock only (Figure 15).

The 6-bit prescalers divides the input frequency of the

clock source by any integer number from 1 to 64. Each

prescaler drives its counter, which decrements the value

(1 to 256) that has been loaded into the counter. When both

the counter and prescaler reach the end of the count, a

timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is gener-

ated.

The counter can be programmed to start, stop, restart to

continue, or restart from the initial value. The counters can

also be programmed to stop upon reaching zero (single

pass mode) or to automatically reload the initial value and

continue counting (modulo-n continuous mode).

The counter, but not the prescalers, can be read at any

time without disturbing their value or count mode. The

clock source for T1 is user-definable and can be either the

internal microprocessor clock divided by four, or an exter-

nal signal input through Port 3. The Timer Mode register

configures the external timer input (P31) as an external

clock, a trigger input that is retriggerable or non-

retriggerable, or as a gate input for the internal clock. Port

3, line P36, also serves as a timer output (T

OUT

) through

which T0, T1 or the internal clock is output. The counter/

timers are cascaded by connecting the T0 output to the

input of T1.

OSC

PRE0

Initial Value

Register

T0

Initial Value

Register

T0

Current Value

Register

6-Bit

Down

Counter

8-bit

Down

Counter

÷

4

6-Bit

Down

Counter

8-Bit

Down

Counter

PRE1

Initial Value

Register

T1

Initial Value

Register

T1

Current Value

Register

÷

2

Clock

Logic

IRQ4

IRQ5

Internal Data Bus

Write

Write

Read

Internal Clock

Gated Clock

Triggered Clock

TIN  P31

Write

Write

Read

Internal Data Bus

External Clock

Internal

Clock

÷

4

Serial I/O 

Clock

Tout

P36

÷

2

Figure 15.  Counter/Timers Block Diagram

background image

\16

Z86C21 MCU

WITH

 8K ROM

FUNCTIONAL DESCRIPTION 

(Continued)

Interrupts.

 The Z86C21 has six different interrupts from

eight different sources. The interrupts are maskable and

prioritized. The eight sources are divided as follow: four

sources are claimed by Port 3, lines P33-P30; one in Serial

Out, one in Serial In, and two in the counter/timers (Figure

16). The Interrupt Mask Register globally or individually

enables or disables the six interrupt requests. When more

than one interrupt is pending, priorities are resolved by a

programmable priority encoder that is controlled by the

Interrupt Priority register. (Refer to Table 4.)

All Z86C21 interrupts are vectored through locations in the

program memory. When an interrupt machine cycle is

activated, an interrupt request is granted. Thus, this dis-

ables all of the subsequent interrupts, save the Program

Counter and Status Flags, and then branches to the

program memory vector location reserved for that inter-

rupt. This memory location and the next byte contain the

16-bit address of the interrupt service routine for that

particular interrupt request.

To accommodate polled interrupt systems, interrupt in-

puts are masked and the Interrupt Request register is

polled to determine which of the interrupt requests need

service. Software initialed interrupts are supported by

setting the appropriate bit in the Interrupt Request Register

(IRQ).

Internal interrupt requests are sampled on the falling edge

of the last cycle of every instruction, and the interrupt

request must be valid 5TpC before the falling edge of the

last clock cycle of the currently executing instruction.

For the ROMless mode, when the device samples a valid

interrupt request, the next 48 (external) clock cycles are

used to prioritize the interrupt, and push the two PC bytes

and the FLAG register on the stack. The following nine

cycles are used to fetch the interrupt vector from external

memory. The first byte of the interrupt service routine is

fetched beginning on the 58th TpC cycle following the

internal sample point, which corresponds to the 63rd TpC

cycle following the external interrupt sample point.

IRQ

IMR

IPR

PRIORITY

LOGIC

6

Global

Interrupt

Enable

Vector Select

Interrupt 

Request

IRQ0 - IRQ5

Figure 16.  Interrupt Block Diagram

background image

17

Z86C21 MCU

WITH

 8K ROM

Clock.

 The Z86C21 on-chip oscillator has a high-gain,

parallel-resonant amplifier for connection to a crystal, LC,

ceramic resonator, or any suitable external clock source

(XTAL1 = Input, XTAL2 = Output). The crystal should be AT

cut, 1 MHz to 16 MHz max, and series resistance (RS) is

less than or equal to 100 Ohms. The crystal should be

connected across XTAL1 and XTAL2 using the recom-

mended capacitors (10 pF < CL < 300 pF) from each pin

11, ground instead of just system ground. This prevents

noise injection into the clock input (Figure 17).

Note:

 Actual capacitor value is specified by the crystal

manufacturer.

Figure 17.  Oscillator Configuration

XTAL1

XTAL2

C1

C2

C1

C2

XTAL1

XTAL2

XTAL1

XTAL2

Ceramic Resonator 

or Crystal

LC Clock

External Clock

L

Pin 11

Pin 11

Pin 11

Pin 11

HALT.

 Turns off the internal CPU clock but not the XTAL

oscillation. The counter/timers and the external interrupts

IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The device

is recovered by interrupts, either externally or internally

generated.  An interrupt request must be executed (en-

abled) to exit HALT mode. After the interrupt service

routine, the program continues from the instruction after

the HALT.

STOP.

 This instruction turns off the internal clock and

external crystal oscillation and reduces the standby cur-

rent to 5 

µ

A (typical) or less. The STOP mode is terminated

by a reset which causes the processor to restart the

application program at address 000C (HEX).

In order to enter STOP (or HALT) mode, it is necessary to

first flush the instruction pipeline to avoid suspending

execution in mid-instruction. To do this, the user must

execute a NOP (opcode=0FFH) immediately before the

appropriate sleep instruction. i.e.,

FF NOP

; clear the pipeline

6F STOP

; enter STOP mode

or

FF NOP

; clear the pipeline

7F HALT

; enter HALT mode

background image

\18

Z86C21 MCU

WITH

 8K ROM

ABSOLUTE MAXIMUM RATINGS

Symbol Description

Min

Max

Units

V

CC

Supply Voltage*

–0.3

+7.0

V

T

STG

Storage Temp

–65

+150

°

C

T

A

Oper Ambient Temp

°

C

Stresses greater than those listed under Absolute Maxi-

mum Ratings may cause permanent damage to the de-

vice. This is a stress rating only; operation of the device at

any condition above those indicated in the operational

sections of these specifications is not implied. Exposure to

absolute maximum rating conditions for an extended pe-

riod may affect device reliability.

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test

conditions as noted. All voltages are referenced to GND.

Positive current flows into the referenced pin (Figure 18).

+5V

From Output 

Under Test

9.1 k

2.1 K

150 pF

Notes:

* Voltages on all pins with respect to GND.

† See Ordering Information

Figure 18.  Test Load Diagram

background image

19

Z86C21 MCU

WITH

 8K ROM

DC CHARACTERISTICS

                    T

A

 = 0

°

C                    T

A

 = –40

°

C

                   to +70

°

C

                  to +105

°

C

Typical

Sym Parameter

Min

Max

Min

Max

@ 25

°

C

Units

Conditions

Max Input Voltage

7

7

V

I

IN

 < 250 

µ

A

V

CH

Clock Input High Voltage

3.8

V

CC 

+0.3

3.8

V

CC

+0.3

V

Driven by External Clock Generator

V

CL

Clock Input Low Voltage

–0.3

0.8

–0.3

0.8

V

Driven by External Clock Generator

V

IH

Input High Voltage

2

V

CC 

+0.3

2.0

V

CC 

+0.3

V

V

IL

Input Low Voltage

–0.3

0.8

–0.3

0.8

V

V

OH

Output High Voltage

2.4

2.4

V

I

OH

 = –2.0 mA

V

OH

Output High Voltage

V

CC 

–100 mV

V

CC 

–100 mV

V

I

OH

 = –100 

µ

A

V

OL

Output Low Voltage

0.4

0.4

V

I

OL

 = +5.0  mA

V

RH

Reset Input High Voltage

3.8

V

CC

+0.3

3.8

V

CC 

 +0.3

V

V

Rl

Reset Input Low Voltage

–0.3

0.8

–0.3

0.8

V

I

IL

Input Leakage

–2

2

–2

2

µ

A

V

IN

 = 0V, V

CC

I

OL

Output Leakage

–2

2

–2

2

µ

A

V

IN

 = 0V, V

CC

I

IR

Reset Input Current

–80

–80

µ

A

V

RL

 = 0V

I

CC

Supply Current

30

30

20

mA

[1] @ 12 MHz

35

35

24

mA

[1] @ 16 MHz

I

CC1

Standby Current

6.5

6.5

4

mA

[1] HALT mode V

IN

 = OV, V

CC

@ 12 MHz

7

7

4.5

mA

[1] HALT mode V

IN 

= OV, V

CC

@ 16 MHz

I

CC2

Standby Current

10

20

1

µ

A

[1] STOP mode V

IN

 = OV, V

CC

I

ALL

Auto Latch Low Current

–10

10

–14

14

5

µ

A

Note:

[1] All inputs driven to either 0V or V

CC

, outputs floating.

background image

\20

Z86C21 MCU

WITH

 8K ROM

AC CHARACTERISTICS

External I/O or Memory Read or Write Timing Diagram

R//W

9

12

18

3

16

13

4

5

8

11

6

17

10

15

7

14

Port 0, /DM

Port 1

/AS

/DS

(Read)

Port 1

/DS

(Write)

A7 - A0

D7 - D0 IN

D7 - D0  OUT

A7 - A0

17

1

2

Figure 19.  External I/O or Memory Read/Write Timing

background image

21

Z86C21 MCU

WITH

 8K ROM

AC CHARACTERISTICS

External I/O or Memory Read or Write Timing Table

 T

A

 = 0

°

C to +70

°

C

T

A

 = –40

°

C to +105

°

C

            12 MHz          16 MHz          12 MHz        16 MHz

No

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Units

Notes

1

TdA(AS)

Address Valid to /AS Rise Delay

35

25

35

25

ns

[2,3]

2

TdAS(A)

/AS Rise to Address Float Delay

45

35

45

35

ns

[2,3]

3

TdAS(DR)

/AS Rise to Read Data Req’d Valid

250

180

250

180

ns

[1,2,3]

4

TwAS

/AS Low Width

55

40

55

40

ns

[2,3]

5

TdAZ(DS)

Address Float to /DS Fall

0

0

0

0

ns

6

TwDSR

/DS (Read) Low Width

185

135

185

135

ns

[1,2,3]

7

TwDSW

/DS (Write) Low Width

110

80

110

80

ns

[1,2,3]

8

TdDSR(DR)

/DS Fall to Read Data Req’d Valid

130

75

130

75

ns

[1,2,3]

9

ThDR(DS)

Read Data to /DS Rise Hold Time

0

0

0

0

ns

[2,3]

10

TdDS(A)

/DS Rise to Address Active Delay

65

50

65

50

ns

[2,3]

11

TdDS(AS)

/DS Rise to /AS Fall Delay

45

35

45

35

ns

[2,3]

12

TdR/W(AS)

R//W Valid to /AS Rise Delay

30

20

33

25

ns

[2,3]

13

TdDS(R/W)

/DS Rise to R//W Not Valid

50

35

50

35

ns

[2,3]

14

TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay

35

25

35

25

ns

[2,3]

15

TdDS(DW)

/DS Rise to Write Data Not Valid Delay

55

35

55

35

ns

[2,3]

16

TdA(DR)

Address Valid to Read Data Req’d Valid

310

230

310

230

ns

[1,2,3]

17

TdAS(DS)

/AS Rise to /DS Fall Delay

65

45

65

45

ns

[2,3]

18

TdDM(AS)

/DM Valid to /AS Rise Delay

50

30

50

30

ns

[2,3]

Clock Dependent Formulas

Number

Symbol

Equation

1

TdA(AS)

0.40TpC + 0.32

2

TdAS(A)

0.59TpC – 3.25

3

TdAS(DR)

2.83TpC + 6.14

4

TwAS

0.66TpC – 1.65

6

TwDSR

2.33TpC – 10.56

7

TwDSW

1.27TpC + 1.67

8

TdDSR(DR)

1.97TpC – 42.5

10

TdDS(A)

0.8TpC

11

TdDS(AS)

0.59TpC – 3.14

12

TdR/W(AS)

0.4TpC

13

TdDS(R/W)

0.8TpC – 15

14

TdDW(DSW)

0.4TpC

15

TdDS(DW)

0.88TpC – 19

16

TdA(DR)

4TpC –20

17

TdAS(DS)

0.91TpC –10.7

18

TdDM(AS)

0.9TpC – 26.3

Notes:

[1] When using extended memory timing add 2 TpC.

[2] Timing numbers given are for minimum TpC.

[3] See clock cycle dependent characteristics table.

Standard Test Load

All timing references use 2.0V for a logic 1 and 0.8V for a logic 0.

background image

\22

Z86C21 MCU

WITH

 8K ROM

AC CHARACTERISTICS

Additional Timing Diagram

Clock

1

3

4

8

2

2

3

TIN

IRQN

6

5

7

7

9

AC CHARACTERISTICS

Additional Timing Table

 T

A

 = 0

°

C to +70

°

C

 

 

T

A

 = –40

°

C to +105

°

C

          12 MHz

16 MHz           12 MHz

         16 MHz

No

Sym

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Units

Notes

1

TpC

Input Clock Period

83

1000

62.5

1000

83

1000

62.5

1000

ns

[1]

2

TrC,TfC

Clock Input Rise & Fall Times

15

10

15

10

ns

[1]

3

TwC

Input Clock Width

35

25

35

25

ns

[1]

4

TwTinL

Timer Input Low Width

75

75

75

75

ns

[2]

5

TwTinH

Timer Input High Width

3TpC

3TpC

3TpC

3TpC

[2]

6

TpTin

Timer Input Period

8TpC

8TpC

8TpC

8TpC

[2]

7

TrTin,TfTin

Timer Input Rise & Fall Times

100

100

100

100

ns

[2]

8A

TwIL

Interrupt Request Input Low Times

70

70

70

50

ns

[2,4]

8B

TwIL

Interrupt Request Input Low Times

3TpC

3TpC

3TpC

3TpC

[2,5]

9

TwIH

Interrupt Request Input High Times

3TpC

3TpC

3TpC

3TpC

[2,3]

Figure 20.  Additional Timing

Notes:

[1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0.

[2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0.

[3] Interrupt references request through Port 3.

[4] Interrupt request through Port 3 (P33-P31).

[5] Interrupt request through Port 30.

background image

23

Z86C21 MCU

WITH

 8K ROM

AC CHARACTERISTICS

Handshake Timing Diagrams

AC CHARACTERISTICS

Handshake Timing Table

 T

A

 = 0

°

C to +70

°

C

T

A

 = –40

°

C to +105

°

C

           12 MHz

16 MHz            12 MHz

16 MHz

Data

No

Sym

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Direction

1

TsDI(DAV)

Data In Setup Time

0

0

0

0

IN

2

ThDI(DAV)

Data In Hold Time

145

145

145

145

IN

3

TwDAV

Data Available Width

110

110

110

110

IN

4

TdDAVI(RDY)

DAV Fall to RDY Fall Delay

115

115

115

115

IN

5

TdDAVId(RDY)

DAV Rise to RDY Rise Delay

115

115

115

115

IN

6

TdRDYO(DAV)

RDY Rise to DAV Fall Delay

0

0

0

0

IN

7

TdD0(DAV)

Data Out to DAV Fall Delay

TpC

TpC

TpC

TpC

OUT

8

TdDAV0(RDY)

DAV Fall to RDY Fall Delay

0

0

0

0

OUT

9

TdRDY0(DAV)

RDY Fall to DAV Rise Delay

115

115

115

115

OUT

10

TwRDY

RDY Width

110

110

110

110

OUT

11

TdRDY0d(DAV)

RDY Rise to DAV Fall Delay

115

115

115

115

OUT

Data Out

/DAV

(Output)

RDY

(Input)

Next Data Out Valid

Delayed    RDY

Delayed DAV

Data Out Valid

7

8

9

10

11

Data In

1

2

3

4

5

6

/DAV

(Input)

RDY

(Output)

Next Data In Valid

Delayed RDY

Delayed DAV

Data In Valid

Figure 21.  Input Handshake Timing

Figure 22.  Output Handshake Timing

background image

\24

Z86C21 MCU

WITH

 8K ROM

D7

D6

D5

D4

D3

D2

D1

D0

Serial Data (D0   = LSB)

R240 SIO 

D7

D6

D5

D4

D3

D2

D1

D0

Count Mode

    0    T1 Single Pass

    1    T1 Modulo N

Clock Source

    1    T1 Internal

    0    T1 External Timing Input

           (T

IN

) Mode 

Prescaler Modulo

   (Range: 1-64 Decimal

   01-00 HEX)

R243 PRE1

Z8 CONTROL REGISTER DIAGRAMS

D7

D6

D5

D4

D3

D2

D1

D0

0    Disable T0 Count

1    Enable  T0 Count

0    No Function

1    Load T0

0    No Function

1    Load T1

0    Disable T1 Count

1    Enable  T1 Count

T

IN

 Modes

00    External Clock Input

01    Gate Input

10    Trigger Input

   (Non-retriggerable)

11    Trigger Input

   (Retriggerable) 

T

OUT

 Modes

00    Not Used

01    T0 Out

10    T1  Out

11    Internal Clock Out

R241 TMR

D7

D6

D5

D4

D3

D2

D1

D0

T1   Initial Value 

       (When Written)

       (Range: 1-256 Decimal

       01-00 HEX)

T1   Current Value

       (When Read)

R242 T1

D7

D6

D5

D4

D3

D2

D1

D0

T0 Initial Value 

   (When Written)

   (Range: 1-256 Decimal

   01-00 HEX)

T0 Current Value

   (When Read)

R244 T0

0    T0 Single Pass

1    T0 Modulo N

D7

D6

D5

D4

D3

D2

D1

D0

Count Mode

Reserved (Must be 0)

Prescaler Modulo

(Range: 1-64 Decimal

01-00 HEX)

R245 PRE0

Figure 23.  Serial I/O Register

(F0

H

: Read/Write)

Figure 26.  Prescaler 1 Register

(F3

H

: Write Only)

Figure 28.  Prescaler 0 Register

(F5

H

: Write Only)

Figure 24.  Timer Mode Register

(F1

H

: Read/Write)

Figure 25.  Counter/Timer 1 Register

(F2

H

: Read/Write)

Figure 27.  Counter/Timer 0 Register

(F4

H

: Read/Write)

background image

25

Z86C21 MCU

WITH

 8K ROM

D7

D6

D5

D4

D3

D2

D1

D0

P2

0

 - P2

7

 I/O Definition

   0    Defines Bit as Output

   1    Defines Bit as Input

R246 P2M

D7

D6

D5

D4

D3

D2

D1

D0

R248 P01M 

P0

0

 - P0

0

 Mode

   00    Output

   01    Input

   1X    A

11

 - A

8

Stack Selection

   0    External

   1    Internal

P1

7

 - P1

0

 Mode

   00    Byte Output

   01    Byte Input

   10    AD

7

 - AD

0

   11    High-Impedance AD

7

 - DA

0

,     

           /AS, /DS, /R//W, A

11 

- A

8

           A

15 

- A

12

, If Selected

P0

- P0

4

 Mode

   00    Output

   01    Input

   1X    A 

15 

- A

12

External Memory Timing

   0    Normal

   1    Extended

   

00    P33 = Input

        P34 = Output

01    P33 = Input 

10    P34 = /DM

11    P33 = /DAV1/RDY1

       P34 = RDY1//DAV1

D7

D6

D5

D4

D3

D2

D1

D0

R247 P3M

0   Port 2 Open Drain

1   Port 2 Push-pull

0   Parity Off

1   Parity On

0   P32 = Input

     P35 = Output

1   P32 = /DAV0/RDY0

     P35 = RDY0//DAV0

0   P31 = Input (TIN)

     P36 = Output (TOUT)

1   P31 = /DAV2/RDY2

     P36 = RDY2//DAV2

0    P30 = Input

      P37 = Output

1    P30 = Serial In 

      P37 = Serial Out

Reserved (Must be 0)

D7 D6

D5

D4

D3

D2

D1

D0

Interrupt Group Priority

Reserved = 000

C > A > B = 001

A > B > C = 010

A > C > B = 011

B > C > A = 100

C > B > A = 101

B > A > C = 110

Reserved = 111

IRQ3, IRQ5 Priority (Group A)

0    IRQ5 > IRQ3

1    IRQ3 > IRQ5

IRQ0, IRQ2 Priority (Group B)

0    IRQ2 > IRQ0

1    IRQ0 > IRQ2

IRQ1, IRQ4 Priority (Group C)

0    IRQ1 > IRQ4

1    IRQ4 > IRQ1

Reserved (Must be 0)

R249 IPR

Figure 29.  Port 2 Mode Register

(F6

H

: Write Only)

Figure 30.  Port 3 Mode Register

(F7

H

: Write Only)

Figure 31.  Port 0 and 1 Mode Register

(F8

H

: Write Only)

Figure 32.  Interrupt Priority Register

(F9

H

: Write Only)

background image

\26

Z86C21 MCU

WITH

 8K ROM

Z8 CONTROL REGISTER DIAGRAMS

 (Continued)

D7

D6

D5

D4

D3

D2

D1

D0

1    Enables RAM Protect

1    Enables IRQ5-IRQ0

      (D

0

 = IRQ0)

1    Enables Interrupts

R251 IMR

D7

D6

D5

D4

D3

D2

D1

D0

R252 FLAGS

User Flag F1 

User Flag F2

Half Carry Flag

Decimal Adjust Flag

Overflow Flag

Sign Flag

Zero Flag

Carry Flag

D7

D6

D5

D4

D3

D2

D1

D0

Stack Pointer Upper

Byte (SP

15 

- SP

8

)

R254 SPH

D7 D6 D5 D4 D3 D2 D1 D0

Stack Pointer Lower

Byte (SP

7

 - SP

0

)

R255 SPL

D7

D6

D5

D4

D3

D2

D1

D0

R253 RP

0   Reserved (Must be 0)

Register Pointer

r4

r5

r6

r7

Figure 33.  Interrupt Request Register

(FA

H

: Read/Write)

Figure 36.  Register Pointer Register

(FD

H

: Read/Write)

Figure 35.  Flag Register

(FC

H

: Read/Write)

Figure 38.  Stack Pointer Register

(FF

H

: Read/Write)

D7

D6

D5

D4

D3

D2

D1

D0

R250 IRQ

Reserved (Must be 0)

IRQ0 = P32   Input (D0 = IRQ0)

IRQ1 = P33   Input

IRQ2 = P31   Input

IRQ3 = P30   Input, Serial Input

IRQ4 = T0     Serial Output

IRQ5 = T1

Figure 37.  Stack Pointer Register

(FE

H

: Read/Write)

Figure 34.  Interrupt Mask Register

(FB

H

: Read/Write)

background image

27

Z86C21 MCU

WITH

 8K ROM

INSTRUCTION SET NOTATION

Addressing Modes. 

The following notation is used to

describe the addressing modes and instruction opera-

tions as shown in the instruction summary.

Symbol

Meaning

IRR

Indirect register pair or indirect working-

register pair address

Irr

Indirect working-register pair only

X

Indexed address

DA

Direct address

RA

Relative address

IM

Immediate

R

Register or working-register address

r

Working-register address only

IR

Indirect-register or indirect

working-register address

Ir

Indirect working-register address only

RR

Register pair or working register pair

address

Symbols. 

The following symbols are used in describing

the instruction set.

Symbol

Meaning

dst

Destination location or contents

src

Source location or contents

cc

Condition code

@

Indirect address prefix

SP

Stack Pointer

PC

Program Counter

FLAGS

Flag register (Control Register 252)

RP

Register Pointer (R253)

IMR

Interrupt mask register (R251)

Flags.

 Control register (R252) contains the following six

flags:

Symbol

Meaning

C

Carry flag

Z

Zero flag

S

Sign flag

V

Overflow flag

D

Decimal-adjust flag

H

Half-carry flag

Affected flags are indicated by:

0

Clear to zero

1

Set to one

*

Set to clear according to operation

-

Unaffected

x

Undefined

background image

\28

Z86C21 MCU

WITH

 8K ROM

CONDITION CODES

Value

Mnemonic

Meaning

Flags Set

1000

Always True

0111

C

Carry

C = 1

1111

NC

No Carry

C = 0

0110

Z

Zero

Z = 1

1110

NZ

Not Zero

Z = 0

1101

PL

Plus

S = 0

0101

MI

Minus

S = 1

0100

OV

Overflow

V = 1

1100

NOV

No Overflow

V = 0

0110

EQ

Equal

Z = 1

1110

NE

Not Equal

Z = 0

1001

GE

Greater Than or Equal

(S XOR V) = 0

0001

LT

Less than

(S XOR V) = 1

1010

GT

Greater Than

[Z OR (S XOR V)] = 0

0010

LE

Less Than or Equal

[Z OR (S XOR V)] = 1

1111

UGE

Unsigned Greater Than or Equal

C = 0

0111

ULT

Unsigned Less Than

C = 1

1011

UGT

Unsigned Greater Than

(C = 0  AND Z = 0) = 1

0011

ULE

Unsigned Less Than or Equal

(C OR Z) = 1

0000

F

Never True (Always False)

background image

29

Z86C21 MCU

WITH

 8K ROM

MODE

dst/src

OPC

dst

OPC

MODE

OPC

src

dst

OPC

VALUE

OPC

OPC

MODE

src/dst

dst/src

OPC

src/dst

dst/src

OPC

VALUE

dst

OPC

RA

dst/CC

7FH

FFH

6FH

OPC

dst

dst/src

1 1 1 0

dst

1 1 1 0

src

1 1 1 0

MODE

src

OPC

dst

MODE

dst

OPC

VALUE

OPC

src

MODE

dst

OPC

MODE

ADDRESS

x

dst/src

OPC

DAU

cc

DAL

DAU

DAL

OPC

src

1 1 1 0

dst

1 1 1 0

dst

1 1 1 0

src

1 1 1 0

dst

1 1 1 0

CLR, CPL, DA, DEC, 

DECW, INC, INCW, 

POP, PUSH, RL, RLC,

RR, RRC, SRA, SWAP

JP, CALL (Indirect)

OR

OR

OR

OR

OR

OR

OR

SRP

ADC, ADD, AND, CP,

OR, SBC, SUB, TCM,

TM, XOR

LD, LDE, LDEI,

LDC, LDCI

LD

LD

DJNZ, JR

STOP/HALT

LD

LD

JP

CALL

ADC, ADD, AND, CP,

LD, OR, SBC, SUB,

TCM, TM, XOR

ADC, ADD, AND, CP,

LD, OR, SBC, SUB,

TCM, TM, XOR

One-Byte Instructions

Two-Byte Instructions

Three-Byte Instructions

CCF, DI, EI, IRET, NOP, 

RCF, RET, SCF

OR

INSTRUCTION FORMATS

INSTRUCTION SUMMARY

Note:

 Assignment of a value is indicated by the symbol

“ 

 ”. For example:

dst 

 dst + src

indicates that the source data is added to the destination

data and the result is stored in the destination location. The

notation “addr (n)” is used to refer to bit (n) of a given

operand location. For example:

dst (7)

refers to bit 7 of the destination operand.

background image

\30

Z86C21 MCU

WITH

 8K ROM

INSTRUCTION SUMMARY 

(Continued)

Address

Instruction

Mode

Opcode

Flags Affected

and Operation

dst src

Byte (Hex) C Z S V D H

ADC

 dst, src

1[  ]

T T T T 0 T

dst

dst + src + C

ADD

 dst, src

0[  ]

T T T T 0 T

dst

dst + src

AND

 dst, src

5[  ]

-

T T 0 -

-

dst

dst AND src

CALL

 

dst

DA

D6

-

-

-

-

-

-

SP

SP – 2

IRR

D4

@SP

PC,

PC

dst

CCF

EF

T -

-

-

-

-

C

NOT C

CLR

 

dst

R

B0

-

-

-

-

-

-

dst

0

IR

B1

COM

 dst

R

60

-

T T 0 -

-

dst

NOT dst

IR

61

CP

 dst, src

A[  ]

T T T T -

-

dst – src

DA

 dst

R

40

T T T X -

-

dst

DA dst

IR

41

DEC

 dst

R

00

-

T T T -

-

dst

dst – 1

IR

01

DECW

 dst

RR

80

-

T T T -

-

dst

dst – 1

IR

81

DI

8F

-

-

-

-

-

-

IMR(7)

0

DJNZ

r,  dst

RA

rA

-

-

-

-

-

-

r

r – 1

r = 0 – F

if r 

 0

PC

PC + dst

Range: +127,

–128

EI

9F

-

-

-

-

-

-

IMR(7)

1

HALT

7F

-

-

-

-

-

-

Address

Instruction

Mode

Opcode

Flags Affected

and Operation

dst src

Byte (Hex) C Z S V D H

INC 

dst

r

rE

-

T T T -

-

dst

dst + 1

r = 0 – F

R

20

IR

21

INCW

 dst

RR

A0

-

T T T -

-

dst

dst + 1

IR

A1

IRET

BF

T T T T T T

FLAGS

@SP;

SP

SP + 1

PC

@SP;

SP

SP + 2;

IMR(7)

1

JP 

cc, dst

DA

cD

-

-

-

-

-

-

if cc is true

c = 0 – F

PC

dst

IRR

30

JR 

cc, dst

RA

cB

-

-

-

-

-

-

if cc is true,

c = 0 – F

PC

PC + dst

Range: +127,

–128

LD 

dst, src

r

Im

rC

-

-

-

-

-

-

dst

src

r

R

r8

R

r

r9

r = 0 – F

r

X

C7

X

r

D7

r

Ir

E3

Ir

r

F3

R

R

E4

R

IR

E5

R

IM

E6

IR

IM

E7

IR

R

F5

LDC 

dst, src

r

Irr

C2

-

-

-

-

-

-

LDCI 

dst, src

Ir

Irr

C3

-

-

-

-

-

-

dst

src

r

r +1;

rr

rr + 1

background image

31

Z86C21 MCU

WITH

 8K ROM

Address

Instruction

Mode

Opcode

Flags Affected

and Operation

dst src

Byte (Hex) C Z S V D H

STOP

6F

-

-

-

-

-

-

SUB 

dst, src

2[  ]

T T T T 1 T

dst

dst

src

SWAP 

dst

R

F0

X T T X -

-

IR

F1

TCM 

dst, src

6[  ]

-

T T 0 -

-

(NOT dst)

AND src

TM 

dst, src

7[  ]

-

T T 0 -

-

dst AND src

XOR 

dst, src

B[  ]

-

T T 0 -

-

dst

dst

XOR src

†  These instructions have an identical set of addressing modes, which

are encoded for brevity. The first opcode nibble is found in the instruction

set table above. The second nibble is expressed symbolically by a ‘[  ]’

in this table, and its value is found in the following table to the left of the

applicable addressing mode pair.

For example, the opcode of an ADC instruction using the addressing

modes r (destination) and Ir (source) is 13.

Address Mode

Lower

dst

src

Opcode Nibble

r

r

[2]

r

Ir

[3]

R

R

[4]

R

IR

[5]

R

IM

[6]

IR

IM

[7]

INSTRUCTION SUMMARY 

(Continued)

Address

Instruction

Mode

Opcode

Flags Affected

and Operation

dst src

Byte (Hex) C Z S V D H

NOP

FF

-

-

-

-

-

-

OR 

dst, src

4[  ]

-

T T 0 -

-

dst

dst OR src

POP 

dst

R

50

-

-

-

-

-

-

dst

@SP;

IR

51

SP

SP + 1

PUSH 

src

R

70

-

-

-

-

-

-

SP

SP – 1;

IR

71

@SP

src

RCF

CF

0

-

-

-

-

-

C

0

RET

AF

-

-

-

-

-

-

PC

@SP;

SP

SP + 2

RL 

dst

R

90

T T T T -

-

IR

91

RLC 

dst

R

10

T T T T -

-

IR

11

RR 

dst

R

E0

T T T T -

-

IR

E1

RRC 

dst

R

C0

T T T T -

-

IR

C1

SBC 

dst, src

3[  ]

T T T T 1 T

dst

dst

src

C

SCF

DF

1

-

-

-

-

-

C

1

SRA 

dst

R

D0

T T T 0 -

-

IR

D1

SRP 

src

Im

31

-

-

-

-

-

-

RP

src

C

7

0

C

7

0

C

7

0

C

7

0

C

7

0

7

4

3

0

background image

\32

Z86C21 MCU

WITH

 8K ROM

6.5

DEC

R1

 

6.5

DEC

IR1

 

6.5

ADD

r1, r2 

6.5

ADD

r1, Ir2 

10.5

ADD

R2, R1 

10.5

ADD

IR2, R1 

10.5

ADD

R1, IM

10.5

ADD

IR1, IM

 

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Lower Nibble (Hex)

Upper Nibble (Hex)

Bytes per Instruction

2

3

2

3

1

6.5

RLC

R1

 

6.5

RLC

IR1

 

6.5

ADC

r1, r2 

6.5

ADC

r1, Ir2 

10.5

ADC

R2, R1 

10.5

ADC

IR2, R1 

10.5

ADC

R1, IM

10.5

ADC

IR1, IM

 

6.5

INC

R1

 

6.5

INC

IR1

 

6.5

SUB

r1, r2 

6.5

SUB

r1, Ir2 

10.5

SUB

R2, R1 

10.5

SUB

IR2, R1 

10.5

SUB

R1, IM

10.5

SUB

IR1, IM

 

10.5

DECW

RR1

 

10.5

DECW

IR1

 

6.5

RL

R1

 

6.5

RL

IR1

 

10.5

INCW

RR1

 

10.5

INCW

IR1 

 

6.5

CP

r1, r2 

6.5

CP

r1, Ir2 

10.5

CP

R2, R1 

10.5

CP

IR2, R1 

10.5

CP

R1, IM

10.5

CP

IR1, IM

 

6.5

CLR

R1

 

6.5

CLR

IR1

 

6.5

XOR

r1, r2 

6.5

XOR

r1, Ir2 

10.5

XOR

R2, R1 

10.5

XOR

IR2, R1 

10.5

XOR

R1, IM

10.5

XOR

IR1, IM

 

6.5

RRC

R1

 

6.5

RRC

IR1

 

12.0

LDC

r1, Irr2 

18.0

LDCI

Ir1, Irr2 

10.5

LD

r1,x,R2

6.5

SRA

R1

 

6.5

SRA

IR1

 

20.0

CALL*

IRR1 

20.0

CALL

DA

10.5

LD

r2,x,R1

6.5

RR

R1

 

6.5

RR

IR1

 

6.5

LD

r1, IR2 

10.5

LD

R2, R1 

10.5

LD

IR2, R1 

10.5

LD

R1, IM

10.5

LD

IR1, IM

 

8.5

SWAP

R1

 

8.5

SWAP

IR1

 

6.5

LD

Ir1, r2

10.5

LD

R2, IR1

6.5

LD

r1, R2

 

6.5

LD

r2, R1

 

12/10.5

DJNZ

r1, RA

 

12/10.0

JR

cc, RA

 

6.5

LD

r1, IM

 

12.10.0

JP

cc, DA

 

6.5

INC

r1

 

6.0

STOP

 

7.0

HALT

 

6.1

DI

 

6.1

EI

 

14.0

RET

 

16.0

IRET

 

6.5

RCF

 

6.5

SCF

 

6.5

CCF

 

6.0

NOP

 

 10.5

CP

R1, R2

4

A

Lower

Opcode

Nibble

Pipeline

Cycles

Mnemonic

Second

Operand

Execution

Cycles

Upper

Opcode

Nibble

First

Operand

Legend:

R = 8-bit Address

r = 4-bit Address

R1 or  r1 = Dst Address

R2 or  r2 = Src Address

Sequence:

Opcode, First Operand,

Second Operand

Note: 

Blank areas not defined.

*

2-byte instruction appears as

  a 3-byte instruction

8.0

JP

IRR1

 

6.1

SRP

IM

 

6.5

SBC

r1, r2 

6.5

SBC

r1, Ir2 

10.5

SBC

R2, R1 

10.5

SBC

IR2, R1 

10.5

SBC

R1, IM

10.5

SBC

IR1, IM

 

8.5

DA

R1

 

8.5

DA

IR1

 

6.5

OR

r1, r2 

6.5

OR

r1, Ir2 

10.5

OR

R2, R1 

10.5

OR

IR2, R1 

10.5

OR

R1, IM

10.5

OR

IR1, IM

 

10.5

POP

R1

 

10.5

POP

IR1

 

6.5

AND

r1, r2 

6.5

AND

r1, Ir2 

10.5

AND

R2, R1 

10.5

AND

IR2, R1 

10.5

AND

R1, IM

10.5

AND

IR1, IM

 

6.5

COM

R1

 

6.5

COM

IR1

 

6.5

TCM

r1, r2 

6.5

TCM

r1, Ir2 

10.5

TCM

R2, R1 

10.5

TCM

IR2, R1 

10.5

TCM

R1, IM

10.5

TCM

IR1, IM

 

10/12.1

PUSH

R2

 

12/14.1

PUSH

IR2

 

6.5

TM

r1, r2 

6.5

TM

r1, Ir2 

10.5

TM

R2, R1 

10.5

TM

IR2, R1 

10.5

TM

R1, IM

10.5

TM

IR1, IM

 

12.0

LDC

r1, Irr2 

18.0

LDCI

Ir1, Irr2 

12.0

LDE

r1, Irr2 

18.0

LDEI

Ir1, Irr2 

12.0

LDE

r2, Irr1

18.0

LDEI

Ir2, Irr1

OPCODE MAP

background image

33

Z86C21 MCU

WITH

 8K ROM

PACKAGE INFORMATION

40-Pin PDIP Package Diagram

44-Pin PLCC Package Diagram

background image

\34

Z86C21 MCU

WITH

 8K ROM

PACKAGE INFORMATION 

(Continued)

44-Pin QFP Package Diagram

background image

35

Z86C21 MCU

WITH

 8K ROM

ORDERING INFORMATION

Z86C21

12 MHz

40-pin DIP

44-pin PLCC

44-pin QFP

Z86C2112PSC

Z86C2112VSC

Z86C2112FSC

Z86C2112PEC

Z86C2112VEC

Z86C2112FEC

Example:

Z   89C21   12   P   S   C

Environmental Flow

Temperature

Package

Speed

Product Number

Zilog Prefix

is a Z89C21, 12 MHz, DIP, 0

°

C to +70

°

C, Plastic Standard Flow

16 MHz

40-pin DIP

44-pin PLCC

44-pin QFP

Z86C2116PSC

Z86C2116VSC

Z86C2116FSC

Zilog’s products are not authorized for use as critical compo-

nents in life support devices or systems unless a specific written

agreement pertaining to such intended use is executed between

the customer and Zilog prior to use. Life support devices or

systems are those which are intended for surgical implantation

into the body, or which sustains life whose failure to perform,

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result in

significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.

Campbell, CA 95008-6600

Telephone (408) 370-8000

Telex 910-338-7621

FAX 408 370-8056

Internet: http://www.zilog.com

© 1995 by Zilog, Inc. All rights reserved. No part of this document

may be copied or reproduced in any form or by any means

without the prior written consent of Zilog, Inc. The information in

this document is subject to change without notice. Devices sold

by Zilog, Inc. are covered by warranty and patent indemnification

provisions appearing in Zilog, Inc. Terms and Conditions of Sale

only. Zilog, Inc. makes no warranty, express, statutory, implied or

by description, regarding the information set forth herein or

regarding the freedom of the described devices from intellectual

property infringement. Zilog, Inc. makes no warranty of mer-

chantability or fitness for any purpose. Zilog, Inc. shall not be

responsible for any errors that may appear in this document.

Zilog, Inc. makes no commitment to update or keep current the

information contained in this document.

For fast results, contact your local Zilog Sales Office for assistance in ordering the part desired.

CODES

Preferred Package

P = Plastic DIP

V = Plastic Chip Carrier

Longer Lead Time

F = Plastic Quad Flat Pack

Preferred Temperature

S = 0

°

C to +70

°

C

Longer Lead Time

E = -40

°

C to +105

°

C

Speeds

12 = 12 MHz

16 = 16 MHz

Environmental

C = Plastic Standard


Document Outline