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Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent

licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

© INTEL CORPORATION, 1993

November 1993

Order Number: 270727-006

80960CA-33, -25, -16

32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

•  Two Instructions/Clock Sustained Execution

•  Four 59 Mbytes/s DMA Channels with Data Chaining

•  Demultiplexed 32-bit Burst Bus with Pipelining

s

32-bit Parallel Architecture

— Two Instructions/clock Execution

— Load/Store Architecture

— Sixteen 32-bit Global Registers

— Sixteen 32-bit Local Registers

— Manipulates 64-bit Bit Fields

— 11 Addressing Modes

— Full Parallel Fault Model

— Supervisor Protection Model

s

Fast Procedure Call/Return Model

— Full Procedure Call in 4 Clocks

s

On-Chip Register Cache

— Caches Registers on Call/Ret

— Minimum of 6 Frames Provided

— Up to 15 Programmable Frames

s

On-Chip Instruction Cache

— 1 Kbyte Two-Way Set Associative

— 128-bit Path to Instruction Sequencer

— Cache-Lock Modes

— Cache-Off Mode

s

High Bandwidth On-Chip Data RAM

— 1 Kbyte On-Chip Data RAM

— Sustains 128 bits per Clock Access

s

Four On-Chip DMA Channels

— 59 Mbytes/s Fly-by Transfers

— 32 Mbytes/s Two-Cycle Transfers

— Data Chaining

— Data Packing/Unpacking

— Programmable Priority Method

s

32-Bit Demultiplexed Burst Bus

— 128-bit Internal Data Paths to and

from Registers

— Burst Bus for DRAM Interfacing

— Address Pipelining Option

— Fully Programmable Wait States

— Supports 8-, 16- or 32-bit Bus Widths

— Supports Unaligned Accesses

— Supervisor Protection Pin

s

Selectable Big or Little Endian Byte 

Ordering

s

High-Speed Interrupt Controller

— Up to 248 External Interrupts

— 32 Fully Programmable Priorities

— Multi-mode 8-bit Interrupt Port

— Four Internal DMA Interrupts

— Separate, Non-maskable Interrupt Pin

— Context Switch in 750 ns Typical

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ii

CONTENTS

PAGE

1.0  PURPOSE .................................................................................................................................................. 1

2.0  80960CA OVERVIEW................................................................................................................................. 1

2.1  The C-Series Core .............................................................................................................................. 2

2.2  Pipelined, Burst Bus  ........................................................................................................................... 2

2.3  Flexible DMA Controller ...................................................................................................................... 2

2.4  Priority Interrupt Controller .................................................................................................................. 2

2.5  Instruction Set Summary  .................................................................................................................... 3

3.0  PACKAGE INFORMATION......................................................................................................................... 4

3.1  Package Introduction  .......................................................................................................................... 4

3.2  Pin Descriptions .................................................................................................................................. 4

3.3  80960CA Mechanical Data  ............................................................................................................... 11

3.3.1  80960CA PGA Pinout  ............................................................................................................ 11

3.3.2  80960CA PQFP Pinout  .......................................................................................................... 15

3.4  Package Thermal Specifications  ...................................................................................................... 18

3.5  Stepping Register Information  .......................................................................................................... 20

3.6  Suggested Sources for 80960CA Accessories.................................................................................. 20

4.0  ELECTRICAL SPECIFICATIONS............................................................................................................. 21

4.1  Absolute Maximum Ratings  .............................................................................................................. 21

4.2  Operating Conditions  ........................................................................................................................ 21

4.3  Recommended Connections  ............................................................................................................ 21

4.4  DC Specifications  ............................................................................................................................. 22

4.5  AC Specifications .............................................................................................................................. 23

4.5.1  AC Test Conditions  ................................................................................................................ 29

4.5.2  AC Timing Waveforms  ........................................................................................................... 29

4.5.3  Derating Curves  ..................................................................................................................... 33

5.0  RESET, BACKOFF AND HOLD ACKNOWLEDGE ................................................................................. 35

6.0  BUS WAVEFORMS ................................................................................................................................. 36

7.0  REVISION HISTORY ................................................................................................................................ 64

80960CA-33, -25, -16

32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

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iii

CONTENTS

PAGE

LIST OF FIGURES

Figure 1

80960CA Block Diagram  .............................................................................................................. 1

Figure 2

80960CA PGA Pinout—View from Top (Pins Facing Down)  ...................................................... 13

Figure 3

80960CA PGA Pinout —View from Bottom (Pins Facing Up)  .................................................... 14

Figure 4

80960CA PQFP Pinout (View from Top Side)  ............................................................................ 17

Figure 5

Measuring 80960CA PGA and PQFP Case Temperature .......................................................... 18

Figure 6

Register g0  ................................................................................................................................. 20

Figure 7

AC Test Load  .............................................................................................................................. 29

Figure 8

Input and Output Clocks Waveform ............................................................................................ 29

Figure 9

CLKIN Waveform ........................................................................................................................ 29

Figure 10

Output Delay and Float Waveform  ............................................................................................. 30

Figure 11

Input Setup and Hold Waveform  ................................................................................................ 30

Figure 12

NMI, XINT7:0 Input Setup and Hold Waveform .......................................................................... 31

Figure 13

Hold Acknowledge Timings  ........................................................................................................ 31

Figure 14

Bus Backoff (BOFF) Timings ...................................................................................................... 32

Figure 15

Relative Timings Waveforms  ...................................................................................................... 33

Figure 16

Output Delay or Hold vs. Load Capacitance  .............................................................................. 33

Figure 17

Rise and Fall Time Derating at Highest Operating Temperature and Minimum V

CC

.................. 34

Figure 18

I

CC

 vs. Frequency and Temperature  ........................................................................................... 34

Figure 19

Cold Reset Waveform  ................................................................................................................ 36

Figure 20

Warm Reset Waveform  .............................................................................................................. 37

Figure 21

Entering the ONCE State  ........................................................................................................... 38

Figure 22

Clock Synchronization in the 2-x Clock Mode  ............................................................................ 39

Figure 23

Clock Synchronization in the 1-x Clock Mode  ............................................................................ 39

Figure 24

Non-Burst, Non-Pipelined Requests Without Wait States  .......................................................... 40

Figure 25

Non-Burst, Non-Pipelined Read Request With Wait States  ....................................................... 41

Figure 26

Non-Burst, Non-Pipelined Write Request With Wait States  ....................................................... 42

Figure 27

Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ........................................ 43

Figure 28

Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................. 44

Figure 29

Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus  ....................................... 45

Figure 30

Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus ............................................. 46

Figure 31

Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus  ............................................ 47

Figure 32

Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................... 48

Figure 33

Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus  ....................................... 49

Figure 34

Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus  ............................................ 50

Figure 35

Burst, Pipelined Read Request Without Wait States, 32-Bit Bus  ............................................... 51

Figure 36

Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..................................................... 52

Figure 37

Burst, Pipelined Read Request With Wait States, 16-Bit Bus ..................................................... 53

Figure 38

Burst, Pipelined Read Request With Wait States, 8-Bit Bus ....................................................... 54

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iv

CONTENTS

PAGE

LIST OF FIGURES (continued)

Figure 39

Using External READY ............................................................................................................... 55

Figure 40

Terminating a Burst with BTERM ............................................................................................... 56

Figure 41

BOFF Functional Timing  ............................................................................................................ 57

Figure 42

HOLD Functional Timing  ............................................................................................................ 58

Figure 43

DREQ and DACK Functional Timing  .......................................................................................... 59

Figure 44

EOP Functional Timing  .............................................................................................................. 59

Figure 45

Terminal Count Functional Timing .............................................................................................. 60

Figure 46

FAIL Functional Timing ............................................................................................................... 60

Figure 47

A Summary of Aligned and Unaligned Transfers for Little Endian Regions ................................ 61

Figure 48

A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ............ 62

Figure 49

Idle Bus Operation ...................................................................................................................... 63

LIST OF TABLES

Table 1

80960CA Instruction Set  .............................................................................................................. 3

Table 2

Pin Description Nomenclature ...................................................................................................... 4

Table 3

80960CA Pin Description — External Bus Signals  ...................................................................... 5

Table 4

80960CA Pin Description — Processor Control Signals  .............................................................. 8

Table 5

80960CA Pin Description — DMA and Interrupt Unit Control Signals  ....................................... 10

Table 6

80960CA PGA Pinout — In Signal Order ................................................................................... 11

Table 7

80960CA PGA Pinout — In Pin Order ........................................................................................ 12

Table 8

80960CA PQFP Pinout — In Signal Order ................................................................................. 15

Table 9

80960CA PQFP Pinout — In Pin Order  ..................................................................................... 16

Table 10

Maximum T

A

 at Various Airflows in

o

C (PGA Package Only)  ..................................................... 18

Table 11

80960CA PGA Package Thermal Characteristics  ...................................................................... 19

Table 12

80960CA PQFP Package Thermal Characteristics .................................................................... 19

Table 13

Die Stepping Cross Reference  ................................................................................................... 20

Table 14

Operating Conditions (80960CA-33, -25, -16) ............................................................................ 21

Table 15

DC Characteristics  ..................................................................................................................... 22

Table 16

80960CA AC Characteristics (33 MHz)  ...................................................................................... 23

Table 17

80960CA AC Characteristics (25 MHz)  ...................................................................................... 25

Table 18

80960CA AC Characteristics (16 MHz)  ...................................................................................... 27

Table 19

Reset Conditions  ........................................................................................................................ 35

Table 20

Hold Acknowledge and Backoff Conditions  ................................................................................ 35

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1

80960CA-33, -25, -16

1.0

PURPOSE

This document provides electrical characteristics for

the 33, 25 and 16 MHz versions of the 80960CA. For

a detailed description of any 80960CA functional

topic—other than parametric performance—consult

the 80960CA Product Overview (Order No. 270669)

or the i960

®

 CA Microprocessor User’s Manual

(Order No. 270710). To obtain data sheet updates

and errata, please call Intel’s FaxBACK

®

 data-on-

demand system (1-800-628-2283 or 916-356-3105).

Other information can be obtained from Intel’s tech-

nical BBS (916-356-3600).

2.0

80960CA OVERVIEW

The 80960CA is the second-generation member of

the 80960 family of embedded processors. The

80960CA is object code compatible with the 32-bit

80960 Core Architecture while including Special

Function Register extensions to control on-chip

peripherals and instruction set extensions to shift 64-

bit operands and configure on-chip hardware.

Multiple 128-bit internal buses, on-chip instruction

caching and a sophisticated instruction scheduler

allow the processor to sustain execution of two

instructions every clock and peak at execution of

three instructions per clock.

A 32-bit demultiplexed and pipelined burst bus

provides a 132 Mbyte/s bandwidth to a system’s

high-speed external memory sub-system. In

addition, the 80960CA’s on-chip caching of instruc-

tions, procedure context and critical program data

substantially decouple system performance from the

wait states associated with accesses to the system’s

slower, cost sensitive, main memory subsystem.

The 80960CA bus controller integrates full wait state

and bus width control for highest system perfor-

mance with minimal system design complexity.

Unaligned access and Big Endian byte order support

reduces the cost of porting existing applications to

the 80960CA.

The processor also integrates four complete data-

chaining DMA channels and a high-speed interrupt

controller on-chip. DMA channels perform: single-

cycle or two-cycle transfers, data packing and

unpacking and data chaining. Block transfers—in

addition to source or destination synchronized trans-

fers—are provided.

The interrupt controller provides full programmability

of 248 interrupt sources into 32 priority levels with a

typical interrupt task switch (”latency”) time of

750 ns.

Figure 1.  80960CA Block Diagram

Execution

Unit

Programmable

Bus

Controller

Bus Request

Queues

Six-port

Register File

64-Bit

SRC1 Bus

64-Bit

SRC2 Bus

64-Bit

DST Bus

32-Bit

Base Bus

128-Bit

Load Bus

128-Bit

Store Bus

Instruction Prefetch Queue

Instruction Cache

(1 KByte, Two-way

Set Associative)

128-BIT CACHE BUS

Interrupt Controller

Control

Address

Data

Memory-side

Machine Bus

Register-side

Machine Bus

Parallel

Instruction

Scheduler

Memory Region

Configuration

Multiply/Divide

Unit

Four-Channel

DMA Controller

Interrupt 

Port

1 KByte 

5 to 15 Sets 

Register Cache

Data RAM

Address

Generation Unit

F_CX001A

DMA

Port

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2

80960CA-33, -25, -16

2.1

The C-Series Core

The C-Series core is a very high performance

microarchitectural implementation of the 80960 Core

Architecture. The C-Series core can sustain execu-

tion of two instructions per clock (66 MIPs at

33 MHz). To achieve this level of performance, Intel

has incorporated state-of-the-art silicon technology

and innovative microarchitectural constructs into the

implementation of the C-Series core. Factors that

contribute to the core’s performance include:

Parallel instruction decoding allows issuance of 

up to three instructions per clock

Single-clock execution of most instructions

Parallel instruction decode allows sustained, 

simultaneous execution of two single-clock 

instructions every clock cycle

Efficient instruction pipeline minimizes pipeline 

break losses

Register and resource scoreboarding allow simul-

taneous multi-clock instruction execution

Branch look-ahead and prediction allows many 

branches to execute with no pipeline break

Local Register Cache integrated on-chip caches 

Call/Return context

Two-way set associative, 1 Kbyte integrated 

instruction cache

1 Kbyte integrated Data RAM sustains a four-

word (128-bit) access every clock cycle

2.2

Pipelined, Burst Bus

A 32-bit high performance bus controller interfaces

the 80960CA to external memory and peripherals.

The Bus Control Unit features a maximum transfer

rate of 132 Mbytes per second (at 33 MHz). Inter-

nally programmable wait states and 16 separately

configurable memory regions allow the processor to

interface with a variety of memory subsystems with a

minimum of system complexity and a maximum of

performance. The Bus Controller’s main features

include:

Demultiplexed, Burst Bus to exploit most efficient 

DRAM access modes

Address Pipelining to reduce memory cost while 

maintaining performance

32-, 16- and 8-bit modes for I/O interfacing ease

Full internal wait state generation to reduce 

system cost

Little and Big Endian support to ease application 

development

Unaligned access support for code portability

Three-deep request queue to decouple the bus 

from the core

2.3

Flexible DMA Controller

A four-channel DMA controller provides high speed

DMA control for data transfers involving peripherals

and memory. The DMA provides advanced features

such as data chaining, byte assembly and disas-

sembly and a high performance fly-by mode capable

of transfer speeds of up to 59 Mbytes per second at

33 MHz. The DMA controller features a performance

and flexibility which is only possible by integrating the

DMA controller and the 80960CA core.

2.4

Priority Interrupt Controller

A programmable-priority interrupt controller

manages up to 248 external sources through the 8-

bit external interrupt port. The Interrupt Unit also

handles the four internal sources from the DMA

controller and a single non-maskable interrupt input.

The 8-bit interrupt port can also be configured to

provide individual interrupt sources that are level or

edge triggered.

Interrupts in the 80960CA are prioritized and

signaled within 270 ns of the request. If the interrupt

is of higher priority than the processor priority, the

context switch to the interrupt routine typically is

complete in another 480 ns. The interrupt unit

provides the mechanism for the low latency and high

throughput interrupt service which is essential for

embedded applications.

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3

80960CA-33, -25, -16

2.5

Instruction Set Summary

Table 1 summarizes the 80960CA instruction set by logical groupings. See the i960

®

 CA Microprocessor User’s

Manual for a complete description of the instruction set.

Table 1.  80960CA Instruction Set

Data 

Movement

Arithmetic

Logical

Bit and Bit Field 

and Byte

Load

Store

Move

Load Address

Add

Subtract

Multiply

Divide

Remainder

Modulo

Shift

*Extended Shift

Extended Multiply

Extended Divide

Add with Carry

Subtract with Carry

Rotate

And

Not And

And Not

Or

Exclusive Or

Not Or

Or Not

Nor

Exclusive Nor

Not

Nand

Set Bit

Clear Bit

Not Bit

Alter Bit

Scan For Bit

Span Over Bit

Extract

Modify

Scan Byte for Equal

Comparison

Branch

Call/Return

Fault

Compare

Conditional Compare

Compare and 

Increment

Compare and 

Decrement

Test Condition Code

Check Bit

Unconditional Branch

Conditional Branch

Compare and Branch

Call

Call Extended

Call System

Return

Branch and Link

Conditional Fault

Synchronize Faults

Debug

Processor 

Management

Atomic

Modify Trace Controls

Mark

Force Mark

Flush Local Registers

Modify Arithmetic 

Controls

Modify Process 

Controls

*System Control

*DMA Control

Atomic Add

Atomic Modify

NOTES:

Instructions marked by (*) are 80960CA extensions to the 80960 instruction set.

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4

80960CA-33, -25, -16

3.0

PACKAGE INFORMATION

3.1

Package Introduction

This section describes the pins, pinouts and thermal

characteristics for the 80960CA in the 168-pin

Ceramic Pin Grid Array (PGA) package and the 196-

pin Plastic Quad Flat Package (PQFP). For complete

package specifications and information, see the

Packaging Handbook (Order No. 240800).

3.2

Pin Descriptions

The 80960CA pins are described in this section.

Table 2 presents the legend for interpreting the pin

descriptions in the following tables. Pins associated

with the 32-bit demultiplexed processor bus are

described in Table 3. Pins associated with basic

processor configuration and control are described in

Table 4. Pins associated with the 80960CA DMA

Controller and Interrupt Unit are described in Table

5.

All pins float while the processor is in the ONCE

mode.

Table 2.  Pin Description Nomenclature

Symbol

Description

I

Input only pin

O

Output only pin

I/O

Pin can be either an input or output

Pins “must be” connected as described

S(...)

Synchronous. Inputs must meet setup 

and hold times relative to PCLK2:1 for 

proper operation. All outputs are 

synchronous to PCLK2:1.

S(E) 

Edge sensitive input

S(L) 

Level sensitive input

A(...)

Asynchronous. Inputs may be 

asynchronous to PCLK2:1.

A(E)

Edge sensitive input

A(L)

Level sensitive input

H(...)

While the processor’s bus is in the 

Hold Acknowledge or Bus Backoff state, 

the pin:

H(1) 

is driven to V

CC

H(0)

is driven to V

SS

H(Z) 

floats

H(Q)

continues to be a valid input

R(...)

While the processor’s RESET pin is low, 

the pin:

R(1) 

is driven to V

CC

R(0)

is driven to V

SS

R(Z) 

floats

R(Q)

continues to be a valid output

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5

80960CA-33, -25, -16

Table 3.  80960CA Pin Description — External Bus Signals  (Sheet 1 of 3)

Name

Type

Description

A31:2

O

S

H(Z)

R(Z)

ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most 

significant address bit; A2 is the least significant. During a bus access, A31:2 identify 

all external addresses to word (4-byte) boundaries. The byte enable signals indicate 

the selected byte in each word. During burst accesses, A3:2 increment to indicate 

successive data cycles.

D31:0

I/O

S(L)

H(Z)

R(Z)

DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configu-

ration. The least significant bit of the data is carried on D0 and the most significant on 

D31. When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. 

For 16-bit data bus widths, D15:0 are used. For 32-bit bus widths the full data bus is 

used.

BE3:0

O

S

H(Z)

R(1)

BYTE ENABLES select which of the four bytes addressed by A31:2 are active during 

an access to a memory region configured for a 32-bit data-bus width. BE3 applies to 

D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0.

32-bit bus:

BE3

–Byte Enable 3

–enable D31:24

BE2

–Byte Enable 2

–enable D23:16

BE1

–Byte Enable 1

–enable D15:8

BE0

–Byte Enable 0

–enable D7:0

For accesses to a memory region configured for a 16-bit data-bus width, the 

processor uses the BE3, BE1 and BE0 pins as BHE, A1 and BLE respectively.

16-bit bus:

BE3

–Byte High Enable (BHE)

–enable D15:8

BE2

–Not used (driven high or low)

BE1

–Address Bit 1 (A1)

BE0

–Byte Low Enable (BLE)

–enable D7:0

For accesses to a memory region configured for an 8-bit data-bus width, the 

processor uses the BE1 and BE0 pins as A1 and A0 respectively.

8-bit bus:

BE3

–Not used (driven high or low)

BE2

–Not used (driven high or low)

BE1

–Address Bit 1 (A1)

BE0

–Address Bit 0 (A0)

W/R

O

S

H(Z)

R(0)

WRITE/READ is asserted for read requests and deasserted for write requests. The 

W/R signal changes in the same clock cycle as ADS. It remains valid for the entire 

access in non-pipelined regions. In pipelined regions, W/R is not guaranteed to be 

valid in the last cycle of a read access.

ADS

O

S

H(Z)

R(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access. 

ADS is asserted for the first clock of a bus access.

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6

80960CA-33, -25, -16

READY

I

S(L)

H(Z)

R(Z)

READY is an input which signals the termination of a data transfer. READY is used to 

indicate that read data on the bus is valid or that a write-data transfer has completed. 

The READY signal works in conjunction with the internally programmed wait-state 

generator. If READY is enabled in a region, the pin is sampled after the programmed 

number of wait-states has expired. If the READY pin is deasserted, wait states 

continue to be inserted until READY becomes asserted. This is true for the N

RAD

N

RDD

, N

WAD

 and N

WDD

 wait states. The N

XDA

 wait states cannot be extended.

BTERM

I

S(L)

H(Z)

R(Z)

BURST TERMINATE is an input which breaks up a burst access and causes another 

address cycle to occur. The BTERM signal works in conjunction with the internally 

programmed wait-state generator. If READY and BTERM are enabled in a region, the 

BTERM pin is sampled after the programmed number of wait states has expired. 

When BTERM is asserted, a new ADS signal is generated and the access is 

completed. The READY input is ignored when BTERM is asserted. BTERM must be 

externally synchronized to satisfy BTERM setup and hold times.

WAIT

O

S

H(Z)

R(1)

WAIT indicates internal wait state generator status. WAIT is asserted when wait 

states are being caused by the internal wait state generator and not by the READY or 

BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT can also be 

thought of as a READY output that the processor provides when it is inserting wait 

states.

BLAST

O

S

H(Z)

R(0)

BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the 

last data transfer of burst and non-burst accesses after the wait state counter reaches 

zero. BLAST remains asserted until the clock following the last cycle of the last data 

transfer of a bus access. If the READY or BTERM input is used to extend wait states, 

the BLAST signal remains asserted until READY or BTERM terminates the access.

DT/R

O

S

H(Z)

R(0)

DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in 

conjunction with DEN to provide control for data transceivers attached to the external 

bus. When DT/R is asserted, the signal indicates that the processor receives data. 

Conversely, when deasserted, the processor sends data. DT/R changes only while 

DEN is high.

DEN

O

S

H(Z)

R(1)

DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of 

the bus request first data cycle and is deasserted at the end of the last data cycle. 

DEN is used in conjunction with DT/R to provide control for data transceivers attached 

to the external bus. DEN remains asserted for sequential reads from pipelined 

memory regions. DEN is deasserted when DT/R changes.

LOCK

O

S

H(Z)

R(1)

BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK

may be used to prevent external agents from accessing memory which is currently 

involved in an atomic operation. LOCK is asserted in the first clock of an atomic 

operation and deasserted in the clock cycle following the last bus access for the 

atomic operation. To allow the most flexibility for memory system enforcement of 

locked accesses, the processor acknowledges a bus hold request when LOCK is 

asserted. The processor performs DMA transfers while LOCK is active.

HOLD

I

S(L)

H(Z)

R(Z)

HOLD REQUEST signals that an external agent requests access to the external bus. 

The processor asserts HOLDA after completing the current bus request. HOLD, 

HOLDA and BREQ are used together to arbitrate access to the processor’s external 

bus by external bus agents.

Table 3.  80960CA Pin Description — External Bus Signals  (Sheet 2 of 3)

Name

Type

Description

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7

80960CA-33, -25, -16

BOFF

I

S(L)

H(Z)

R(Z)

BUS BACKOFF, when asserted, suspends the current access and causes the bus 

pins to float. When BOFF is deasserted, the ADS signal is asserted on the next clock 

cycle and the access is resumed.

HOLDA

O

S

H(1)

R(Q)

HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relin-

quished control of the external bus. When HOLDA is asserted, the external address 

bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ 

are used together to arbitrate access to the processor’s external bus by external bus 

agents. Since the processor grants HOLD requests and enters the Hold Acknowledge 

state even while RESET is asserted, the state of the HOLDA pin is independent of the 

RESET pin.

BREQ

O

S

H(Q)

R(0)

BUS REQUEST is asserted when the bus controller has a request pending. BREQ 

can be used by external bus arbitration logic in conjunction with HOLD and HOLDA to 

determine when to return mastership of the external bus to the processor.

D/C

O

S

H(Z)

R(Z)

DATA OR CODE is asserted for a data request and deasserted for instruction 

requests. D/C has the same timing as W/R.

DMA

O

S

H(Z)

R(Z)

DMA ACCESS indicates whether the bus request was initiated by the DMA controller. 

DMA is asserted for any DMA request. DMA is deasserted for all other requests.

SUP

O

S

H(Z)

R(Z)

SUPERVISOR ACCESS indicates whether the bus request is issued while in 

supervisor mode. SUP is asserted when the request has supervisor privileges and is 

deasserted otherwise. SUP can be used to isolate supervisor code and data 

structures from non-supervisor requests.

Table 3.  80960CA Pin Description — External Bus Signals  (Sheet 3 of 3)

Name

Type

Description

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8

80960CA-33, -25, -16

Table 4.  80960CA Pin Description — Processor Control Signals  (Sheet 1 of 2)

Name

Type

Description

RESET

I

A(L)

H(Z)

R(Z)

RESET causes the chip to reset. When RESET is asserted, all external signals 

return to the reset state. When RESET is deasserted, initialization begins. When 

the 2-x clock mode is selected, RESET must remain asserted for 32 CLKIN cycles 

before being deasserted to guarantee correct processor initialization. When the 1-x 

clock mode is selected, RESET must remain asserted for 10,000 CLKIN cycles 

before being deasserted to guarantee correct processor initialization. The 

CLKMODE pin selects 1-x or 2-x input clock division of the CLKIN pin.

The processor’s Hold Acknowledge bus state functions while the chip is reset. If the 

processor’s bus is in the Hold Acknowledge state when RESET is asserted, the 

processor will internally reset, but maintains the Hold Acknowledge state on 

external pins until the Hold request is removed. If a Hold request is made while the 

processor is in the reset state, the processor bus will grant HOLDA and enter the 

Hold Acknowledge state.

FAIL

O

S

H(Q)

R(0)

FAIL indicates failure of the processor’s self-test performed at initialization. When 

RESET is deasserted and the processor begins initialization, the FAIL pin is 

asserted. An internal self-test is performed as part of the initialization process. If 

this self-test passes, the FAIL pin is deasserted; otherwise it remains asserted. The 

FAIL pin is reasserted while the processor performs an external bus self-confidence 

test. If this self-test passes, the processor deasserts the FAIL pin and branches to 

the user’s initialization routine; otherwise the FAIL pin remains asserted. Internal 

self-test and the use of the FAIL pin can be disabled with the STEST pin.

STEST

I

S(L)

H(Z)

R(Z)

SELF TEST causes the processor’s internal self-test feature to be enabled or 

disabled at initialization. STEST is read on the rising edge of RESET. When 

asserted, the processor’s internal self-test and external bus confidence tests are 

performed during processor initialization. When deasserted, only the bus 

confidence tests are performed during initialization.

ONCE

I

A(L)

H(Z)

R(Z)

ON CIRCUIT EMULATION, when asserted, causes all outputs to be floated. ONCE

is continuously sampled while RESET is low and is latched on the rising edge of 

RESET. To place the processor in the ONCE state:

(1)

assert RESET and ONCE (order does not matter)

(2)

wait for at least 16 CLKIN periods in 2-x mode—or 10,000 CLKIN periods in

1-x mode—after V

CC

 and CLKIN are within operating specifications

(3)

deassert RESET

(4)

wait at least 32 CLKIN periods

(The processor will now be latched in the ONCE state as long as RESET is high.)

To exit the ONCE state, bring V

CC

 and CLKIN to operating conditions, then assert 

RESET and bring ONCE high prior to deasserting RESET.

CLKIN must operate within the specified operating conditions of the processor until 

Step 4 above has been completed. CLKIN may then be changed to DC to achieve 

the lowest possible ONCE mode leakage current.

ONCE can be used by emulator products or for board testers to effectively make an 

installed processor transparent in the board.

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9

80960CA-33, -25, -16

CLKIN

I

A(E)

H(Z)

R(Z)

CLOCK INPUT is an input for the external clock needed to run the processor. The 

external clock is internally divided as prescribed by the CLKMODE pin to produce 

PCLK2:1.

CLKMODE

I

A(L)

H(Z)

R(Z)

CLOCK MODE selects the division factor applied to the external clock input 

(CLKIN). When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and 

the processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to 

create PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high 

or low in a system as the clock mode is not latched by the processor. If left 

unconnected, the processor will internally pull the CLKMODE pin low, enabling the 

2-x clock mode.

PCLK2:1

O

S

H(Q)

R(Q)

PROCESSOR OUTPUT CLOCKS provide a timing reference for all processor 

inputs and outputs. All input and output timings are specified in relation to PCLK2 

and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are provided 

to allow flexibility in the system’s allocation of capacitive loading on the clock. 

PCLK2:1 may also be connected at the processor to form a single clock signal.

V

SS

GROUND connections must be connected externally to a V

SS

 board plane.

V

CC

POWER connections must be connected externally to a V

CC

 board plane.

V

CCPLL

V

CCPLL

 is a separate V

CC

 supply pin for the phase lock loop used in 1-x clock mode. 

Connecting a simple lowpass filter to V

CCPLL

 may help reduce clock jitter (T

CP

) in 

noisy environments. Otherwise, V

CCPLL

 should be connected to V

CC

. This pin is 

implemented starting with the D-stepping. See Table 13 for die stepping 

information.

NC

NO CONNECT pins must not be connected in a system.

Table 4.  80960CA Pin Description — Processor Control Signals  (Sheet 2 of 2)

Name

Type

Description

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80960CA-33, -25, -16

Table 5.  80960CA Pin Description — DMA and Interrupt Unit Control Signals

Name

Type

Description

DREQ3:0

I

A(L)

H(Z)

R(Z)

DMA REQUEST causes a DMA transfer to be requested. Each of the four signals 

requests a transfer on a single channel. DREQ0 requests channel 0, DREQ1

requests channel 1, etc. When two or more channels are requested simulta-

neously, the channel with the highest priority is serviced first. The channel priority 

mode is programmable.

DACK3:0

O

S

H(1)

R(1)

DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of 

the four signals acknowledges a transfer for a single channel. DACK0 acknowl-

edges channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted 

when the requesting device of a DMA is accessed.

EOP/TC3:0

I/O

A(L)

H(Z/Q)

R(Z)

END OF PROCESS/TERMINAL COUNT can be programmed as either an input 

(EOP3:0) or as an output (TC3:0), but not both. Each pin is individually program-

mable. When programmed as an input, EOPx causes the termination of a current 

DMA transfer for the channel corresponding to the EOPx pin. EOP0 corresponds 

to channel 0, EOP1 corresponds to channel 1, etc. When a channel is configured 

for source and destination chaining, the EOP pin for that channel causes 

termination of only the current buffer transferred and causes the next buffer to be 

transferred. EOP3:0 are asynchronous inputs.

When programmed as an output, the channel’s TCx pin indicates that the channel 

byte count has reached 0 and a DMA has terminated. TCx is driven with the same 

timing as DACKx during the last DMA transfer for a buffer. If the last bus request is 

executed as multiple bus accesses, TCx will stay asserted for the entire bus 

request.

XINT7:0

I

A(E/L)

H(Z)

R(Z)

EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins can 

be configured in three modes:

Dedicated Mode:

each pin is a dedicated external interrupt source. Dedicated 

inputs can be individually programmed to be level (low) or 

edge (falling) activated.

Expanded Mode:

the eight pins act together as an 8-bit vectored interrupt 

source. The interrupt pins in this mode are level activat-

ed.Since the interrupt pins are active low, the vector number 

requested is the one’s complement of the positive logic 

value place on the port. This eliminates glue logic to 

interface to combinational priority encoders which output 

negative logic.

Mixed Mode:

XINT7:5 are dedicated sources and XINT4:0 act as the five 

most significant bits of an expanded mode vector. The least 

significant bits are set to 010 internally.

NMI

I

A(E)

H(Z)

R(Z)

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. 

NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated 

source.

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11

80960CA-33, -25, -16

3.3

80960CA Mechanical Data

3.3.1

80960CA PGA Pinout

Tables 6 and 7 list the 80960CA pin names with

package location. Figure 2 depicts the complete

80960CA PGA pinout as viewed from the top side of

the component (i.e., pins facing down). Figure 3

shows the complete 80960CA PGA pinout as viewed

from the pin-side of the package (i.e., pins facing up).

See Section 4.0, ELECTRICAL SPECIFICATIONS

for specifications and recommended connections.

Table 6.  80960CA PGA Pinout — In Signal Order

Address Bus

Data Bus

Bus Control

Processor Control

I/O

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

A31

S15

D31

R3

BE3

S5

RESET

A16

DREQ3

A7

A30

Q13

D30

Q5

BE2

S6

DREQ2

B6

A29

R14

D29

S2

BE1

S7

FAIL

A2

DREQ1

A6

A28

Q14

D28

Q4

BE0

R9

DREQ0

B5

A27

S16

D27

R2

STEST

B2

A26

R15

D26

Q3

W/R

S10

DACK3

A10

A25

S17

D25

S1

ONCE

C3

DACK2

A9

A24

Q15

D24

R1

ADS

R6

DACK1

A8

A23

R16

D23

Q2

CLKIN

C13

DACK0

B8

A22

R17

D22

P3

READY

S3

CLKMODE

C14

A21

Q16

D21

Q1

BTERM

R4

PLCK1

B14

EOP/TC3

A14

A20

P15

D20

P2

PLCK2

B13

EOP/TC2

A13

A19

P16

D19

P1

WAIT

S12

EOP/TC1

A12

A18

Q17

D18

N2

BLAST

S8

V

SS

EOP/TC0

A11

A17

P17

D17

N1

Location

A16

N16

D16

M1

DT/R

S11

C7, C8, C9, C10, 

C11, C12, F15, G3, 

G15, H3, H15, J3, 

J15, K3, K15, L3, 

L15, M3, M15, Q7, 

Q8, Q9, Q10, Q11

XINT7

C17

A15

N17

D15

L1

DEN

S9

XINT6

C16

A14

M17

D14

L2

XINT5

B17

A13

L16

D13

K1

LOCK

S14

XINT4

C15

A12

L17

D12

J1

XINT3

B16

A11

K17

D11

H1

V

CC

XINT2

A17

A10

J17

D10

H2

HOLD

R5

Location

XINT1

A15

A9

H17

D9

G1

HOLDA

S4

B7, B9, B11, B12, 

C6, E15, F3, F16, 

G2, H16, J2, J16, K2, 

K16, M2, M16, N3, 

N15, Q6, R7, R8, 

R10, R11

XINT0

B15

A8

G17

D8

F1

BREQ

R13

A7

G16

D7

E1

NMI

D15

A6

F17

D6

F2

D/C

S13

A5

E17

D5

D1

DMA

R12

A4

E16

D4

E2

SUP

Q12

V

CCPLL

B10

A3

D17

D3

C1

No Connect

A2

D16

D2

D2

BOFF

B1

Location

D1

C2

A1, A3, A4, A5, B3, 

B4, C4, C5, D3

D0

E3

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12

80960CA-33, -25, -16

Table 7.  80960CA PGA Pinout — In Pin Order

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

A1

NC

C1

D3

G1

D9

M1

D16

R1

D24

A2

FAIL

C2

D1

G2

V

CC

M2

V

CC

R2

D27

A3

NC

C3

ONCE

G3

V

SS

M3

V

SS

R3

D31

A4

NC

C4

NC

G15

V

SS

M15

V

SS

R4

BTERM

A5

NC

C5

NC

G16

A7

M16

V

CC

R5

HOLD

A6

DREQ1

C6

V

CC

G17

A8

M17

A14

R6

ADS

A7

DREQ3

C7

V

SS

R7

V

CC

A8

DACK1

C8

V

SS

H1

D11

N1

D17

R8

V

CC

A9

DACK2

C9

V

SS

H2

D10

N2

D18

R9

BE0

A10

DACK3

C10

V

SS

H3

V

SS

N3

V

CC

R10

V

CC

A11

EOP/TC0

C11

V

SS

H15

V

SS

N15

V

CC

R11

V

CC

A12

EOP/TC1

C12

V

SS

H16

V

CC

N16

A16

R12

DMA

A13

EOP/TC2

C13

CLKIN

H17

A9

N17

A15

R13

BREQ

A14

EOP/TC3

C14

CLKMODE

R14

A29

A15

XINT1

C15

XINT4

J1

D12

P1

D19

R15

A26

A16

RESET

C16

XINT6

J2

V

CC

P2

D20

R16

A23

A17

XINT2

C17

XINT7

J3

V

SS

P3

D22

R17

A22

J15

V

SS

P15

A20

B1

BOFF

D1

D5

J16

V

CC

P16

A19

S1

D25

B2

STEST

D2

D2

J17

A10

P17

A17

S2

D29

B3

NC

D3

NC

S3

READY

B4

NC

D15

NMI

K1

D13

Q1

D21

S4

HOLDA

B5

DREQ0

D16

A2

K2

V

CC

Q2

D23

S5

BE3

B6

DREQ2

D17

A3

K3

V

SS

Q3

D26

S6

BE2

B7

V

CC

K15

V

SS

Q4

D28

S7

BE1

B8

DACK0

E1

D7

K16

V

CC

Q5

D30

S8

BLAST

B9

V

CC

E2

D4

K17

A11

Q6

V

CC

S9

DEN

B10

V

CCPLL

E3

D0

Q7

V

SS

S10

W/R

B11

V

CC

E15

V

CC

L1

D15

Q8

V

SS

S11

DT/R

B12

V

CC

E16

A4

L2

D14

Q9

V

SS

S12

WAIT

B13

PCLK2

E17

A5

L3

V

SS

Q10

V

SS

S13

D/C

B14

PCLK1

L15

V

SS

Q11

V

SS

S14

LOCK

B15

XINT0

F1

D8

L16

A13

Q12

SUP

S15

A31

B16

XINT3

F2

D6

L17

A12

Q13

A30

S16

A27

B17

XINT5

F3

V

CC

Q14

A28

S17

A25

F15

V

SS

Q15

A24

F16

V

CC

Q16

A21

F17

A6

Q17

A18

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13

80960CA-33, -25, -16

Figure 2.  80960CA PGA Pinout — View from Top (Pins Facing Down)

D5

D7

D8

D9

D11

D12

D13

D15

D16

D17

D19

D21

D24

D25

D2

D4

D6

V

CC

D10

V

CC

V

CC

D14

V

CC

D18

D20

D23

D27

D29

NC

D0

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

CC

D22

D31

READY

D26

D28

BTERM

HOLDA

D30

HOLD

BE3

V

CC

ADS

BE2

V

SS

V

CC

BE1

V

SS

V

CC

BLAST

V

SS

BE0

DEN

V

SS

V

CC

W/R

V

SS

V

CC

DT/R

A29

LOCK

SUP

WAIT

DMA

A28

A30

BREQ

D/C

D3

D1

ONCE

NC

NC

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

CLKIN

CLK MODE

V

SS

BOFF

STEST

NC

NC

DREQ0

DREQ2

V

CC

DACK0

V

CC

V

CCPLL

V

CC

PCLK2

PCLK1

V

CC

NC

FAIL

NC

NC

NC

DREQ1

DREQ3

DACK1

DACK2

DACK3

EOP/TC0

EOP/TC2

EOP/TC3

EOP/TC1

V

SS

A2

V

CC

A22

A25

A20

V

SS

A3

A5

NMI

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

A24

A31

A26

A4

V

CC

A6

A8

A9

A10

A11

A12

A14

A15

A17

A18

V

CC

V

CC

V

CC

A13

V

CC

A16

A19

A21

A23

A27

A7

XINT6

XINT7

XINT4

XINT3

XINT5

XINT0

RESET

XINT2

XINT1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

A

B

C

D

E

F

G

H

J

K

L

M

N

P

Q

R

S

F_CA002A

A

B

C

D

E

F

G

H

J

K

L

M

N

P

Q

R

S

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14

80960CA-33, -25, -16

Figure 3.  80960CA PGA Pinout — View from Bottom (Pins Facing Up)

D5

D7

D8

D9

D11

D12

D13

D15

D16

D17

D19

D21

D24

D25

D2

D4

D6

V

CC

D10

V

CC

V

CC

D14

V

CC

D18

D20

D23

D27

D29

NC

D0

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

CC

D22

D31

READY

D26

D28

BTERM HOLDA

D30

HOLD

BE3

V

CC

ADS

BE2

V

SS

V

CC

BE1

V

SS

V

CC

BLAST

V

SS

BE0

DEN

V

SS

V

CC

W/R

V

SS

V

CC

DT/R

A29

LOCK

SUP

WAIT

DMA

A28

A30

BREQ

D/C

D3

D1

ONCE

NC

NC

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

CLKIN

CLK MODE

V

SS

BOFF

STEST

NC

NC

DREQ0

DREQ2

V

CC

DACK0

V

CC

V

CCPLL

V

CC

PCLK2

PCLK1

V

CC

NC

FAIL

NC

NC

NC

DREQ1

DREQ3

DACK1

DACK2

DACK3

EOP/TC0

EOP/TC2

EOP/TC3

EOP/TC1

V

SS

A2

V

CC

A22

A25

A20

V

SS

A3

A5

NMI

V

CC

V

SS

V

SS

V

SS

V

SS

V

SS

A24

A31

A26

A4

V

CC

A6

A8

A9

A10

A11

A12

A14

A15

A17

A18

V

CC

V

CC

V

CC

A13

V

CC

A16

A19

A21

A23

A27

A7

XINT6

XINT7

XINT4

XINT3

XINT5

XINT0

RESET

XINT2

XINT1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

F_CA003A

A

B

C

D

E

F

G

H

J

K

L

M

N

P

Q

R

S

A

B

C

D

E

F

G

H

J

K

L

M

N

P

Q

R

S

Metal Lid

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15

80960CA-33, -25, -16

3.3.2

80960CA PQFP Pinout

Tables 8 and 9 list the 80960CA pin names with

package location. Figure 4 shows the 80960CA

PQFP pinout as viewed from the top side.

See Section 4.0, ELECTRICAL SPECIFICATIONS

for specifications and recommended connections.

Table 8.  80960CA PQFP Pinout — In Signal Order

Address Bus

Data Bus

Bus Control

Processor Control

I/O

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

A31

153

D31

186

BE3

176

RESET

91

DREQ3

60

A30

152

D30

187

BE2

175

FAIL

45

DREQ2

59

A29

151

D29

188

BE1

172

STEST

46

DREQ1

58

A28

145

D28

189

BE0

170

ONCE

43

DREQ0

57

A27

144

D27

191

CLKIN

87

A26

143

D26

192

W/R

164

CLKMODE

85

DACK3

65

A25

142

D25

194

PCLK2

74

DACK2

64

A24

141

D24

195

ADS

178

PCLK1

78

DACK1

63

A23

139

D23

3

V

SS

DACK0

62

A22

138

D22

4

READY

182

Location

A21

137

D21

5

BTERM

184

2, 7, 16, 24, 30, 38, 

39, 49, 56, 70, 75, 

77, 81, 83, 88, 89, 

92, 98, 105, 109, 

110, 121, 125, 131, 

135, 147, 150, 161, 

165, 173, 174, 185, 

196

EOP/TC3

69

A20

136

D20

6

EOP/TC2

68

A19

134

D19

8

WAIT

162

EOP/TC1

67

A18

133

D18

9

BLAST

169

EOP/TC0

66

A17

132

D17

10

A16

130

D16

11

DT/R

163

XINT7

107

A15

129

D15

13

DEN

167

V

CC

XINT6

106

A14

128

D14

14

Location

XINT5

102

A13

124

D13

15

LOCK

156

1, 12, 20, 28, 32, 37, 

44, 50, 61, 71, 79, 

82, 96, 99, 103, 115, 

127, 140, 148, 154, 

168, 171, 180, 190

XINT4

101

A12

123

D12

17

XINT3

100

A11

122

D11

18

HOLD

181

XINT2

95

A10

120

D10

19

HOLDA

179

XINT1

94

A9

119

D9

21

BREQ

155

XINT0

93

A8

118

D8

22

V

CCPLL

72

A7

117

D7

23

D/C

159

No Connect

NMI

108

A6

116

D6

25

DMA

160

Location

A5

114

D5

26

SUP

158

29, 31, 41, 42, 47, 

48, 51, 52, 53, 54, 

55, 73, 76, 80, 84, 

86, 90, 97, 104, 126, 

146, 149, 157, 166, 

177, 183, 193

A4

113

D4

27

A3

112

D3

33

BOFF

40

A2

111

D2

34

D1

35

D0

36

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16

80960CA-33, -25, -16

Table 9.  80960CA PQFP Pinout — In Pin Order

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

1

V

CC

34

D2

67

EOP

/

TC1

100

XINT3

133

A18

166

NC

2

V

SS

35

D1

68

EOP

/

TC2

101

XINT4

134

A19

167

DEN

3

D23

36

D0

69

EOP

/

TC3

102

XINT5

135

V

SS

168

V

CC

4

D22

37

V

CC

70

V

SS

103

V

CC

136

A20

169

BLAST

5

D21

38

V

SS

71

V

CC

104

NC

137

A21

170

BE0

6

D20

39

V

SS

72

V

CCPLL

105

V

SS

138

A22

171

V

CC

7

V

SS

40

BOFF

73

NC

106

XINT6

139

A23

172

BE1

8

D19

41

NC

74

PCLK2

107

XINT7

140

V

CC

173

V

SS

9

D18

42

NC

75

V

SS

108

NMI

141

A24

174

V

SS

10

D17

43

ONCE

76

NC

109

V

SS

142

A25

175

BE2

11

D16

44

V

CC

77

V

SS

110

V

SS

143

A26

176

BE3

12

V

CC

45

FAIL

78

PCLK1

111

A2

144

A27

177

NC

13

D15

46

STEST

79

V

CC

112

A3

145

A28

178

ADS

14

D14

47

NC

80

NC

113

A4

146

NC

179

HOLDA

15

D13

48

NC

81

V

SS

114

A5

147

V

SS

180

V

CC

16

V

SS

49

V

SS

82

V

CC

115

V

CC

148

V

CC

181

HOLD

17

D12

50

V

CC

83

V

SS

116

A6

149

NC

182

READY

18

D11

51

NC

84

NC

117

A7

150

V

SS

183

NC

19

D10

52

NC

85

CLKMODE

118

A8

151

A29

184

BTERM

20

V

CC

53

NC

86

NC

119

A9

152

A30

185

V

SS

21

D9

54

NC

87

CLKIN

120

A10

153

A31

186

D31

22

D8

55

NC

88

V

SS

121

V

SS

154

V

CC

187

D30

23

D7

56

V

SS

89

V

SS

122

A11

155

BREQ

188

D29

24

V

SS

57

DREQ0

90

NC

123

A12

156

LOCK

189

D28

25

D6

58

DREQ1

91

RESET

124

A13

157

NC

190

V

CC

26

D5

59

DREQ2

92

V

SS

125

V

SS

158

SUP

191

D27

27

D4

60

DREQ3

93

XINT0

126

NC

159

D/

C

192

D26

28

V

CC

61

V

CC

94

XINT1

127

V

CC

160

DMA

193

NC

29

NC

62

DACK0

95

XINT2

128

A14

161

V

SS

194

D25

30

V

SS

63

DACK1

96

V

CC

129

A15

162

WAIT

195

D24

31

NC

64

DACK2

97

NC

130

A16

163

DT/

R

196

V

SS

32

V

CC

65

DACK3

98

V

SS

131

V

SS

164

W/

R

33

D3

66

EOP

/

TC0

99

V

CC

132

A17

165

V

SS

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17

80960CA-33, -25, -16

Figure 4.  80960CA PQFP Pinout (View from Top Side)

50

98

99

147

148

196

Pin 1

49

F_CA004A

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18

80960CA-33, -25, -16

3.4

Package Thermal Specifications

The 80960CA is specified for operation when T

C

(case temperature) is within the range of 0

o

C–100

o

C.

T

C

 may be measured in any environment to deter-

mine whether the 80960CA is within specified oper-

ating range. Case temperature should be measured

at the center of the top surface, opposite the pins.

Refer to Figure 5.

T

A

 (ambient temperature) can be calculated from

θ

CA

(thermal resistance from case to ambient) using the

following equation:

T

A

 = T

C

 – P*

θ

CA

Table 10 shows the maximum T

A

 allowable (without

exceeding T

C

) at various airflows and operating

frequencies (f

PCLK

).

Note that T

A

 is greatly improved by attaching fins or a

heatsink to the package. P (maximum power

consumption) is calculated by using the typical I

CC

as tabulated in Section 4.4, DC Specifications and

V

CC

 of 5V.

Figure 5.  Measuring 80960CA PGA and PQFP Case Temperature

Table 10.  Maximum T

A

 at Various Airflows in

o

C (PGA Package Only)

Airflow-ft/min (m/sec)

f

PCLK

(MHz)

0

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.07)

T

A

 with 

Heatsink*

33

25

16

51

61

74

66

73

82

79

83

89

81

85

90

85

88

92

87

89

93

T

A

 without 

Heatsink*

33

25

16

36

49

66

47

58

72

59

67

78

66

73

82

73

78

86

75

80

87

NOTES:

*0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).

Measure PQFP case temperature

at center of top surface.

Measure PGA temperature at

center of top surface

168 - Pin PGA

Pin 196

Pin 1

F_CX007A

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19

80960CA-33, -25, -16

Table 11.  80960CA PGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Parameter

Airflow — ft./min (m/sec)

0

(0)

200

(1.01)

400

(2.03)

600

(3.07)

800

(4.06)

1000

(5.07)

θ

 Junction-to-Case 

(Case measured as 

shown in Figure 5)

1.5

1.5

1.5

1.5

1.5

1.5

θ

 Case-to-Ambient 

(No Heatsink)

17

14

11

9

7.1

6.6

θ

 Case-to-Ambient 

(With Heatsink)*

13

9

5.5

5

3.9

3.4

NOTES:

1. This table applies to 80960CA PGA plugged into socket or soldered directly to board.

2.

θ

JA

 =

θ

JC

 +

θ

CA

*0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).

Table 12.  80960CA PQFP Package Thermal Characteristics

Thermal Resistance — °C/Watt

Parameter

Airflow — ft./min (m/sec)

0

(0)

50

(0.25)

100

(0.50)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

θ

 Junction-to-Case (Case Measured 

as shown in Figure 5)

5

5

5

5

5

5

5

θ

 Case-to-Ambient (No Heatsink)

19

18

17

15

12

10

9

NOTES:

1. This table applies to 80960CA PQFP soldered directly to board.

2.

θ

JA

 =

θ

JC

 +

θ

CA

θ

JC

θ

JA

θ

JC

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20

80960CA-33, -25, -16

3.5

Stepping Register Information

Upon reset, register g0 contains die stepping infor-

mation. Figure 6 shows how g0 is configured. The

most significant byte contains an ASCII 0. The upper

middle byte contains an ASCII C. The lower middle

byte contains an ASCII A. The least significant byte

contains the stepping number in ASCII. g0 retains

this information until it is overwritten by the user

program.

Figure 6.  Register g0

Table 13 contains a cross reference of the number in

the least significant byte of register g0 to the die

stepping number.

Table 13.  Die Stepping Cross Reference

g0 Least Significant 

Byte

Die Stepping

01

B

02

C-1

03

C-2,C-3

04

D

ASCII

00

43

41

Stepping Number

DECIMAL

0

C

A

Stepping Number

MSB

LSB

3.6

Suggested Sources for 80960CA

Accessories

The following is a list of suggested sources for

80960CA accessories. This is not an endorsement of

any kind, nor is it a warranty of the performance of

any of the listed products and/or companies.

Sockets

1. 3M Textool Test and Interconnection 

Products Department

P.O. Box 2963

Austin, TX 78769-2963

2. Augat, Inc.

Interconnection Products Group

33 Perry Avenue

P.O. box 779

Attleboro, MA 02703

(508) 699-7646

3. Concept Manufacturing, Inc.

(Decoupling Sockets)

41484 Christy Street

Fremont, CA 94538

(415) 651-3804

Heatsinks/Fins

1. Thermalloy, Inc.

2021 West Valley View Lane

Dallas, TX 75234-8993

(214) 243-4321

FAX: (214) 241-4656

2. E G & G Division

60 Audubon Road

Wakefield, MA 01880

(617) 245-5900

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21

80960CA-33, -25, -16

4.0

ELECTRICAL SPECIFICATIONS

4.1

Absolute Maximum Ratings

Parameter

Maximum Rating

Storage Temperature ................................–65

o

C to +150

o

C

Case Temperature Under Bias .................–65

o

C to +110

o

C

Supply Voltage wrt. V

SS

............................. –0.5V to + 6.5V

Voltage on Other Pins wrt. V

SS

...........–0.5V to V

CC

 + 0.5V

NOTICE: This is a production data sheet. The

specifications are subject to change without notice.

*WARNING: Stressing the device beyond the

“Absolute Maximum Ratings” may cause perma-

nent damage. These are stress ratings only. Opera-

tion beyond the “Operating Conditions” is not

recommended and extended exposure beyond the

“Operating Conditions” may affect device reliability.

4.2

Operating Conditions

Table 14.  Operating Conditions (80960CA-33, -25, -16)

Symbol

Parameter

Min

Max

Units

Notes

V

CC

Supply Voltage

80960CA-33

80960CA-25

80960CA-16

4.75

4.50

4.50

5.25

5.50

5.50

V

V

V

f

CLK2x

Input Clock Frequency (2-x Mode)

80960CA-33

80960CA-25

80960CA-16

0

0

0

66.66

50

32

MHz

MHz

MHz

f

CLK1x

Input Clock Frequency (1-x Mode)

80960CA-33

80960CA-25

80960CA-16

8

8

8

33.33

25

16

MHz

MHz

MHz

(1)

T

C

Case Temperature Under Bias

PGA Package

80960CA-33, -25, -16

196-Pin PQFP

0

0

100

100

o

C

o

C

NOTES:

1. When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum fre-

quency of 8 MHz for proper processor operation. However, in the 1-x mode, CLKIN may still be stopped when the pro-

cessor either is in a reset condition or is reset. If CLKIN is stopped, the specified RESET low time must be provided once 

CLKIN restarts and has stabilized.

4.3

Recommended Connections

Power and ground connections must be made to

multiple V

CC

 and V

SS

 (GND) pins. Every 80960CA-

based circuit board should include power (V

CC

) and

ground (V

SS

) planes for power distribution. Every

V

CC

 pin must be connected to the power plane, and

every V

SS

 pin must be connected to the ground

plane. Pins identified as “NC”

must not be

connected in the system.

Liberal decoupling capacitance should be placed

near the 80960CA. The processor can cause tran-

sient power surges when its numerous output buffers

transition, particularly when connected to large

capacitive loads.

Low inductance capacitors and interconnects are

recommended for best high frequency electrical

performance. Inductance can be reduced by short-

ening the board traces between the processor and

decoupling capacitors as much as possible. Capaci-

tors specifically designed for PGA packages will offer

the lowest possible inductance.

For reliable operation, always connect unused inputs

to an appropriate signal level. In particular, any

unused interrupt (XINT, NMI) or DMA (DREQ) input

should be connected to V

CC

 through a pull-up

resistor, as should BTERM if not used. Pull-up resis-

tors should be in the in the range of 20 K

for each

pin tied high. If READY or HOLD are not used, the

unused input should be connected to ground. N.C.

pins must always remain unconnected. Refer to

the i960

®

 Cx Microprocessor User’s Manual (Order

Number 270710) for more information.

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22

80960CA-33, -25, -16

4.4

DC Specifications

Table 15.  DC Characteristics

(80960CA-33, -25, -16 under the conditions described in Section 4.2, Operating Conditions.)

Symbol

Parameter

Min

Max

Units

Notes

V

IL

Input

Low

 Voltage for all pins except RESET

– 0.3

+0.8

V

V

IH

Input High Voltage for all pins except RESET

2.0

V

CC

 + 0.3

V

V

OL

Output Low Voltage

0.45

V

I

OL

 = 5 mA

V

OH

Output High Voltage

I

OH

 = –1 mA

I

OH

 = – 200

 µ

A

2.4

V

CC

 – 0.5

V

V

V

ILR

Input Low Voltage for RESET

– 0.3

1.5

V

V

IHR

Input High Voltage for RESET

3.5

V

CC

 + 0.3

V

I

LI1

Input Leakage Current for each pin except:

BTERM, ONCE, DREQ3:0, STEST,

EOP3:0/TC3:0, NMI, XINT7:0, BOFF, READY,

HOLD, CLKMODE

±15

µA

0

 V

IN

V

CC

 (1)

I

LI2

Input Leakage Current for:

BTERM, ONCE, DREQ3:0, STEST,

EOP3:0/TC3:0, NMI, XINT7:0, BOFF

0

– 300

µA

V

IN

=

0.45V (2)

I

LI3

Input Leakage Current for:

READY, HOLD, CLKMODE

0

500

µA

V

IN

=

2.4V (3,7)

I

LO

Output Leakage Current

±15

µA

0.45

 V

OUT

V

CC

I

CC

Supply Current (80960CA-33):

I

CC

 Max

I

CC

Typ

900

750

mA

mA

(4)

(5)

I

CC

Supply Current (80960CA-25):

I

CC

 Max

I

CC

Typ

750

600

mA

mA

(4)

(5)

I

CC

Supply Current (80960CA-16):

I

CC

 Max

I

CC

Typ

550

400

mA

mA

(4)

(5)

I

ONCE

ONCE-mode Supply Current

100

mA

C

IN

Input Capacitance for:

CLKIN, RESET, ONCE, 

READY, HOLD, DREQ3:0, BOFF, 

XINT7:0, NMI, BTERM, CLKMODE

0

12

pF

F

C

 = 1 MHz

C

OUT

Output Capacitance of each output pin

12

pF

F

C

 = 1 MHz (6)

C

I/O

I/O Pin Capacitance

12

pF

F

C

 = 1 MHz

NOTES:

1. No pullup or pulldown.

2. These pins have internal pullup resistors.

3. These pins have internal pulldown resistors.

4. Measured at worst case frequency, V

CC

 and temperature, with device operating and outputs loaded to the test conditions described in Sec-

tion 4.5.1, AC Test Conditions.

5. I

CC

 Typical is not tested.

6. Output Capacitance is the capacitive load of a floating output.

7. CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted.

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23

80960CA-33, -25, -16

4.5

AC Specifications

Table 16.  80960CA AC Characteristics (33 MHz)

(80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test 

Conditions.)

Symbol

Parameter

Min

Max

Units

Notes

Input Clock (1,9)

T

F

CLKIN Frequency

0

66.66

MHz

T

C

CLKIN Period

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

30

15

125

ns

ns

(11)

T

CS

CLKIN Period Stability

In 1-x Mode (f

CLK1x

)

±0.1%

(12)

T

CH

CLKIN High Time

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

6

6

62.5

ns

ns

(11)

T

CL

CLKIN Low Time

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

6

6

62.5

ns

ns

(11)

T

CR

CLKIN Rise Time

0

6

ns

T

CF

CLKIN Fall Time

0

6

ns

Output Clocks (1,8)

T

CP

CLKIN to PCLK2:1 Delay

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

– 2

2

2

25

ns

ns

(3,12)

(3)

T

PCLK2:1 Period

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

T

C

2T

C

ns

ns

(12)

(3)

T

PH

PCLK2:1 High Time

(T/2) – 2

T/2

ns

(12)

T

PL

PCLK2:1 Low Time

(T/2) – 2

T/2

ns

(12)

T

PR

PCLK2:1 Rise Time

1

4

ns

(3)

T

PF

PCLK2:1 Fall Time

1

4

ns

(3)

Synchronous Outputs (8)

T

OH

T

OV

Output Valid Delay, Output Hold

T

OH1

, T

OV1

A31:2

T

OH2

, T

OV2

BE3:0

T

OH3

, T

OV3

ADS

T

OH4

, T

OV4

W/R

T

OH5

, T

OV5

D/C, SUP, DMA

T

OH6

, T

OV6

BLAST, WAIT

T

OH7

, T

OV7

DEN

T

OH8

, T

OV8

HOLDA, BREQ

T

OH9

, T

OV9

LOCK

T

OH10

, T

OV10

DACK3:0

T

OH11

, T

OV11

D31:0

T

OH12

, T

OV12

DT/R

T

OH13

, T

OV13

FAIL

T

OH14

, T

OV14

EOP3:0/TC3:0

3

3

6

3

4

5

3

4

4

4

3

T/2 + 3

2

3

14

16

18

18

16

16

16

16

16

18

16

T/2 + 14

14

18

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

(6,10)

(6,10)

T

OF

Output Float for all outputs

3

22

ns

(6)

Synchronous Inputs (1,9,10)

T

IS

Input Setup

T

IS1

D31:0

T

IS2

BOFF

T

IS3

BTERM/READY

T

IS4

HOLD

3

17

7

7

ns

ns

ns

ns

T

IH

Input Hold

T

IH1

D31:0

T

IH2

BOFF

T

IH3

BTERM/READY

T

IH4

HOLD

5

5

2

3

ns

ns

ns

ns

background image

24

80960CA-33, -25, -16

Relative Output Timings (1,2,3,8)

T

AVSH1

A31:2 Valid to ADS Rising

T – 4

T + 4

ns

T

AVSH2

BE3:0, W/R, SUP, D/C, 

DMA, DACK3:0 Valid to ADS Rising

T – 6

T + 6

ns

T

AVEL1

A31:2 Valid to DEN Falling

T – 4

T + 4

ns

T

AVEL2

BE3:0, W/R, SUP, INST,

DMA, DACK3:0 Valid to DEN Falling

T – 6

T + 6

ns

T

NLQV

WAIT Falling to Output Data Valid

± 4

ns

T

DVNH

Output Data Valid to WAIT Rising

N*T – 4

N*T + 4

ns

(4)

T

NLNH

WAIT Falling to WAIT Rising

N*T ± 4

ns

(4)

T

NHQX

Output Data Hold after WAIT Rising

(N+1)*T–8

(N+1)*T+6

ns

(5)

T

EHTV

DT/R Hold after DEN High

T/2 – 7

ns

(6)

T

TVEL

DT/R Valid to DEN Falling

T/2 – 4

ns

Relative Input Timings (1,2,3)

T

IS5

RESET Input Setup (2-x Clock Mode)

6

ns

(13)

T

IH5

RESET Input Hold (2-x Clock Mode)

5

ns

(13)

T

IS6

DREQ3:0 Input Setup

12

ns

(7)

T

IH6

DREQ3:0 Input Hold

7

ns

(7)

T

IS7

XINT7:0, NMI Input Setup

7

ns

(15)

T

IH7

XINT7:0, NMI Input Hold

3

ns

(15)

T

IS8

RESET Input Setup (1-x Clock Mode)

3

ns

(14)

T

IH8

RESET Input Hold (1-x Clock Mode)

T/4 + 1

ns

(14)

NOTES:

1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.

2. See Figure 16 for capacitive derating information for output delays and hold times.

3. See Figure 17 for capacitive derating information for rise and fall times.

4. Where N is the number of N

RAD

, N

RDD

, N

WAD

 or N

WDD

 wait states that are programmed in the Bus Controller Region Table. WAIT never goes 

active when there are no wait states in an access.

5. N = Number of wait states inserted with READY.

6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.

7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for 

proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asyn-

chronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor.

8. These specifications are guaranteed by the processor.

9. These specifications must be met by the system for proper operation of the processor.

10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for 

PCLK2:1 loading.

11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in 

reset, the input clock may stop even in 1-x mode.

12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adja-

cent cycles.

13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee 

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the 

CLKIN. (See Figure 22.)

14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee 

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN. 

(See Figure 23.)

15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins 

are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when assert-

ing them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecu-

tive PCLK2:1 rising edges.

Table 16.  80960CA AC Characteristics (33 MHz) (Continued)

(80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test 

Conditions.)

Symbol

Parameter

Min

Max

Units

Notes

background image

25

80960CA-33, -25, -16

Table 17.  80960CA AC Characteristics (25 MHz)

(80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test 

Conditions.)

Symbol

Parameter

Min

Max

Units

Notes

Input Clock (1,9)

T

F

CLKIN Frequency

0

50

MHz

T

C

CLKIN Period

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

40

20

125

ns

ns

(11)

T

CS

CLKIN Period Stability

In 1-x Mode (f

CLK1x

)

±0.1%

(12)

T

CH

CLKIN High Time

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

8

8

62.5

ns

ns

(11)

T

CL

CLKIN Low Time

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

8

8

62.5

ns

ns

(11)

T

CR

CLKIN Rise Time

0

6

ns

T

CF

CLKIN Fall Time

0

6

ns

Output Clocks (1,8)

T

CP

CLKIN to PCLK2:1 Delay

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

– 2

2

2

25

ns

ns

(3,12)

(3)

T

PCLK2:1 Period

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

T

C

2T

C

ns

ns

(12)

(3)

T

PH

PCLK2:1 High Time

(T/2) – 3

T/2

ns

(12)

T

PL

PCLK2:1 Low Time

(T/2) – 3

T/2

ns

(12)

T

PR

PCLK2:1 Rise Time

1

4

ns

(3)

T

PF

PCLK2:1 Fall Time

1

4

ns

(3)

Synchronous Outputs (8)

T

OH

T

OV

Output Valid Delay, Output Hold

T

OH1

, T

OV1

A31:2

T

OH2

, T

OV2

BE3:0

T

OH3

, T

OV3

ADS

T

OH4

, T

OV4

W/R

T

OH5

, T

OV5

D/C, SUP, DMA

T

OH6

, T

OV6

BLAST, WAIT

T

OH7

, T

OV7

DEN

T

OH8

, T

OV8

HOLDA, BREQ

T

OH9

, T

OV9

LOCK

T

OH10

, T

OV10

DACK3:0

T

OH11

, T

OV11

D31:0

T

OH12

, T

OV12

DT/R

T

OH13

, T

OV13

FAIL

T

OH14

, T

OV14

EOP3:0/TC3:0

3

3

6

3

4

5

3

4

4

4

3

T/2 + 3

2

3

16

18

20

20

18

18

18

18

18

20

18

T/2 + 16

16

20

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

(6,10)

(6,10)

T

OF

Output Float for all outputs

3

22

ns

(6)

Synchronous Inputs (1,9,10)

T

IS

Input Setup

T

IS1

D31:0

T

IS2

BOFF

T

IS3

BTERM/READY

T

IS4

HOLD

5

19

9

9

ns

ns

ns

ns

T

IH

Input Hold

T

IH1

D31:0

T

IH2

BOFF

T

IH3

BTERM/READY

T

IH4

HOLD

5

7

2

5

ns

ns

ns

ns

background image

26

80960CA-33, -25, -16

Relative Output Timings (1,2,3,8)

T

AVSH1

A31:2 Valid to ADS Rising

T – 4

T + 4

ns

T

AVSH2

BE3:0, W/R, SUP, D/C, 

DMA, DACK3:0 Valid to ADS Rising

T – 6

T + 6

ns

T

AVEL1

A31:2 Valid to DEN Falling

T – 4

T + 4

ns

T

AVEL2

BE3:0, W/R, SUP, INST,

DMA, DACK3:0 Valid to DEN Falling

T – 6

T + 6

ns

T

NLQV

WAIT Falling to Output Data Valid

± 4

ns

T

DVNH

Output Data Valid to WAIT Rising

N*T – 4

N*T + 4

ns

(4)

T

NLNH

WAIT Falling to WAIT Rising

N*T ± 4

ns

(4)

T

NHQX

Output Data Hold after WAIT Rising

(N+1)*T–8

(N+1)*T+6

ns

(5)

T

EHTV

DT/R Hold after DEN High

T/2 – 7

ns

(6)

T

TVEL

DT/R Valid to DEN Falling

T/2 – 4

ns

Relative Input Timings (1,2,3)

T

IS5

RESET Input Setup (2-x Clock Mode)

8

ns

(13)

T

IH5

RESET Input Hold (2-x Clock Mode)

7

ns

(13)

T

IS6

DREQ3:0 Input Setup

14

ns

(7)

T

IH6

DREQ3:0 Input Hold

9

ns

(7)

T

IS7

XINT7:0, NMI Input Setup

9

ns

(15)

T

IH7

XINT7:0, NMI Input Hold

5

ns

(15)

T

IS8

RESET Input Setup (1-x Clock Mode)

3

ns

(14)

T

IH8

RESET Input Hold (1-x Clock Mode)

T/4 + 1

ns

(14)

NOTES:

1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.

2. See Figure 16 for capacitive derating information for output delays and hold times.

3. See Figure 17 for capacitive derating information for rise and fall times.

4. Where N is the number of N

RAD

, N

RDD

, N

WAD

 or N

WDD

 wait states that are programmed in the Bus Controller Region Table. WAIT never goes 

active when there are no wait states in an access.

5. N = Number of wait states inserted with READY.

6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.

7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for 

proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asyn-

chronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor.

8. These specifications are guaranteed by the processor.

9. These specifications must be met by the system for proper operation of the processor.

10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for 

PCLK2:1 loading.

11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in 

reset, the input clock may stop even in 1-x mode.

12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adja-

cent cycles.

13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee 

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the 

CLKIN. (See Figure 22.)

14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee 

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN. 

(See Figure 23.)

15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins 

are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when assert-

ing them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecu-

tive PCLK2:1 rising edges.

Table 17.  80960CA AC Characteristics (25 MHz) (Continued)

(80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test 

Conditions.)

Symbol

Parameter

Min

Max

Units

Notes

background image

27

80960CA-33, -25, -16

Table 18.  80960CA AC Characteristics (16 MHz)

(80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.)

Symbol

Parameter

Min

Max

Units

Notes

Input Clock (1,9)

T

F

CLKIN Frequency

0

32

MHz

T

C

CLKIN Period

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

62.5

31.25

125

ns

ns

(11)

T

CS

CLKIN Period Stability

In 1-x Mode (f

CLK1x

)

±0.1%

(12)

T

CH

CLKIN High Time

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

10

10

62.5

ns

ns

(11)

T

CL

CLKIN Low Time

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

10

10

62.5

ns

ns

(11)

T

CR

CLKIN Rise Time

0

6

ns

T

CF

CLKIN Fall Time

0

6

ns

Output Clocks (1,8)

T

CP

CLKIN to PCLK2:1 Delay

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

– 2

2

2

25

ns

ns

(3,12)

(3)

T

PCLK2:1 Period

In 1-x Mode (f

CLK1x

)

In 2-x Mode (f

CLK2x

)

T

C

2T

C

ns

ns

(12)

(3)

T

PH

PCLK2:1 High Time

(T/2) – 4

T/2

ns

(12)

T

PL

PCLK2:1 Low Time

(T/2) – 4

T/2

ns

(12)

T

PR

PCLK2:1 Rise Time

1

4

ns

(3)

T

PF

PCLK2:1 Fall Time

1

4

ns

(3)

Synchronous Outputs (8)

T

OH

T

OV

Output Valid Delay, Output Hold

T

OH1

, T

OV1

A31:2

T

OH2

, T

OV2

BE3:0

T

OH3

, T

OV3

ADS

T

OH4

, T

OV4

W/R

T

OH5

, T

OV5

D/C, SUP, DMA

T

OH6

, T

OV6

BLAST, WAIT

T

OH7

, T

OV7

DEN

T

OH8

, T

OV8

HOLDA, BREQ

T

OH9

, T

OV9

LOCK

T

OH10

, T

OV10

DACK3:0

T

OH11

, T

OV11

D31:0

T

OH12

, T

OV12

DT/R

T

OH13

, T

OV13

FAIL

T

OH14

, T

OV14

EOP3:0/TC3:0

3

3

6

3

4

5

3

4

4

4

3

T/2 + 3

2

3

18

20

22

22

20

20

20

20

20

22

20

T/2 + 18

18

22

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

(6,10)

(6,10)

T

OF

Output Float for all outputs

3

22

ns

(6)

Synchronous Inputs (1,9,10)

T

IS

Input Setup

T

IS1

D31:0

T

IS2

BOFF

T

IS3

BTERM/READY

T

IS4

HOLD

5

21

9

9

ns

ns

ns

ns

T

IH

Input Hold

T

IH1

D31:0

T

IH2

BOFF

T

IH3

BTERM/READY

T

IH4

HOLD

5

7

2

5

ns

ns

ns

ns

background image

28

80960CA-33, -25, -16

Relative Output Timings (1,2,3,8)

T

AVSH1

A31:2 Valid to ADS Rising

T – 4

T + 4

ns

T

AVSH2

BE3:0, W/R, SUP, D/C, 

DMA, DACK3:0 Valid to ADS Rising

T – 6

T + 6

ns

T

AVEL1

A31:2 Valid to DEN Falling

T – 6

T + 6

ns

T

AVEL2

BE3:0, W/R, SUP, INST,

DMA, DACK3:0 Valid to DEN Falling

T – 6

T + 6

ns

T

NLQV

WAIT Falling to Output Data Valid

± 4

ns

T

DVNH

Output Data Valid to WAIT Rising

N*T – 4

N*T + 4

ns

(4)

T

NLNH

WAIT Falling to WAIT Rising

N*T ± 4

ns

(4)

T

NHQX

Output Data Hold after WAIT Rising

(N+1)*T–8

(N+1)*T+6

ns

(5)

T

EHTV

DT/R Hold after DEN High

T/2 – 7

ns

(6)

T

TVEL

DT/R Valid to DEN Falling

T/2 – 4

ns

Relative Input Timings (1,2,3)

T

IS5

RESET Input Setup (2-x Clock Mode)

10

ns

(13)

T

IH5

RESET Input Hold (2-x Clock Mode)

9

ns

(13)

T

IS6

DREQ3:0 Input Setup

16

ns

(7)

T

IH6

DREQ3:0 Input Hold

11

ns

(7)

T

IS7

XINT7:0, NMI Input Setup

9

ns

(15)

T

IH7

XINT7:0, NMI Input Hold

5

ns

(15)

T

IS8

RESET Input Setup (1-x Clock Mode)

3

ns

(14)

T

IH8

RESET Input Hold (1-x Clock Mode)

T/4 + 1

ns

(14)

NOTES:

1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.

2. See Figure 16 for capacitive derating information for output delays and hold times.

3. See Figure 17 for capacitive derating information for rise and fall times.

4. Where N is the number of N

RAD

, N

RDD

, N

WAD

 or N

WDD

 wait states that are programmed in the Bus Controller Region Table. WAIT never goes 

active when there are no wait states in an access.

5. N = Number of wait states inserted with READY.

6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.

7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for 

proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asyn-

chronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor.

8. These specifications are guaranteed by the processor.

9. These specifications must be met by the system for proper operation of the processor.

10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for 

PCLK2:1 loading.

11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in 

reset, the input clock may stop even in 1-x mode.

12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adja-

cent cycles.

13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee 

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. 

(See Figure 22.)

14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee 

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN. 

(See Figure 23.)

15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins are 

sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when asserting 

them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive 

PCLK2:1 rising edges.

Table 18.  80960CA AC Characteristics (16 MHz) (Continued)

(80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.)

Symbol

Parameter

Min

Max

Units

Notes

background image

29

80960CA-33, -25, -16

4.5.1

AC Test Conditions

The AC Specifications in Section 4.5 are tested with

the 50 pF load shown in Figure 7. Figure 16 shows

how timings vary with load capacitance.

Specifications are measured at the 1.5V crossing

point, unless otherwise indicated. Input waveforms

are assumed to have a rise and fall time of

2 ns

from 0.8V to 2.0V. See Section 4.5.2, AC Timing

Waveforms for AC spec definitions, test points and

illustrations.

Figure 7.  AC Test Load

Output Pin

C

L

 = 50 pF for all signals

C

L

F_CX008A

4.5.2

AC Timing Waveforms

Figure 8.  Input and Output Clocks Waveform

Figure 9.  CLKIN Waveform

PCLK2:1

2.4V

1.5V

1.5V

1.5V

0.45V

T

CP

T

PH

T

PL

T

PR

T

PF

T

F_CX009A

CLKIN

2.0V

1.5V

0.8V

TCF

TCH

TCL

TC

TCR

F_CX010A

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30

80960CA-33, -25, -16

Figure 10.  Output Delay and Float Waveform

Figure 11.  Input Setup and Hold Waveform

PCLK2:1

Outputs

1.5V

1.5V

T

OV

Min

Max

T

OH

Min

Max

T

OF

1.5V

1.5V

1.5V

1.5V

Outputs

F_CX011A

PCLK2:1

Inputs:

1.5V

1.5V

1.5V

Valid

T

IS

T

IH

(READY, HOLD, BTERM,

BOFF, DREQ3:0,

D31:0 on reads)

F_CX012A

Min

Max

T

OV

 T

OH

 - OUTPUT DELAY - The maximum output delay is referred to

as the Output Valid Delay (T

OV

). The minimum output delay is 

referred to as the Output Hold (T

OH

).

T

OF

- OUTPUT FLOAT DELAY - The output float condition occurs

when the maximum output current becomes less that I

LO

 in magnitude.

T

IS

 T

IH

- INPUT SETUP AND HOLD - The input setup and hold requirements

specify the sampling window during which synchronous inputs must be

stable for correct processor operation.

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31

80960CA-33, -25, -16

Figure 12.  NMI, XINT7:0 Input Setup and Hold Waveform

Figure 13.  Hold Acknowledge Timings

PCLK2:1

1.5V

1.5V

1.5V

Valid

T

IS

T

IH

NMI, XINT7:0

Min

Min

F_CX013A

1.5V

1.5V

PCLK2:1

1.5V

1.5V

1.5V

Outputs:

A31:2, D31:0, BE3:0,

ADS, BLAST, WAIT, W/R,

DT/R, DEN, LOCK,

D/C, SUP, DMA

Min

Max

Min

Max

Valid

1.5V Valid

T

OF

T

OV

HOLD

T

IS

T

IH

1.5V

1.5V

1.5V

T

IH

T

IS

HOLDA

T

OV

Min

Min

Min

Min

T

OV

Max

Min

Max

Min

T

OV

 T

OH

 - OUTPUT DELAY - The maximum output delay is referred to

as the Output Valid Delay (T

OV

). The minimum output delay is 

referred to as the Output Hold (T

OH

).

T

OF

- OUTPUT FLOAT DELAY - The output float condition occurs

when the maximum output current becomes less that I

LO

 in magnitude.

T

IS

 T

IH

- INPUT SETUP AND HOLD - The input setup and hold requirements

specify the sampling window during which synchronous inputs must be

stable for correct processor operation.

F_CX014A

1.5V

1.5V

1.5V

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32

80960CA-33, -25, -16

Figure 14.  Bus Backoff (BOFF) Timings

PCLK2:1

1.5V

1.5V

1.5V

Outputs:

A31:2, D31:0, BE3:0,

ADS, BLAST, WAIT, W/R,

DT/R, DEN, LOCK,

D/C, SUP, DMA

Min

Max

Min

Max

Valid

1.5V Valid

T

OF

T

OV

BOFF

T

IS

T

IH

1.5V

1.5V

1.5V

T

IH

T

IS

F_CX015A

1.5V

1.5V

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33

80960CA-33, -25, -16

Figure 15.  Relative Timings Waveforms

4.5.3

Derating Curves

Figure 16.  Output Delay or Hold vs. Load Capacitance

PCLK2:1

1.5V

1.5V

1.5V

1.5V

1.5V

1.5V

1.5V

1.5V

1.5V

1.5V

1.5V

1.5V

1.5V

T

AVSH

T

DVHN

T

NHQX

T

NLNH

T

AVEL

T

VEL

T

EHTV

T

NLQV

ADS

A31:2, BE3:0,

W/R, LOCK,

SUP, D/C, DMA

D31:0

WAIT

DT/R

DEN

D31:0

F_CX016A

1.5V

In

V

IH

V

IL

Out

50

100

150

C

L

(pF)

nom + 10

nom + 5

nom

All outputs except: LOCK, 

EOP3:0/TC3:0, FAIL

F_CX017A

DMA, SUP, BREQ, DACK3:0,

Note: PCLK Load = 50pF

O

u

tp

u

t

V

a

lid

D

e

la

y

s

(n

s

)

@

1

.5

V

LOCK, DMA, SUP, BREQ,

DACK3:0, EOP3:0/TC3:0, FAIL

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34

80960CA-33, -25, -16

Figure 17.  Rise and Fall Time Derating at Highest Operating Temperature and Minimum V

CC

Figure 18.  I

CC

 vs. Frequency and Temperature

50

100

150

T

im

e

(n

s

)

C

L

(pF)

10

8

6

4

2

50

100

150

T

im

e

(n

s

)

C

L

(pF)

10

8

6

4

2

a) All outputs except: LOCK, DMA, SUP, HOLDA, BREQ

DACK3:0, EOP3:0/TC3:0, FAIL

b) LOCK, DMA, SUP, HOLDA, BREQ, DACK3:0,

EOP3:0/TC3:0, FAIL

0.8V to 2.0V

0.8V to 2.0V

F_CX019A

900

0

0

33

T

C

 = 100° C

T

C

 = 0° C

f

PCLK

 (MHz)

I

C

C

(m

A

)

I

CC

 - I

CC

 under test conditions

F_CX020A

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35

80960CA-33, -25, -16

5.0

RESET, BACKOFF AND HOLD 

ACKNOWLEDGE

Table 19 lists the condition of each processor output

pin while RESET is asserted (low).

Table 19.  Reset Conditions

Pins

State During Reset

(HOLDA inactive)

1

A31:2

Floating

D31:0

Floating

BE3:0

Driven high (Inactive)

W/R

Driven low (Read)

ADS

Driven high (Inactive)

WAIT

Driven high (Inactive)

BLAST

Driven low (Active)

DT/R

Driven low (Receive)

DEN

Driven high (Inactive)

LOCK

Driven high (Inactive)

BREQ

Driven low (Inactive)

D/C

Floating

DMA

Floating

SUP

Floating

FAIL

Driven low (Active)

DACK3:0

Driven high (Inactive)

EOP3:0/TC3:0

Floating (Set to input mode)

NOTES:

1. With regard to bus output pin state only, the Hold

Acknowledge state takes precedence over the reset

state. Although asserting the RESET pin will internally

reset the processor, the processor’s bus output pins

will not enter the reset state if it has granted Hold

Acknowledge to a previous HOLD request (HOLDA is

active). Furthermore, the processor will grant new

HOLD requests and enter the Hold Acknowledge state

even while in reset.

For example, if HOLDA is inactive and the processor is

in the reset state, then HOLD is asserted, the proces-

sor’s bus pins enter the Hold Acknowledge state and

HOLDA is granted. The processor will not be able to

perform memory accesses until the HOLD request is

removed, even if the RESET pin is brought high. This

operation is provided to simplify boot-up synchroniza-

tion among multiple processors sharing the same bus.

Table 20 lists the condition of each processor output

pin while HOLDA is asserted (low).

Table 20.  Hold Acknowledge 

and Backoff Conditions

Pins

State During HOLDA

A31:2

Floating

D31:0

Floating

BE3:0

Floating

W/R

Floating

ADS

Floating

WAIT

Floating

BLAST

Floating

DT/R

Floating

DEN

Floating

LOCK

Floating

BREQ

Driven (High or low)

D/C

Floating

DMA

Floating

SUP

Floating

FAIL

Driven high (Inactive)

DACK3:0

Driven high (Inactive)

EOP3:0/TC3:0

Driven (If output)

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36

80960CA-33, -25, -16

6.0

BUS WAVEFORMS

Figure 19.  Cold Reset Waveform

C

L

K

IN

P

C

L

K

2

:1

A

D

S

,

W

/R

,

D

T

/R

,

IN

S

T

,

S

U

P

,

D

3

1

:0

,

S

T

E

S

T

R

E

S

E

T

V

C

C

-

O

N

C

E

B

L

A

S

T

L

O

C

K

,

W

A

IT

,

D

E

N

,

D

A

C

K

3

:0

B

R

E

Q

,

F

A

IL

D

M

A

,

A

3

1

:2

,

D

/C

,

B

E

3

:0

E

O

P

/T

C

3

:0

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

In

v

a

lid

V

a

lid

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

C

L

K

IN

a

n

d

V

C

C

S

ta

b

le

to

R

E

S

E

T

h

ig

h

,

3

2

C

L

K

IN

P

e

ri

o

d

s

in

2

x

M

o

d

e

,

p

e

ri

o

d

s

in

1

x

M

o

d

e

.

∼ ∼

In

p

u

ts

T

d

e

la

y

1

P

C

L

K

T

s

e

tu

p

1

P

C

L

K

T

h

o

ld

1

P

C

L

K

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

m

in

im

u

m

1

0

,0

0

0

C

L

K

IN

F

_

C

X

0

2

1

A

∼ ∼

∼ ∼

R

E

S

E

T

h

ig

h

to

F

ir

s

t

B

u

s

a

c

ti

v

it

y,

a

p

p

ro

x

im

a

te

ly

3

2

P

C

L

K

p

e

ri

o

d

s

.

V

C

C

a

n

d

C

L

K

IN

S

ta

b

le

to

O

u

tp

u

ts

V

a

lid

,

m

a

x

im

u

m

3

2

C

L

K

IN

P

e

ri

o

d

s

.

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37

80960CA-33, -25, -16

Figure 20.  Warm Reset Waveform

T

d

e

la

y

1

P

C

L

K

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

M

a

x

im

u

m

R

E

S

E

T

L

o

w

to

R

E

S

E

T

S

ta

te

4

P

C

L

K

P

e

ri

o

d

s

1

P

C

L

K

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

F

_

C

X

0

2

2

A

P

C

L

K

2

:1

A

D

S

,

W

/R

,

D

T

/R

,

S

U

P

,

D

3

1

:0

,

S

T

E

S

T

R

E

S

E

T

B

L

A

S

T

L

O

C

K

,

W

A

IT

,

D

E

N

,

D

A

C

K

3

:0

B

R

E

Q

,

F

A

IL

D

M

A

,

A

3

1

:2

,

D

/C

,

B

E

3

:0

E

O

P

/T

C

3

:0

V

a

li

d

∼ ∼

∼ ∼

T

h

o

ld

T

s

e

tu

p

1

P

C

L

K

R

E

S

E

T

H

ig

h

to

F

ir

s

t

B

u

s

A

c

ti

v

it

y,

A

p

p

ro

x

im

a

te

ly

3

2

P

C

L

K

P

e

ri

o

d

s

M

in

im

u

m

R

E

S

E

T

L

o

w

T

im

e

1

6

P

C

L

K

P

e

ri

o

d

s

∼ ∼

∼ ∼

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38

80960CA-33, -25, -16

Figure 21.  Entering the ONCE State

C

L

K

IN

P

C

L

K

2

:1

A

D

S

,

B

E

3

:0

,

A

3

1

:2

,

R

E

S

E

T

O

N

C

E

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

V

C

C

a

n

d

C

L

K

IN

S

ta

b

le

to

O

u

tp

u

ts

V

a

lid

,

m

a

x

im

u

m

3

2

C

L

K

IN

P

e

ri

o

d

s

.

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

C

L

K

IN

a

n

d

V

C

C

S

ta

b

le

a

n

d

R

E

S

E

T

lo

w

a

n

d

O

N

C

E

lo

w

to

R

E

S

E

T

h

ig

h

,

m

in

im

u

m

3

2

C

L

K

IN

P

e

ri

o

d

s

in

2

x

M

o

d

e

,

1

0

,0

0

0

C

L

K

IN

P

e

ri

o

d

s

in

1

x

M

o

d

e

.

∼ ∼

D

3

1

:0

,

L

O

C

K

,

W

A

IT

,

B

L

A

S

T

,W

/R

,

D

/C

,

D

E

N

,

D

T

/R

,

H

O

L

D

,

H

O

L

D

A

,

D

M

A

,

E

O

P

3

:0

/T

C

3

:0

,

S

T

E

S

T

,

X

IN

T

7

:0

,

N

M

I,

D

A

C

K

3

:0

,

D

R

E

Q

3

:0

R

E

A

D

Y

,

B

T

E

R

M

B

L

A

S

T

,

F

A

IL

,

S

U

P

,B

R

E

Q

,

∼ ∼∼∼

∼ ∼∼∼

M

a

x

im

u

m

3

2

C

L

K

IN

P

e

ri

o

d

s

R

e

q

u

ir

e

d

a

ft

e

r

O

N

C

E

M

o

d

e

e

n

te

re

d

V

C

C

∼ ∼

∼ ∼∼∼

∼ ∼

F

_

C

X

0

2

3

A

∼ ∼

C

L

K

IN

m

a

y

n

o

t

fl

o

a

t.

It

m

u

s

t

b

e

d

ri

v

e

n

h

ig

h

o

r

lo

w

o

r

c

o

n

ti

n

u

e

to

ru

n

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39

80960CA-33, -25, -16

Figure 22.  Clock Synchronization in the 2-x Clock Mode

Figure 23.  Clock Synchronization in the 1-x Clock Mode

CLKIN

RESET

PCLK2:1

(Case 1)

PCLK2:1

(Case 2)

1.5V

TIH

TIS

1.5V

1.5V

1.5V

1.5V

1.5V

TCP

Max

Min

TCP

Max

Min

TCP

SYNC

Note: Case 1 and Case 2 show two possible polarities of PCLK2:1

Min

1.5V

1.5V

1.5V

1.5V

1.5V

1.5V

F_CX024A

Max

CLKIN

1.5V

1.5V

RESET

TIH

TIS

1.5V

2x CLK

Note: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2xCLK. 2xCLK is an internal signal

generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising

edge of CLKIN. The RESET pin is sampled when PCLK is high.

F_CX025A

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40

80960CA-33, -25, -16

Figure 24.  Non-Burst, Non-Pipelined Requests Without Wait States

In

ADS

A31:4, SUP

,

DMA, D/C,

BE3:0, LOCK

W

/

R

BLAST

DT

/

R

DEN

A3:2

WAIT

D31:0

PCLK

A

D

A

D

A

D

In

Valid

Valid

Valid

Valid

Valid

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

0

00

X

xx

X

xx

0

00000

X

xx

0

00000

OFF

0

Disabled

0

0

0..0

Disabled

0

Valid

F_CX026A

Out

Function

Bit

Value

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41

80960CA-33, -25, -16

Figure 25.  Non-Burst, Non-Pipelined Read Request With Wait States

ADS

A31:2, BE3:0

DMA, D/C,

SUP, LOCK

W/R

BLAST

DT/R

DEN

WAIT

D31:0

PCLK

A

3

2

1

D

1

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

1

01

X

xx

X

xx

X

xxxxx

X

xx

3

00011

OFF

0

Disabled

0

0

0..0

Disabled

0

In

Function

Bit

Value

Valid

Valid

A

F_CX027A

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42

80960CA-33, -25, -16

Figure 26.  Non-Burst, Non-Pipelined Write Request With Wait States

ADS

A31:2,

W/R

BLAST

DT/R

DEN

SUP, DMA,

WAIT

D31:0

PCLK

A

3

2

1

D

1

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

1

01

X

xx

X

xx

3

00011

X

xx

X

xxxxxx

OFF

0

Disabled

0

0

0..0

Disabled

0

Out

A

Function

Bit

Value

Valid

Valid

D/C, LOCK

F_CX028A

BE3:0

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43

80960CA-33, -25, -16

Figure 27.  Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus

In0

ADS

A31:4, SUP,

DMA, D/C,

BE3:0, LOCK

W

/

R

BLAST

DT

/

R

DEN

A3:2

WAIT

D31:0

PCLK

A

D

D

D

D

A

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

0

00

32-Bit

10

X

xx

X

xxxxx

0

00

0

00000

OFF

0

Enabled

1

0

0..0

Disabled

0

F_CX029A

Function

Bit

Value

In3

In2

In1

Valid

00

01

10

11

background image

44

80960CA-33, -25, -16

Figure 28.  Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

BE3:0, LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

1

01

32-bit

10

X

xx

X

xxxxx

1

01

2

00010

OFF

0

Enabled

1

0

0..0

Disabled

0

A

2

1

D

1

D

1

D

1

D

1

A

In1

In2

In3

In0

Valid

00

11

01

10

Function

Bit

Value

F_CX030A

background image

45

80960CA-33, -25, -16

Figure 29.  Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

0

00

32-bit

10

0

00

0

00000

X

xx

X

xxxxx

OFF

0

Enabled

1

0

0..0

Disabled

0

ADS

A31:4, SUP

,

DMA, D/C,

BE3:0, LOCK

W

/

R

BLAST

DT

/

R

DEN

A3:2

WAIT

D31:0

PCLK

A

D

D

D

D

A

Function

Bit

Value

00

01

10

11

Out0

Valid

Out3

Out2

Out1

F_CX031A

background image

46

80960CA-33, -25, -16

Figure 30.  Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

BE3:0, LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

1

01

32-bit

10

1

01

2

00010

X

xx

X

xxxxx

OFF

0

Enabled

1

0

0..0

Disabled

0

A

2

1

D

1

D

1

D

1

D

1

A

Out0

Valid

00

11

01

10

Function

Bit

Value

Out1

Out2

Out3

F_CX032A

background image

47

80960CA-33, -25, -16

Figure 31.  Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus

ADS

SUP, DMA,

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

1

01

16-bit

01

X

xx

X

xxxxx

1

01

2

00010

OFF

0

Enabled

1

0

0..0

Disabled

0

A

2

1

D

1

D

1

D

1

D

1

A

Function

Bit

Value

Valid

A3:2 = 00 or 10

A3:2 = 01 or 11

D15:0

A1=0

D15:0

A1=1

D15:0

A1=0

D15:0

A1=1

D/C, LOCK,

A31:4, BE3/BHE,

BE1/A1

BE0/BLE

F_CX033A

background image

48

80960CA-33, -25, -16

Figure 32.  Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus

ADS

SUP, DMA,

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

1

01

8-bit

00

X

xx

X

xxxxx

1

01

2

00010

OFF

0

Enabled

1

0

0..0

Disabled

0

A

2

1

D

1

D

1

D

1

D

1

A

Function

Bit

Value

Valid

A3:2 = 00, 01, 10 or 11

D7:0

Byte 0

D7:0

Byte 1

D7:0

Byte 2

D7:0

Byte 3

D/C, LOCK,

A31:4

BE1/A1,

A1:0 = 00

A1:0 = 01 

A1:0 = 10

A1:0 =11

BE0/A0

F_CX034A

background image

49

80960CA-33, -25, -16

Figure 33.  Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus

Non-Pipelined Request Concludes

Pipelined Reads Begin.

Pipelined Reads Conclude,

Non-Pipelined Requests Begin.

ADS

A31:4, SUP,

DMA, D/C,

LOCK

BLAST

WAIT

D31:0

PCLK

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

X

xx

X

xx

X

xx

X

xxxxx

X

xx

0

00000

ON

1

Disabled

0

0

0..0

X

x

Function

Bit

Value

IN

D

IN

D'

IN

D''

IN

D'''

IN

D''''

A

A'

D

A''

D'

A'''

D''

A''''

D'''

D''''

Valid

Valid

Valid

Valid

Valid

Invalid

Invalid

DT/R

DEN

A3:2

BE3:0

Valid

Valid

Valid

Valid

Valid

Invalid

W/R

F_CX035A

background image

50

80960CA-33, -25, -16

Figure 34.  Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus

Non-Pipelined Request Concludes

Pipelined Reads Begin.

Pipelined Reads Conclude,

Non-Pipelined Requests Begin.

ADS

A31:4, SUP,

DMA, D/C,

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

BE3:0

A

1

A'

D

1

D'

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

X

xx

X

xx

X

xx

X

xxxxx

X

xx

1

00001

ON

1

Disabled

1

0

0..0

X

x

IN

D'

Invalid

Valid

Valid

Invalid

IN

D

LOCK

Valid

Valid

Invalid

Function

Bit

Value

F_CX036A

background image

51

80960CA-33, -25, -16

Figure 35.  Burst, Pipelined Read Request Without Wait States, 32-Bit Bus

Pipelined Reads

Conclude, Non-Pipelined 

Requests Begin

ADS

A31:4, SUP,

DMA, D/C,

BE3:0, LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

Non-pipelined Request 

Concludes, Pipelined 

Reads Begin

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

X

xx

32-bit

10

X

xx

X

xxxxx

0

00

0

00000

ON

1

Enabled

1

0

0..0

Disabled

0

A

D

D

D

A'

D'

D'

Valid

Valid

In-

Valid

Valid

01

10

11

00

IN

D

IN

D

IN

D

IN

D

IN

D

IN

D

Valid

D

Function

Bit

Value

In-

Valid

In-

Valid

F_CX037A

background image

52

80960CA-33, -25, -16

Figure 36.  Burst, Pipelined Read Request With Wait States, 32-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

BE3:0, LOCK

W/R

A3:2

D31:0

WAIT

BLAST

DT/R

DEN

PCLK

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

X

xx

32-bit

10

X

xx

X

xxxxx

1

01

2

00010

ON

1

Enabled

1

0

0..0

Disabled

0

Function

Bit

Value

IN

D

IN

D

IN

D

IN

D

IN

D'

A

2

1

D

1

D

1

D

1

A'

2

1

Valid

D

D'

Valid

In-

valid

In-

valid

00

01

10

11

Valid

In-

valid

Non-pipelined request concludes,

pipelined reads begin.

Pipelined reads conclude,

Non-pipelined requests begin.

F_CX038A

background image

53

80960CA-33, -25, -16

Figure 37.  Burst, Pipelined Read Request With Wait States, 16-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

BE0/BLE, 

W/R

A3:2

BE1/A1

WAIT

BLAST

DT/R

DEN

PCLK

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

X

xx

16-bit

10

X

xx

X

xxxxx

1

01

2

00010

ON

1

Enabled

1

0

0..0

Disabled

0

Function

Bit

Value

D15:0

A1=0

D15:0

A1=1

D15:0

A1=0

D15:0

A1=1

D15:0

D'

A

2

1

D

1

D

1

D

1

A'

2

1

D

D'

In-

valid

Non-pipelined request concludes,

pipelined reads begin.

Pipelined reads conclude,

Non-pipelined requests begin.

A3:2 = 00 or 10

A3:2 = 01 or 11

Valid

In-

valid

Valid

In-

valid

BE3/BHE,

D31:0

F_CX040A

LOCK

Valid

Valid

In-

valid

background image

54

80960CA-33, -25, -16

Figure 38.  Burst, Pipelined Read Request With Wait States, 8-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

LOCK

W/R

A3:2

BE1/A1,

WAIT

BLAST

DT/R

DEN

PCLK

re

s

e

rv

e

d

Byte 

Order

Bus

Width

N

WDD

N

WAD

N

XDA

N

RDD

N

RAD

Pipe-

Lining

External

Ready

Control

Burst

re

s

e

rv

e

d

31-23

22

18-17

21

20-19

16-12

7-3

11-10

9-8

2

1

0

X

x

0

0

X

xx

8-bit

10

X

xx

X

xxxxx

1

01

2

00010

ON

1

Enabled

1

0

0..0

Disabled

0

Function

Bit

Value

D7:0

Byte 0

D7:0

Byte 1

D7:0

Byte 2

D7:0

Byte 3

D7:0

D'

A

2

1

D

1

D

1

D

1

A'

2

1

D

D'

In-

valid

Non-pipelined request concludes,

pipelined reads begin.

Pipelined reads conclude,

Non-pipelined requests begin.

Valid

In-

valid

BE0/A0

D31:0

A3:2 = 00, 01, 10, or 11

Valid

In-

valid

A1:0 = 00

A1:0 = 01

A1:0 = 10

A1:0 = 11

Valid

Valid

In-

valid

F_CX039A

background image

55

80960CA-33, -25, -16

Figure 39.  Using External READY

PCLK

ADS

A31:4, SUP,

DT/R

DEN

READY

W/R

DMA, INST,

BLAST

BTERM

A3:2

WAIT

D31:0

D/C, BE3:0,

LOCK

D0

D1

D2

D3

D0

D1

D2

D3

00

01

10

11

00

01

10

11

Valid

Valid

Quad-Word Read Request

N

RAD

 = 0, N

RDD

 = 0, N

XDA

 = 0

Ready Enabled

Quad-Word Write Request

N

WAD

 = 1, N

WDD

 = 0, N

WDA

 = 0

Ready Enabled

F_CX041A

background image

56

80960CA-33, -25, -16

Figure 40.  Terminating a Burst with BTERM

PCLK

ADS

A31:4, SUP,

DT/R

DEN

READY

W/R

DMA, INST,

BLAST

BTERM

A3:2

WAIT

D31:0

D/C, BE3:0,

LOCK

D0

D1

D2

D3

Valid

Quad-Word Write Request

N

WAD

 = 0, N

WDD

 = 0, N

WDA

= 0

Ready Enabled

00

01

10

11

Note: READY adds memory access time to data transfers, whether or not the

bus access is a burst access. BTERM interrupts a bus access, whether or not

the bus access has more data transfers pending. Either the READY signal or

the BTERM signal will terminate a bus access if the signal is asserted during

the last (or only) data transfer of the bus access.

See Note

F_CX042A

background image

57

80960CA-33, -25, -16

Figure 41.  BOFF Functional Timing

ADS

BLAST

READY

BOFF

A31:2, SUP,

D31:0,

BOFF may not

be asserted

BOFF may not

be asserted

BOFF May be asserted to suspend request

Begin Request

End Request

SUSPEND REQUEST

NON-BURST

Regenerate ADS

DMA, D/C,

BE3:0, WAIT,

DEN, DT/R

(WRITES)

BURST

MAY CHANGE

RESUME REQUEST

BURST

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

Note: READY/BTERM  must be enabled; N

RAD

,  N

RDD

, N

WAD

, N

WDD

= 0

∼ ∼

∼ ∼

F_CX043A

background image

58

80960CA-33, -25, -16

Figure 42.  HOLD Functional Timing

Word Read Request

N

RAD

=1, N

XDA

=1

Word Read

Request

N

RAD

=0,

N

XDA

=0

Hold State

Hold State

PCLK2:1

ADS

A31:2, SUP,

DMA, D/C,

BE3:0, WAIT,

DEN, DT/R

BLAST

HOLD

HOLDA

Valid

Valid

F_CX044A

background image

59

80960CA-33, -25, -16

Figure 43.  DREQ and DACK Functional Timing

Figure 44.  EOP Functional Timing

PCLK2:1

ADS

! (BLAST

& READY

DACKx

(All Modes)

DREQx

(Case 1)

DREQx

(Case 2)

Note: 

F_CX018A

& !WAIT)

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

∼ ∼

High To Prevent 

Next Bus Cycle

High To Prevent 

Next Bus Cycle

System

Clock

Start DMA

Bus Request

End of DMA

Bus Request

DMA 

Acknowledge

DMA 

Request

t

IS5

t

IH5

t

IS5

t

IH5

(See Note)

1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-By and some packing and 

unpacking modes in which loads are followed by loads or stores are followed by stores.

2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high.

Applications are non Fly-By transfers and adjacent load-stores or store-loads.

3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus

accesses (defined by ADS and BLAST. Refer to i960

®

 Cx Microprocessor User’s Manual for “access”,

“request” definitions.

∼ ∼

∼ ∼

PCLK2:1

EOP

F_CX045A

∼ ∼

∼ ∼

∼ ∼

Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge

held for a minimum of 2 clock cycles then deasserted within 15 clock cycles.

triggered. EOP must be

15 CLKs Max

2 CLKs Min

background image

60

80960CA-33, -25, -16

Figure 45.  Terminal Count Functional Timing

Figure 46.  FAIL Functional Timing

Note: Terminal Count becomes active during the last bus request of a buffer transfer. If the

last LOAD/STORE bus request is executed as multiple bus accesses, the TC will be active 

for the entire bus request. Refer to the i960

®

 Cx Microprocessor User’s Manual for 

further information.

PCLK2

DREQ

ADS

DACK

TC

F_CX046A

RESET

FAIL

~65,000 Cycles

5 Cycles

102 Cycles

(Bus Test)

Pass

(Internal Self-Test)

Pass

∼ ∼

∼ ∼

∼ ∼

∼ ∼

Fail

Fail

F_CX047A

background image

61

80960CA-33, -25, -16

Figure 47.  A Summary of Aligned and Unaligned Transfers for Little Endian Regions

0

4

8

12

16

20

24

0

1

2

3

4

5

6

One Double-Word 

Short-Word

Load/Store

Word

Load/Store

Double-Word

Load/Store

Byte, Byte Requests

Short Request (Aligned)

Short Request (Aligned)

Byte, Byte Requests

Word Request (Aligned)

Byte, Short, Byte, Requests

Short, Short Requests

Byte, Short, Byte Requests

Byte Offset

Word Offset

F_CX048A

One Double-Word Burst (Aligned)

Byte, Short, Word, Byte Requests

Short, Word, Short Requests

Byte, Word, Short, Byte Requests

Word, Word Requests

Request (Aligned)

background image

62

80960CA-33, -25, -16

Figure 48.  A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued)

0

4

8

12

16

20

24

0

1

2

3

4

5

6

Triple-Word

Load/Store

Quad-Word

Load/Store

Word, Word, 

Word Requests

Requests

Double-

Double- 

Word, Word, Word,

Word Requests

Byte Offset

Word Offset

One Three-Word

 Request (Aligned)

Byte, Short, Word,

 Word, Byte Requests

 Short Requests

Short, Word, Word,

Byte, Word, Word,

Short, Byte Requests

Word, Word, 

Word Requests

One Four-Word

Request (Aligned)

Byte, Short, Word, Word,

Word, Byte Requests

Short, Word, Word, Word,

Short Requests

Byte, Word, Word, Word, 

Short, Byte Requests

F_CX049A

Requests

Word, 

Word 

Word, 

Word,

Word,

background image

63

80960CA-33, -25, -16

Figure 49.  Idle Bus Operation

PCLK

ADS

A31:4, SUP,

DMA, INST,

D/C, BE3:0

LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

READY,

BTERM

Write Request

N

WAD

=2, N

XDA

 = 0

Ready Disabled

Idle Bus

(not in Hold Acknowledge state)

Read Request

N

WAD

=2, N

XDA

 = 0

Ready Disabled

In

Out

Valid

Valid

Valid

Valid

Valid

Valid

F_CX050A

background image

64

80960CA-33, -25, -16

7.0

REVISION HISTORY

This data sheet supersedes data sheet 270727-005. Specification changes in the 80960CA data sheet are a

result of design changes. The sections significantly changed since the previous revision are:

Section

Last 

Rev.

Description

Table 11. 80960CA PGA Package Thermal 

Characteristics

-005

Removed references and notes pertaining to 

θ

J-CAP

 and

θ

J-PIN.

Table 12. 80960CA PQFP package Thermal 

Characteristics

-005

Removed references and notes pertaining to

θ

JL

and

θ

JB.

3.3 80960CA Mechanical Data

-005

Removed section containing information on 

Package Dimensions. Moved section header to 

encompass Pinout tables and diagrams.

3.7 Suggested Sources for 80960CA 

Accessories

-005

Removed entire section containing information 

about 80960CA accessories.

Tables 16, 17 and18 80960CA AC Charac-

teristics (33-, 25- and 16MHz, respectively)

-005

T

TVEL

 maximum deleted.

T

NHQX

 and T

EHTV

 minimums changed:

WAS:

IS:

T

NHQX

(N+1)*T-6

(N+1)*T-8

T

EHTV

T/2 - 6

T/2 - 7

All

-005

All timing diagrams and waveforms have been 

redrawn to conform to consistent format.

Data sheet formatting has been changed to 

conform to corporate standards. Specific 

formatting changes are not itemized in this revision 

history.