background image

SN54HC161, SN74HC161

4-BIT SYNCHRONOUS BINARY COUNTERS

 

 

SCLS297A – JANUARY 1996 – REVISED MAY 1997

1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

D

Internal Look-Ahead for Fast Counting

D

Carry Output for n-Bit Cascading

D

Synchronous Counting

D

Synchronously Programmable

D

Package Options Include Plastic

Small-Outline (D) and Ceramic Flat (W)

Packages, Ceramic Chip Carriers (FK), and

Standard Plastic (N) and Ceramic (J)

300-mil DIPs

description

These synchronous, presettable counters feature

an internal carry look-ahead for application in

high-speed counting designs. The ’HC161 are

4-bit binary counters. Synchronous operation is

provided by having all flip-flops clocked

simultaneously so that the outputs change

coincident with each other when so instructed by

the count-enable (ENP, ENT) inputs and internal

gating. This mode of operation eliminates the

output counting spikes that are normally

associated with synchronous (ripple-clock)

counters. A buffered clock (CLK) input triggers the

four flip-flops on the rising (positive-going) edge of

the clock waveform.

These counters are fully programmable; that is,

they can be preset to any number between 0 and

9 or 15. As presetting is synchronous, setting up

a low level at the load input disables the counter

and causes the outputs to agree with the setup

data after the next clock pulse, regardless of the

levels of the enable inputs.

The clear function for the ’HC161 is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop

outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without

additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).

Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a

high-level pulse while the count is maximum (9 or 15 with Q

A

 high). This high-level overflow ripple-carry pulse

can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the

level of CLK.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that

modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of

the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the

stable setup and hold times.

The SN54HC161 is characterized for operation over the full military temperature range of –55

°

C to 125

°

C. The

SN74HC161 is characterized for operation from –40

°

C to 85

°

C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54HC161 . . . J  OR  W  PACKAGE

SN74HC161 . . . D OR N PACKAGE

(TOP VIEW)

3

2

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

Q

A

Q

B

NC

Q

C

Q

D

A

B

NC

C

D

SN54HC161 . . . FK PACKAGE

(TOP VIEW)

CLK

CLR

NC

LOAD

ENT

RCO

ENP

GND

NC

V

CC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CLR

CLK

A

B

C

D

ENP

GND

V

CC

RCO

Q

A

Q

B

Q

C

Q

D

ENT

LOAD

NC – No internal connection

 

Copyright 

©

 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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SN54HC161, SN74HC161

4-BIT SYNCHRONOUS BINARY COUNTERS

 

 

SCLS297A – JANUARY 1996 – REVISED MAY 1997

2

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logic symbol

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, N, and W packages.

14

13

12

11

CTRDIV16

LOAD

1,5D

3

A

4

B

5

C

6

D

CT=0

1

M2

M1

9

C5/2,3,4+

G3

10

ENT

RCO

15

3CT=15

QA

QB

QC

QD

G4

7

ENP

2

CLK

CLR

[1]

[2]

[4]

[8]

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SN54HC161, SN74HC161

4-BIT SYNCHRONOUS BINARY COUNTERS

 

 

SCLS297A – JANUARY 1996 – REVISED MAY 1997

3

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logic diagram (positive logic)

1

9

10

7

3

15

14

CLR

LOAD

ENT

ENP

CLK

A

RCO

QA

† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown

on the logic diagram of the D/T flip-flops.

Pin numbers shown are for the D, J, N, and W packages.

M1

G2

G4

3D

4R

1, 2T/1C3

4

13

B

QB

M1

G2

G4

3D

4R

1, 2T/1C3

5

12

C

QC

M1

G2

G4

3D

4R

1, 2T/1C3

6

11

D

QD

M1

G2

G4

3D

4R

1, 2T/1C3

2

LD†

CK†

CK

R

LD

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SN54HC161, SN74HC161

4-BIT SYNCHRONOUS BINARY COUNTERS

 

 

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logic symbol, each D/T flip-flop

M1

LD (Load)

Q (Output)

G2

TE (Toggle Enable)

CK (Clock)

G4

3D

4R

1, 2T/1C3

D (Inverted Data)

R (Inverted Reset)

logic diagram, each D/T flip-flop (positive logic)

TG

TG

TG

TG

TG

TG

CK

LD

TE

LD†

LD†

D

R

CK†

CK†

CK†

CK†

Q

† The origins of LD and CK are shown in the logic diagram of the overall device.

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SN54HC161, SN74HC161

4-BIT SYNCHRONOUS BINARY COUNTERS

 

 

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typical clear, preset, count, and inhibit sequence

The following sequence is illustrated below:

1.

Clear outputs to zero (asynchronous)

2.

Preset to binary 12

3.

Count to 13, 14, 15, 0, 1, and 2

4.

Inhibit

Data

Inputs

Data

Outputs

CLR

LOAD

A

B

C

D

CLK

ENP

ENT

RCO

QA

QB

QC

QD

Async

Clear

Sync

Clear

Preset

Count

Inhibit

12

13

14

15

0

1

2

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SN54HC161, SN74HC161

4-BIT SYNCHRONOUS BINARY COUNTERS

 

 

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absolute maximum ratings over operating free-air temperature range

Supply voltage range, V

CC

 

–0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input clamp current, I

IK

 (V

I

 < 0 or V

I

 > V

CC

) (see Note 1) 

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output clamp current, I

OK

 (V

O

 < 0 or V

O

 > V

CC

) (see Note 1) 

±

20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous output current, I

O

 (V

O

 = 0 to V

CC

±

25 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Continuous current through V

CC

 or GND 

±

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Package thermal impedance, 

θ

JA 

(see Note 2): D package 

113

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

N package 

78

°

C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range, T

stg

 –65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace

length of zero.

recommended operating conditions

SN54HC161

SN74HC161

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

2

5

6

2

5

6

V

VCC = 2 V

1.5

1.5

VIH

High-level input voltage

VCC = 4.5 V

3.15

3.15

V

VCC = 6 V

4.2

4.2

VCC = 2 V

0

0.5

0

0.5

VIL

Low-level input voltage

VCC = 4.5 V

0

1.35

0

1.35

V

VCC = 6 V

0

1.8

0

1.8

VI

Input voltage

0

VCC

0

VCC

V

VO

Output voltage

0

VCC

0

VCC

V

VCC = 2 V

0

1000

0

1000

tt‡

Input transition (rise and fall) time

VCC = 4.5 V

0

500

0

500

ns

VCC = 6 V

0

400

0

400

TA

Operating free-air temperature

–55

125

–40

85

°

C

‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced

grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,

the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

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SN54HC161, SN74HC161

4-BIT SYNCHRONOUS BINARY COUNTERS

 

 

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7

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electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25

°

C

SN54HC161

SN74HC161

UNIT

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

1.9

1.998

1.9

1.9

IOH = –20 

µ

A

4.5 V

4.4

4.499

4.4

4.4

VOH

VI = VIH or VIL

6 V

5.9

5.999

5.9

5.9

V

IOH = –4 mA

4.5 V

3.98

4.3

3.7

3.84

IOH = –5.2 mA

6 V

5.48

5.8

5.2

5.34

2 V

0.002

0.1

0.1

0.1

IOL = 20 

µ

A

4.5 V

0.001

0.1

0.1

0.1

VOL

VI = VIH or VIL

6 V

0.001

0.1

0.1

0.1

V

IOL = 4 mA

4.5 V

0.17

0.26

0.4

0.33

IOL = 5.2 mA

6 V

0.15

0.26

0.4

0.33

II

VI = VCC or 0

6 V

±

0.1

±

100

±

1000

±

1000

nA

ICC

VI = VCC or 0,

IO = 0

6 V

8

160

80

µ

A

Ci

2 V to 6 V

3

10

10

10

pF

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25

°

C

SN54HC161

SN74HC161

UNIT

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

0

6

0

4.2

0

5

fclock

Clock frequency

4.5 V

0

31

0

21

0

25

MHz

6 V

0

36

0

25

0

29

2 V

80

120

100

CLK high or low

4.5 V

16

24

20

t

Pulse duration

6 V

14

20

17

ns

tw

Pulse duration

2 V

80

120

100

ns

CLR low

4.5 V

16

24

20

6 V

14

20

17

2 V

150

225

190

A, B, C, or D

4.5 V

30

45

38

6 V

26

38

32

2 V

135

205

170

LOAD low

4.5 V

27

41

34

t

Setup time before CLK

6 V

23

35

29

ns

tsu

Setup time before CLK

2 V

170

255

215

ns

ENP, ENT

4.5 V

34

51

43

6 V

29

43

37

2 V

125

190

155

CLR inactive

4.5 V

25

38

31

6 V

21

32

26

2 V

0

0

0

th

Hold time, all synchronous inputs after CLK

4.5 V

0

0

0

ns

6 V

0

0

0

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4-BIT SYNCHRONOUS BINARY COUNTERS

 

 

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switching characteristics over recommended operating free-air temperature range, C

L

 = 50 pF

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25

°

C

SN54HC161

SN74HC161

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

6

14

4.2

5

fmax

4.5 V

31

40

21

25

MHz

6 V

36

44

25

29

2 V

83

215

325

270

RCO

4.5 V

24

43

65

54

CLK

6 V

20

37

55

46

CLK

2 V

80

205

310

255

tpd

Any Q

4.5 V

25

41

62

51

ns

6 V

21

35

53

43

2 V

62

195

295

245

ENT

RCO

4.5 V

17

39

59

49

6 V

14

33

50

42

2 V

105

210

315

265

Any Q

4.5 V

21

42

63

53

tPHL

CLR

6 V

18

36

54

45

ns

tPHL

CLR

2 V

110

220

330

275

ns

RCO

4.5 V

22

44

66

55

6 V

19

37

56

47

2 V

38

75

110

95

tt

Any

4.5 V

8

15

22

19

ns

6 V

6

13

19

16

operating characteristics, T

A

 = 25

°

C

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

No load

60

pF

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PARAMETER MEASUREMENT INFORMATION

VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

th

tsu

50%

50%

50%

10%

10%

90%

90%

VCC

VCC

0 V

0 V

tr

tf

Reference

Input

Data

Input

50%

High-Level

Pulse

50%

VCC

0 V

50%

50%

VCC

0 V

tw

Low-Level

Pulse

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

50%

50%

50%

10%

10%

90%

90%

VCC

VOH

VOL

0 V

tr

tf

Input

In-Phase

Output

50%

tPLH

tPHL

50%

50%

10%

10%

90%

90%

VOH

VOL

tr

tf

tPHL

tPLH

Out-of-Phase

Output

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR 

 1 MHz, ZO = 50 

, tr = 6 ns, tf = 6 ns.

C. For clock inputs, fmax is measured when the input duty cycle is 50%.

D. The outputs are measured one at a time with one input transition per measurement.

E. tPLH and tPHL are the same as tpd.

Test

Point

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Figure 1. Load Circuit and Voltage Waveforms

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APPLICATION INFORMATION

n-bit synchronous counters

This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit

counter. The ’HC161 count in binary. Virtually any count mode (modulo-N, N

1

-to-N

2

, N

1

-to-maximum) can be

used with this fast look-ahead circuit.

The application circuit shown in Figure 2 is not valid for clock frequencies above 18 MHz (at 25

°

C and

4.5-V V

CC

). The reason for this is that there is a glitch that is produced on the second stage’s RCO and every

succeeding stage’s RCO. This glitch is common to all HC vendors that Texas Instruments has evaluated, in

addition to the bipolar equivalents (LS, ALS, AS).

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LOAD

1,5D

A

B

C

D

C5/2,3,4+

RCO

3CT=MAX

QA

QB

QC

QD

CLR

[1]

[2]

[3]

[4]

CTR

LSB

ENT

ENP

CLK

LOAD

1,5D

A

B

C

D

C5/2,3,4+

RCO

3CT=MAX

QA

QB

QC

QD

CLR

[1]

[2]

[3]

[4]

CTR

ENT

ENP

CLK

LOAD

1,5D

A

B

C

D

C5/2,3,4+

RCO

3CT=MAX

QA

QB

QC

QD

CLR

[1]

[2]

[3]

[4]

CTR

ENT

ENP

CLK

LOAD

1,5D

A

B

C

D

C5/2,3,4+

RCO

3CT=MAX

QA

QB

QC

QD

CLR

[1]

[2]

[3]

[4]

CTR

ENT

ENP

CLK

To More Significant Stages

Clear (L)

Count (H)/

Disable (L)

Count (H)/

Disable (L)

Load (L)

Clock

CT=0

M1

G3

G4

CT=0

M1

G3

G4

CT=0

M1

G3

G4

CT=0

M1

G3

G4

Figure 2

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The glitch on RCO is caused because the propagation delay of the rising edge of Q

A

 of the second stage is

shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, Q

A

, Q

B

, Q

C

, and Q

D

(ENT 

×

 Q

×

 Q

×

 Q

×

 Q

D

). The resulting glitch is about 7–12 ns in duration. Figure 3 shows the condition in

which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to

other stages. Q

B

, Q

C

, and Q

D

 of the first and second stage are at logic one, and Q

A

 of both stages are at logic

zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, Q

A

 and RCO of the

first stage go high. On the rising edge of the third clock pulse, Q

A

 and RCO of the first stage return to a low level,

and Q

A

 of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears

because of the race condition inside the chip.

1

2

3

4

5

CLK

ENT1

QB1, QC1, QD1

QA1

RCO1, ENT2

QB2, QC2, QD2

QA2

RCO2

Glitch (7–12 ns)

Figure 3

The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock

edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the

inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (t

g

). In other words,

f

max

= 1/(t

pd

CLK-to-RCO + t

g

). For example, at 25

°

C at 4.5-V V

CC

, the clock-to-RCO propagation delay is

43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the

cascaded counters can use is 18 MHz. The following tables contain the f

clock

, t

w

, and f

max

 specifications for

applications that use more than two ’HC161 devices cascaded together.

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timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25

°

C

SN54HC161

SN74HC161

UNIT

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

0

3.6

0

2.5

0

2.9

fclock

Clock frequency

4.5 V

0

18

0

12

0

14

MHz

6 V

0

21

0

14

0

17

2 V

140

200

170

tw

Pulse duration, CLK high or low

4.5 V

28

40

36

ns

6 V

24

36

30

switching characteristics over recommended operating free-air temperature range, C

L

 = 50 pF

(unless otherwise noted) (see Note 3)

PARAMETER

FROM

TO

VCC

TA = 25

°

C

SN54HC161

SN74HC161

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

3.6

2.5

2.9

fmax

4.5 V

18

12

14

MHz

6 V

21

14

17

NOTE 3: These limits apply only to applications that use more than two ’HC161 devices cascaded together.

If the ’HC161 are used as a single unit, or only two cascaded together, then the maximum clock frequency that

the device can use is not limited because of the glitch. In these situations, the device can be operated at the

maximum specifications.

A glitch can appear on RCO of a single ’HC161 device, depending on the relationship of ENT to CLK. Any

application that uses RCO to drive any input except an ENT of another cascaded ’HC161 must take this

into consideration.

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