background image

 SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A

 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

  

 SDAS125B – MARCH 1984 – REVISED DECEMBER 1994

Copyright 

©

 1994, Texas Instruments Incorporated

2–1

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

Fully Synchronous Operation for Counting

and Programming

Internal Carry Look-Ahead Circuitry for

Fast Counting

Carry Output for n-Bit Cascading

Fully Independent Clock Circuit

Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

 

description

These synchronous 4-bit up/down binary

presettable counters feature an internal carry

look-ahead circuitry for cascading in high-speed

counting applications. Synchronous operation is

provided by having all flip-flops clocked

simultaneously so that the outputs change

coincident with each other when so instructed by

the count-enable (ENP, ENT) inputs and internal

gating. This mode of operation eliminates the

output counting spikes normally associated with

asynchronous (ripple-clock) counters. A buffered

clock (CLK) input triggers the four flip-flops on the

rising (positive-going) edge of the clock waveform.

These counters are fully programmable; that is,

they may be preset to either level. The load-input

circuitry allows loading with the carry-enable

output of cascaded counters. Because loading is

synchronous, setting up a low level at the load

(LOAD) input disables the counter and causes the

outputs to agree with the data inputs after the next

clock pulse.

The internal carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without

additional gating. ENP and ENT inputs and a ripple-carry output (RCO) are instrumental in accomplishing this

function. Both ENP and ENT must be low to count. The direction of the count is determined by the level of the

up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. ENT is fed forward

to enable RCO. RCO, thus enabled, produces a low-level pulse while the count is zero (all inputs low) counting

down or maximum (15) counting up. This low-level overflow ripple-carry pulse can be used to enable successive

cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input. All inputs

are diode clamped to minimize transmission-line effects, thereby simplifying system design.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, or U/D)

that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function

of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the

stable setup and hold times.

The SN54ALS169B and SN54AS169A are characterized for operation over the full military temperature range

of – 55

°

C to 125

°

C. The SN74ALS169B and SN74AS169A are characterized for operation from 0

°

C to 70

°

C.

SN54ALS169B, SN54AS169A . . . J  PACKAGE

SN74ALS169B, SN74AS169A . . . D  OR  N  PACKAGE

(TOP VIEW)

3

2

1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

Q

A

Q

B

NC

Q

C

Q

D

A

B

NC

C

D

SN54ALS169B, SN54AS169A . . . FK PACKAGE

(TOP VIEW)

CLK

U/D

NC

LOAD

ENT

RCO

ENP

GND

NC

NC – No internal connection

V

CC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

U/D

CLK

A

B

C

D

ENP

GND

V

CC

RCO

Q

A

Q

B

Q

C

Q

D

ENT

LOAD

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

  

SDAS125B – MARCH 1984 – REVISED DECEMBER 1994

2–2

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic symbol

CTRDIV16

LOAD

1, 7D

3

A

4

B

5

C

6

D

M2 [COUNT]

M1  [LOAD]

9

2,3,5,6+/C7

G5

10

15

3,5CT=15

14

13

12

11

QA

QB

QC

QD

G6

7

2

CLK

1

2

4

8

U/D

M4 [DOWN]

M3 [UP]

1

2,4,5,6 –

ENT

ENP

RCO

4,5CT=0

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

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 SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

  

 SDAS125B – MARCH 1984 – REVISED DECEMBER 1994

2–3

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

logic diagram (positive logic)

C1

1D

14

2

3

7

10

1

9

15

C1

1D

13

4

C1

1D

12

5

C1

1D

11

6

LOAD

U/D

ENT

ENP

CLK

A

B

C

D

QA

QB

QC

QD

RCO

Pin numbers shown are for the D, J, and N packages.

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SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

  

SDAS125B – MARCH 1984 – REVISED DECEMBER 1994

2–4

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

typical load, count, and inhibit sequences

The following sequence is illustrated below:

1.

Load (preset) to binary 13

2.

Count up to 14, 15 (maximum), 0, 1, and 2

3.

Inhibit

4.

Count down to 1, 0 (minimum), 15, 14, and 13

Data

Inputs

Data

Outputs

LOAD

A

B

C

D

CLK

U/D

ENP and ENT

RCO

QA

QB

QC

QD

Load

Count Up

Inhibit

13

14

15

0

0

1

2

Count Down

2

2

1

13

15

14

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

CC

 

 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage, V

I

 

 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range, T

A

: SN54ALS169B  

– 55

°

C to 125

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74ALS169B  

0

°

C to 70

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range 

 – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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 SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

  

 SDAS125B – MARCH 1984 – REVISED DECEMBER 1994

2–5

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

recommended operating conditions

SN54ALS169B

SN74ALS169B

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.5

5

5.5

4.5

5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.7

0.8

V

IOH

High-level output current

– 0.4

– 0.4

mA

IOL

Low-level output current

4

8

mA

fclock

Clock frequency

0

22

0

40

MHz

tw

Pulse duration, CLK high or low

14

12.5

ns

A, B, C, or D

20

15

t

Setup time before CLK

ENP or ENT

25

15

ns

tsu

Setup time before CLK

LOAD

20

15

ns

U/D

28

15

th

Hold time, data after CLK

0

0

ns

TA

Operating free-air temperature

– 55

125

0

70

°

C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

SN54ALS169B

SN74ALS169B

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

TYP†

MAX

UNIT

VIK

VCC = 4.5 V,

II = – 18 mA

– 1.5

– 1.5

V

VOH

VCC = 4.5 V to 5.5 V,

IOH = – 0.4 mA

VCC  – 2

VCC  – 2

V

VOL

VCC = 4 5 V

IOL = 4 mA

0.25

0.4

0.25

0.4

V

VOL

VCC = 4.5 V

IOL = 8 mA

0.35

0.5

V

II

VCC = 5.5 V,

VI = 7 V

0.1

0.1

mA

IIH

VCC = 5.5 V,

VI = 2.7 V

20

20

µ

A

IIL

VCC = 5.5 V,

VI = 0.4 V

– 0.2

– 0.2

mA

IO‡

VCC = 5.5 V,

VO = 2.25 V

– 20

– 112

– 30

– 112

mA

ICC

VCC = 5.5 V

15

25

15

25

mA

† All typical values are at VCC = 5 V, TA = 25

°

C.

‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

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SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

  

SDAS125B – MARCH 1984 – REVISED DECEMBER 1994

2–6

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

switching characteristics (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

RL = 500 

,

TA = MIN to MAX†

UNIT

(INPUT)

(OUTPUT)

SN54ALS169B

SN74ALS169B

MIN

MAX

MIN

MAX

fmax

22

40

MHz

tPLH

CLK

RCO

3

20

3

20

ns

tPHL

CLK

RCO

6

25

6

20

ns

tPLH

CLK

Any Q

2

20

2

15

ns

tPHL

CLK

Any Q

5

23

5

20

ns

tPLH

ENT

RCO

2

16

2

13

ns

tPHL

ENT

RCO

3

24

3

16

ns

tPLH

U/D

RCO

4

22

5

19

ns

tPHL

U/D

RCO

5

26

5

19

ns

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

CC

 

 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input voltage, V

I

 

 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Operating free-air temperature range, T

A

: SN54AS169A  

– 55

°

C to 125

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

SN74AS169A  

0

°

C to 70

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Storage temperature range 

 – 65

°

C to 150

°

C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

SN54AS169A

SN74AS169A

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.5

5

5.5

4.5

5

5.5

V

VIH

High-level input voltage

2

2

V

VIL

Low-level input voltage

0.8

0.8

V

IOH

High-level output current

– 2

– 2

mA

IOL

Low-level output current

20

20

mA

fclock*

Clock frequency

0

60

0

75

MHz

tw*

Pulse duration, CLK high or low

7.7

6.7

ns

A, B, C, or D

10

8

t

*

Setup time before CLK

ENP or ENT

10

8

ns

tsu*

Setup time before CLK

LOAD

10

8

ns

U/D

14

11

th*

Hold time, data after CLK

2

0

ns

TA

Operating free-air temperature

– 55

125

0

70

°

C

* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.

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 SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

  

 SDAS125B – MARCH 1984 – REVISED DECEMBER 1994

2–7

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

SN54AS169A

SN74AS169A

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

MIN

TYP†

MAX

UNIT

VIK

VCC = 4.5 V,

II = – 18 mA

– 1.2

– 1.2

V

VOH

VCC = 4.5 V to 5.5 V,

IOH = – 2 mA

VCC  – 2

VCC  – 2

V

VOL

VCC = 4.5 V,

IOL = 20 mA

0.25

0.5

0.25

0.5

V

II

LOAD, ENT, U/D

VCC = 5 5 V

VI = 7 V

0.2

0.2

mA

II

All others

VCC = 5.5 V,

VI = 7 V

0.1

0.1

mA

IIH

LOAD, ENT, U/D

VCC = 5 5 V

VI = 2 7 V

40

40

µ

A

IIH

All others

VCC = 5.5 V,

VI = 2.7 V

20

20

µ

A

IIL

LOAD, ENT, U/D

VCC = 5 5 V

VI = 0 4 V

–1

–1

mA

IIL

All others

VCC = 5.5 V,

VI = 0.4 V

– 0.5

– 0.5

mA

IO‡

VCC = 5.5 V,

VO = 2.25 V

– 30

– 112

– 30

– 112

mA

ICC

VCC = 5.5 V

41

63

41

63

mA

† All typical values are at VCC = 5 V, TA = 25

°

C.

‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

switching characteristics (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

RL = 500 

,

TA = MIN to MAX§

UNIT

(INPUT)

(OUTPUT)

SN54AS169A

SN74AS169A

MIN

MAX

MIN

MAX

fmax*

60

75

MHz

tPLH

CLK

RCO

3

17.5

3

16.5

ns

tPHL

CLK

(LOAD high or low)

2

14

2

13

ns

tPLH

CLK

Any Q

1

7.5

1

7

ns

tPHL

CLK

Any Q

2

14

2

13

ns

tPLH

ENT

RCO

1.5

10

1.5

9

ns

tPHL

ENT

RCO

1.5

10

1.5

9

ns

tPLH

U/D

RCO

2

14

2

12

ns

tPHL

U/D

RCO

2

14.5

2

13

ns

* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.

§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

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SN54ALS169B, SN54AS169A, SN74ALS169B, SN74AS169A

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

  

SDAS125B – MARCH 1984 – REVISED DECEMBER 1994

2–8

POST OFFICE BOX 655303 

 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/ 74ALS AND 54AS/ 74AS DEVICES

tPHZ

tPLZ

tPHL

tPLH

0.3 V

tPZL

tPZH

tPLH

tPHL

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

From Output

Under Test

Test 

Point

R1

S1

CL

(see Note A)

7 V

1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

th

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

High-Level

Pulse

Low-Level

Pulse

tw

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

Out-of-Phase

Output

(see Note C)

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

VOL

VOH

VOH

VOL

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

[

0 V

VOH

VOL

[

3.5 V

In-Phase

Output

0.3 V

1.3 V

1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

R2

VCC

RL

Test 

Point

From Output

Under Test

CL

(see Note A)

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR 

BI-STATE

TOTEM-POLE OUTPUTS

From Output

Under Test

Test 

Point

CL

(see Note A)

RL

RL = R1 = R2

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. When measuring propagation delay items of 3-state outputs, switch S1 is open.

D. All input pulses have the following characteristics: PRR 

 1 MHz, tr = tf = 2 ns, duty cycle = 50%.

E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

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Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

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Copyright 

©

 1998, Texas Instruments Incorporated