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80960JA/JF/JD/JT 3.3 V EMBEDDED 

32-BIT MICROPROCESSOR

 

Advance Information Datasheet

Product Features

s

Pin/Code Compatible with all 80960Jx 

Processors

s

High-Performance Embedded Architecture

— One Instruction/Clock Execution

— Core Clock Rate is:

80960JA/JF 1x the Bus Clock

80960JD 2x the Bus Clock 

80960JT 3x the Bus Clock

— Load/Store Programming Model

— Sixteen 32-Bit Global Registers

— Sixteen 32-Bit Local Registers (8 sets)

— Nine Addressing Modes

— User/Supervisor Protection Model

s

Two-Way Set Associative Instruction 

Cache

— 80960JA - 2 Kbyte

— 80960JF/JD - 4 Kbyte

— 80960JT - 16 Kbyte

— Programmable Cache-Locking 

Mechanism

s

Direct Mapped Data Cache

— 80960JA - 1 Kbyte

— 80960JF/JD - 2 Kbyte

— 80960JT - 4 Kbyte

— Write Through Operation

s

On-Chip Stack Frame Cache

— Seven Register Sets Can Be Saved

— Automatic Allocation on Call/Return

— 0-7 Frames Reserved for High-Priority 

Interrupts

s

On-Chip Data RAM

— 1 Kbyte Critical Variable Storage

— Single-Cycle Access

s

3.3 V Supply Voltage

— 5 V Tolerant Inputs

— TTL Compatible Outputs

s

High Bandwidth Burst Bus

— 32-Bit Multiplexed Address/Data

— Programmable Memory Configuration

— Selectable 8-, 16-, 32-Bit Bus Widths

— Supports Unaligned Accesses

— Big or Little Endian Byte Ordering

s

High-Speed Interrupt Controller

— 31 Programmable Priorities

— Eight Maskable Pins plus NMI

— Up to 240 Vectors in Expanded Mode

s

Two On-Chip Timers

— Independent 32-Bit Counting 

— Clock Prescaling by 1, 2, 4 or 8

— lnternal Interrupt Sources

s

Halt Mode for Low Power

s

IEEE 1149.1 (JTAG) Boundary Scan 

Compatibility

s

Packages

— 132-Lead Pin Grid Array (PGA)

— 132-Lead Plastic Quad Flat Pack 

(PQFP)

— 196-Ball Mini Plastic Ball Grid Array 

(MPBGA)

Order Number: 273159-001

March, 1998

Notice: This document contains information on products in the sampling and initial production 

phases of development. The specifications are subject to change without notice. Verify with your 

local Intel sales office that you have the latest datasheet before finalizing a design. 

background image

80960JA/JF/JD/JT 3.3 V Microprocessor

 

Advance Information Datasheet

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual 

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability 

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to 

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not 

intended for use in medical, life saving, or life sustaining applications. 

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for 

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 

80960JA/JF/JD/JT 3.3 V Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from 

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

Copyright © Intel Corporation, 1998

*Third-party brands and names are the property of their respective owners.

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Advance Information Datasheet

3

 

80960JA/JF/JD/JT 3.3 V Microprocessor

Contents

1.0

Introduction

.................................................................................................................. 7

2.0

80960Jx Overview

...................................................................................................... 7

2.1

80960 Processor Core .......................................................................................... 9

2.2

Burst Bus............................................................................................................. 10

2.3

Timer Unit............................................................................................................ 10

2.4

Priority Interrupt Controller .................................................................................. 10

2.5

Instruction Set Summary ..................................................................................... 11

2.6

Faults and Debugging ......................................................................................... 11

2.7

Low Power Operation.......................................................................................... 11

2.8

Test Features ...................................................................................................... 12

2.9

Memory-Mapped Control Registers .................................................................... 12

2.10

Data Types and Memory Addressing Modes ...................................................... 12

3.0

Package Information

............................................................................................... 14

3.1

Pin Descriptions .................................................................................................. 16

3.1.1

Functional Pin Definitions....................................................................... 16

3.1.2

80960Jx 132-Lead PGA Pinout.............................................................. 22

3.1.3

80960Jx 132-Lead PQFP Pinout............................................................ 26

3.1.4

80960Jx 196-Ball MPBGA Pinout .......................................................... 29

3.2

Package Thermal Specifications ......................................................................... 34

3.3

Thermal Management Accessories..................................................................... 38

3.3.1

Heatsinks................................................................................................ 38

4.0

Electrical Specifications

........................................................................................ 39

4.1

Absolute Maximum Ratings................................................................................. 39

4.2

Operating Conditions........................................................................................... 39

4.3

Connection Recommendations ........................................................................... 40

4.4

VCC5 Pin Requirements (VDIFF) ....................................................................... 40

4.5

VCCPLL Pin Requirements................................................................................. 41

4.6

DC Specifications ................................................................................................ 42

4.7

AC Specifications ................................................................................................ 44

4.7.1

AC Test Conditions and Derating Curves .............................................. 47

4.7.2

AC Timing Waveforms ........................................................................... 52

5.0

Bus Functional Waveforms

.................................................................................. 58

5.1

Basic Bus States ................................................................................................. 68

5.2

Boundary-Scan Register ..................................................................................... 69

6.0

Device Identification

............................................................................................... 74

7.0

Revision History

....................................................................................................... 77

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80960JA/JF/JD/JT 3.3 V Microprocessor

 

4

 

Advance Information Datasheet

Figures

1

80960Jx Microprocessor Package Options...........................................................7

2

80960Jx Block Diagram ........................................................................................9

3

132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................22

4

132-Lead Pin Grid Array Top View - Pins Facing Down .....................................23

5

132-Lead PQFP - Top View ................................................................................26

6

196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up ..................29

7

196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down ..................30

8

VCC5 Current-Limiting Resistor ..........................................................................40

9

VCCPLL Lowpass Filter ......................................................................................41

10

AC Test Load ......................................................................................................47

11

Output Delay or Hold vs. Load Capacitance .......................................................48

12

T

LX

 vs. AD Bus Load Capacitance......................................................................48

13

80960JA/JF I

CC

 Active (Power Supply) vs. Frequency .......................................49

14

80960JA/JF I

CC

 Active (Thermal) vs. Frequency ................................................49

15

80960JD I

CC

 Active (Power Supply) vs. Frequency............................................50

16

80960JD I

CC

 Active (Thermal) vs. Frequency.....................................................50

17

80960JT I

CC

 Active  (Power Supply) vs. Frequency ...........................................51

18

80960JT I

CC

 Active (Thermal) vs. Frequency .....................................................51

19

CLKIN Waveform ................................................................................................52

20

T

OV1

 Output Delay Waveform .............................................................................52

21

T

OF

 Output Float Waveform ................................................................................53

22

T

IS1

 and T

IH1

 Input Setup and Hold Waveform ...................................................53

23

T

IS2

 and T

IH2

 Input Setup and Hold Waveform ...................................................53

24

T

IS3

 and T

IH3

 Input Setup and Hold Waveform ...................................................54

25

T

IS4

 and T

IH4

 Input Setup and Hold Waveform ...................................................54

26

T

LX

, T

LXL

 and T

LXA

 Relative Timings Waveform.................................................55

27

DT/R and DEN Timings Waveform .....................................................................55

28

TCK Waveform....................................................................................................56

29

T

BSIS1

 and T

BSIH1

 Input Setup and Hold Waveforms .........................................56

30

T

BSOV1

 and T

BSOF1

 Output Delay and Output Float Waveform..........................56

31

T

BSOV2

 and T

BSOF2

 Output Delay and Output Float Waveform..........................57

32

T

BSIS2

 and T

BSIH2

 Input Setup and Hold Waveform ...........................................57

33

Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .........58

34

Burst Read and Write Transactions Without Wait States, 32-Bit Bus .................59

35

Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus...........................60

36

Burst Read and Write Transactions Without Wait States, 8-Bit Bus ...................61

37

Burst Read and Write Transactions With 1, 0 Wait States and 

Extra Tr State on Read, 16-Bit Bus .....................................................................62

38

Double Word Read Bus Request, Misaligned One Byte From 

Quad Word Boundary, 32-Bit Bus, Little Endian .................................................63

39

HOLD/HOLDA Waveform For Bus Arbitration ....................................................64

40

Cold Reset Waveform .........................................................................................65

41

Warm Reset Waveform .......................................................................................66

42

Entering the ONCE State ....................................................................................67

43

Bus States with Arbitration ..................................................................................68

44

Summary of Aligned and Unaligned Accesses (32-Bit Bus) ...............................72

45

Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ...........73

46

80960JT Device Identification Register...............................................................74

47

80960JD Device Identification Register ..............................................................75

48

80960JA/JF Device Identification Register .........................................................76

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Advance Information Datasheet

5

 

80960JA/JF/JD/JT 3.3 V Microprocessor

Tables

1

80960Jx Instruction Set....................................................................................... 13

2

Pin Description Nomenclature............................................................................. 16

3

Pin Description — External Bus Signals ............................................................. 17

4

Pin Description — Processor Control Signals, Test Signals and Power ............. 20

5

Pin Description — Interrupt Unit Signals ............................................................. 21

6

132-Lead PGA Pinout — In Signal Order............................................................ 24

7

132-Lead PGA Pinout — In Pin Order ................................................................ 25

8

132-Lead PQFP Pinout — In Signal Order ......................................................... 27

9

132-Lead PQFP Pinout — In Pin Order .............................................................. 28

10

196-Ball MPBGA Pinout — In Signal Order ........................................................ 31

11

196-Ball MPBGA Pinout — In Pin Order ............................................................. 33

12

132-Lead PGA Package Thermal Characteristics............................................... 35

13

196-Ball MPBGA Package Thermal Characteristics ........................................... 35

14

132-Lead PQFP Package Thermal Characteristics ............................................ 36

15

Maximum T

at Various Airflows in °C (80960JT) ............................................... 36

16

Maximum T

at Various Airflows in °C (80960JD) .............................................. 37

17

Maximum T

at Various Airflows in °C (80960JA/JF).......................................... 37

18

Absolute Maximum Ratings................................................................................. 39

19

80960Jx Operating Conditions ............................................................................ 39

20

VDIFF Parameters .............................................................................................. 40

21

80960Jx DC Characteristics................................................................................ 42

22

80960Jx I

CC

 Characteristics................................................................................ 42

23

80960Jx AC Characteristics ................................................................................ 44

24

Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44) ................... 47

25

Boundary-Scan Register Bit Order...................................................................... 69

26

Natural Boundaries for Load and Store Accesses .............................................. 70

27

Summary of Byte Load and Store Accesses....................................................... 70

28

Summary of Short Word Load and Store Accesses............................................ 70

29

Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)........................... 71

30

80960Jx Device Type and Stepping Reference .................................................. 74

31

Fields of 80960JT Device ID ............................................................................... 75

32

80960JT Device ID Model Types ........................................................................ 75

33

Fields of 80960JD Device ID............................................................................... 76

34

80960JD Device ID Model Types........................................................................ 76

35

Fields of 80960JA/JF Device ID .......................................................................... 77

36

80960JA/JF Device ID Model Types ................................................................... 77

37

Data Sheet Revision History ............................................................................... 77

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 Advance Information Datasheet

7

80960JA/JF/JD/JT 3.3 V Microprocessor

1.0

Introduction

This document contains information for the 80960Jx microprocessor, including electrical 

characteristics and package pinout information. Detailed functional descriptions — other than 

parametric performance — are published in the i960

®

 Jx Microprocessor Developer’s Manual 

(272483).

Throughout this data sheet, references to “80960Jx” indicate features that apply to all of the 

following:

80960JA — 3.3 V (5 V Tolerant), 2 Kbyte instruction cache, 1 Kbyte data cache

80960JF — 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache

80960JD — 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache and clock 

doubling

80960JT — 3.3 V (5 V Tolerant), 16 Kbyte instruction cache, 4 Kbyte data cache and clock 

tripling

2.0

80960Jx Overview

The 80960Jx offers high performance to cost-sensitive 32-bit embedded applications. The 80960Jx 

is object code compatible with the 80960 Core Architecture and is capable of sustained execution 

at the rate of one instruction per clock. This processor’s features include generous instruction 

cache, data cache and data RAM. It also boasts a fast interrupt mechanism and dual-programmable 

timer units.

The 80960Jx’s clock multiplication operates the processor core at two or three times the bus clock 

rate to improve execution performance without increasing the complexity of board designs.

Memory subsystems for cost-sensitive embedded applications often impose substantial wait state 

penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU 

execution from the external bus.

Figure 1.

80960Jx Microprocessor Package Options

i960

®

i

i

© 19xx

© 19xx

A80960JX

NG80960JX

XXXXXXXXSS

XXXXXXXX SS

i

© 19xx

GD80960JX

XXXXXXXSS

132-Pin PGA

132-Pin PQFP

136-Ball MPBGA

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80960JA/JF/JD/JT 3.3 V Microprocessor

8

 

 Advance Information Datasheet

The 80960Jx rapidly allocates and deallocates local register sets during context switches. The 

processor needs to flush a register set to the stack only when it saves more than seven sets to its 

local register cache.

A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full 

complement of control signals simplifies the connection of the 80960Jx to external components. 

The user programs physical and logical memory attributes through memory-mapped control 

registers (MMRs) — an extension not found on the i960 Kx, Sx or Cx processors. Physical and 

logical configuration registers enable the processor to operate with all combinations of bus width 

and data object alignment. The processor supports a homogeneous byte ordering model.

This processor integrates two important peripherals: a timer unit, and an interrupt controller. These 

and other hardware resources are programmed through memory-mapped control registers, an 

extension to the familiar 80960 architecture.

The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and 

general-purpose system timing. These operate in either single-shot or auto-reload mode and can 

generate interrupts. 

The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts. 

The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The 

ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt 

latency. Clock doubling reduces interrupt latency by 40% compared to the 80960JA/JF, and clock 

tripling reduces interrupt latency by 20% compared to the 80960JD. Local registers may be 

dedicated to high-priority interrupts to further reduce latency. Acting independently from the core, 

the ICU compares the priorities of posted interrupts with the current process priority, off-loading 

this task from the core. The ICU also supports the integrated timer interrupts.

The 80960Jx features a Halt mode designed to support applications where low power consumption 

is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up 

to 90 percent.

The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and Boundary 

Scan (JTAG), provide a powerful environment for design debug and fault diagnosis.

The Solutions960

®

 program features a wide variety of development tools which support the i960

 

processor family. Many of these tools are developed by partner companies; some are developed by 

Intel, such as profile-driven optimizing compilers. For more information on these products, contact 

your local Intel representative.

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 Advance Information Datasheet

9

80960JA/JF/JD/JT 3.3 V Microprocessor

2.1

80960 Processor Core

The 80960Jx family is a scalar implementation of the 80960 Core Architecture. Intel designed this 

processor core as a very high performance device that is also cost-effective. Factors that contribute 

to the core’s performance include:

Core operates at the bus speed with the 80960JA/JF

Core operates at two or three times the bus speed with the 80960JD and 80960JT respectively

Single-clock execution of most instructions

Independent Multiply/Divide Unit

Efficient instruction pipeline minimizes pipeline break latency

Register and resource scoreboarding allow overlapped instruction execution

128-bit register bus speeds local register caching

Two-way set associative, integrated instruction cache 

Direct-mapped, integrated data cache

1 Kbyte integrated data RAM delivers zero wait state program data

Figure 2.

80960Jx Block Diagram

Programmable

Interrupt Controller

Control

Address/

Instruction Sequencer

 

Physical Region

Configuration

Interrupt 

Port

1K Data RAM

Memory

Interface

Execution

Multiply

Unit

Divide

Unit

Memory-Mapped 

Register Interface

Data Bus

Global / Local

Register File

SRC2 DEST

SRC1

address

Control

 effective

Constants

Generation

Unit

Address

32-bit Address

32-bit Data

Bus Request

Queues

and

Two 32-Bit 

Timers

8-Set

Local Register Cache

SRC1

SRC2

DEST

PLL, Clocks,

Power Mgmt

Boundary Scan

Controller

TAP

5

CLKIN

S

RC1

S

RC2

DE

ST

SRC1

DES

T

9

32

32-bit buses

address / data

21

Instruction Cache

80960JA - 2K

80960JF/JD - 4K

80960JT - 16K

Two-Way Set Associative

 Direct Mapped 

Data Cache

80960JA - 1K

80960JF/JD - 2K

80960JT - 4K

128

3 Independent 32-Bit SRC1, SRC2, and DEST Buses

Bus 

Control Unit

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80960JA/JF/JD/JT 3.3 V Microprocessor

10

 

 Advance Information Datasheet

2.2

Burst Bus

A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory 

and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit 

words per six clock cycles. The external address/data bus is multiplexed.

Users may configure the 80960Jx’s bus controller to match an application’s fundamental memory 

organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and 

data caching are programmed through a group of logical memory templates and a defaults register. 

The BCU’s features include:

Multiplexed external bus to minimize pin count

32-, 16- and 8-bit bus widths to simplify I/O interfaces

External ready control for address-to-data, data-to-data and data-to-next-address wait state types

Support for big or little endian byte ordering to facilitate the porting of existing program code

Unaligned bus accesses performed transparently

Three-deep load/store queue to decouple the bus from the core

Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it 

performs an external bus confidence test by performing a checksum on the first words of the 

initialization boot record (IBR).

The user may examine the contents of the caches by executing special cache control instructions.

2.3

Timer Unit

The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several 

clock rates and generating interrupts. Each is programmed by use of the TU registers. These 

memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot 

mode and auto-reload capabilities for continuous operation. Each timer has an independent 

interrupt request to the 80960Jx’s interrupt controller. The TU can generate a fault when 

unauthorized writes from user mode are detected. Clock prescaling is supported.

2.4

Priority Interrupt Controller

A programmable interrupt controller manages up to 240 external sources through an 8-bit external 

interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or 

level-triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer 

channels and a single Non-Maskable Interrupt (NMI) pin. Interrupts are serviced according to their 

priority levels relative to the current process priority.

Low interrupt latency is critical to many embedded applications. As part of its highly flexible 

interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:

Interrupt vectors and interrupt handler routines can be reserved on-chip

Register frames for high-priority interrupt handlers can be cached on-chip

The interrupt stack can be placed in cacheable memory space

Interrupt microcode executes at two or three times the bus frequency for the 80960JD and 

80960JT respectively

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 Advance Information Datasheet

11

80960JA/JF/JD/JT 3.3 V Microprocessor

2.5

Instruction Set Summary

The 80960Jx adds several new instructions to the i960 core architecture. The new instructions are:

Conditional Move

Conditional Add

Conditional Subtract

Byte Swap

Halt

Cache Control

Interrupt Control

Table 1 identifies the instructions that the 80960Jx supports. Refer to the i960

®

 Jx Microprocessor 

Developer’s Manual (272483) for a detailed description of each instruction. 

2.6

Faults and Debugging

The 80960Jx employs a comprehensive fault model. The processor responds to faults by making 

implicit calls to a fault handling routine. Specific information collected for each fault allows the 

fault handler to diagnose exceptions and recover appropriately.

The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to 

detect as many as seven different trace event types. Alternatively, mark and fmark instructions 

can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are 

also available to trap on execution and data addresses.

2.7

Low Power Operation

Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s 

sub-micron topology provides the circuit density for optimal cache size and high operating speeds 

while dissipating modest power. The processor also uses dynamic power management to turn off 

clocks to unused circuits.

Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode, 

the processor core stops completely while the integrated peripherals continue to function, reducing 

overall power requirements up to 90 percent. Processor execution resumes from internally or 

externally generated interrupts.

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2.8

Test Features

The 80960Jx incorporates numerous features which enhance the user’s ability to test both the 

processor and the system to which it is attached. These features include ONCE (On-Circuit 

Emulation) mode and Boundary Scan (JTAG).

The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and 

Boundary Scan Architecture (IEEE Std. 1149.1). 

One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE 

mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism.

ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to 

electrically “remove” itself from a circuit board. This allows for system-level testing where a 

remote tester — such as an in-circuit emulator — can exercise the processor system.

The provided test logic does not interfere with component or circuit board behavior and ensures 

that components function correctly, connections between various components are correct, and 

various components interact correctly on the printed circuit board.

The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing. 

It can examine connections which might otherwise be inaccessible to a test system.

2.9

Memory-Mapped Control Registers

The 80960Jx, though compliant with i960 series processor core, has the added advantage of 

memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These 

give software the interface to easily read and modify internal control registers. 

Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished 

through regular memory-format instructions. The processor ensures that these accesses do not 

generate external bus cycles.

2.10

Data Types and Memory Addressing Modes

As with all i960 family processors, the 80960Jx instruction set supports several data types and formats:

Bit

Bit fields

Integer (8-, 16-, 32-, 64-bit)

Ordinal (8-, 16-, 32-, 64-bit unsigned integers)

Triple word (96 bits)

Quad word (128 bits)

The 80960Jx provides a full set of addressing modes for C and assembly programming:

Two Absolute modes

Five Register Indirect modes 

Index with displacement

IP with displacement

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80960JA/JF/JD/JT 3.3 V Microprocessor

Table 1. 

80960Jx Instruction Set

Data Movement

Arithmetic

Logical

Bit, Bit Field and Byte

Load

Store

Move

*Conditional Select

Load Address

Add

Subtract

Multiply

Divide

Remainder

Modulo

Shift

Extended Shift

Extended Multiply

Extended Divide

Add with Carry

Subtract with Carry

*Conditional Add

*Conditional Subtract

Rotate

And

Not And

And Not

Or

Exclusive Or

Not Or

Or Not

Nor

Exclusive Nor

Not

Nand

Set Bit

Clear Bit

Not Bit

Alter Bit

Scan For Bit

Span Over Bit

Extract

Modify

Scan Byte for Equal

*Byte Swap

Comparison

Branch

Call/Return

Fault

Compare

Conditional Compare

Compare and Increment

Compare and Decrement

Test Condition Code

Check Bit

Unconditional Branch

Conditional Branch

Compare and Branch

Call

Call Extended

Call System

Return

Branch and Link

Conditional Fault

Synchronize Faults

Debug

Processor Management

Atomic

Modify Trace Controls

Mark

Force Mark

Flush Local Registers

Modify Arithmetic 

Controls

Modify Process Controls

*Halt

System Control

*Cache Control

*Interrupt Control

Atomic Add

Atomic Modify

Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB implementations.

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3.0

Package Information

The 80960Jx is offered with four speeds and three package types. The 132-pin Pin Grid Array 

(PGA) device is specified for operation at V

CC

= 3.3 V ± 0.15 V over a case temperature range of 

0° to 100°C:

A80960JT-100 (100 MHz core, 33 MHz bus)

A80960JT-75 (75 MHz core, 25 MHz bus)

A80960JD-66 (66 MHz core, 33 MHz bus)

A80960JD-50 (50 MHz core, 25 MHz bus)

A80960JD-40 (40 MHz core, 20 MHz bus)

A80960JD-33 (33 MHz core, 16 MHz bus)

A80960JA/JF-33 (33 MHz)

A80960JA/JF-25 (25 MHz)

A80960JA/JF-16 (16 MHz)

The 132-pin Plastic Quad Flatpack (PQFP) devices are specified for operation at 

V

CC

= 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C:

NG80960JT-100 (100 MHz core, 33 MHz bus)

NG80960JT-75 (75 MHz core, 25 MHz bus)

NG80960JD-66 (66 MHz core, 33 MHz bus)

NG80960JD-50 (50 MHz core, 25 MHz bus)

NG80960JD-40 (40 MHz core, 20 MHz bus)

NG80960JD-33 (33 MHz core, 16 MHz bus)

NG80960JA/JF-33 (33 MHz)

NG80960JA/JF-25 (25 MHz)

NG80960JA/JF-16 (16 MHz)

An extended temperature 132-pin Plastic Quad Flatpack (PQFP) device is specified for operation 

at V

CC

= 3.3 V ± 0.15 V over a case temperature range of -40° to 100°C:

TG80960JA-25 (25 MHz)

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80960JA/JF/JD/JT 3.3 V Microprocessor

The 196-ball Mini Plastic Ball Grid Array (MPBGA) device is specified for operation at 

V

CC

= 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C:

GD80960JT-100 (100 MHz core, 33 MHz bus)

GD80960JT-75 (75 MHz core, 25 MHz bus)

GD80960JD-50 (50 MHz core, 25 MHz bus)

GD80960JD-40 (40 MHz core, 20 MHz bus)

GD80960JD-33 (33 MHz core, 16 MHz bus)

GD80960JA/JF-33 (33 MHz)

GD80960JA/JF-25 (25 MHz)

GD80960JA/JF-16 (16 MHz)

For package specifications and information, refer to Intel’s Packaging Handbook (240800).

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3.1

Pin Descriptions

This section describes the pins for the 80960Jx in the 132-pin ceramic Pin Grid Array (PGA) 

package, 132-lead Plastic Quad Flatpack Package (PQFP) and 196-ball Mini Plastic Ball Grid 

Array (MPBGA).

Section 3.1.1, “Functional Pin Definitions”, describes pin function; Section 3.1.2, “80960Jx 

132-Lead PGA Pinout”, Section 3.1.3, “80960Jx 132-Lead PQFP Pinout” and Section 3.1.4, 

“80960Jx 196-Ball MPBGA Pinout”, define the signal and pin locations for the supported package 

types. 

3.1.1

Functional Pin Definitions

Table 2 presents the legend for interpreting the pin descriptions which follow. Pins associated with 

the bus interface are described in Table 3. Pins associated with basic control and test functions are 

described in Table 4. Pins associated with the Interrupt Unit are described in Table 5.

Table 2. 

Pin Description Nomenclature

Symbol

Description

I

Input pin only.

O

Output pin only.

I/O

Pin can be either an input or output.

Pin must be connected as described.

S

Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation.

S(E) Edge sensitive input

S(L) Level sensitive input

A (...)

Asynchronous. Inputs may be asynchronous relative to CLKIN.

A(E) Edge sensitive input

A(L) Level sensitive input

R (...)

While the processor’s RESET pin is asserted, the pin:

R(1) is driven to V

CC

R(0) is driven to V

SS

R(Q) is a valid output

R(X) is driven to unknown state

R(H) is pulled up to V

CC

H (...)

While the processor is in the hold state, the pin:

H(1) is driven to V

CC

H(0) is driven to V

SS

H(Q) Maintains previous state or continues to be a valid output

H(Z) Floats

P (...)

While the processor is halted, the pin:

P(1) is driven to V

CC

P(0) is driven to V

SS

P(Q) Maintains previous state or continues to be a valid output

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Table 3. 

Pin Description — External Bus Signals (Sheet 1 of 3)

NAME

TYPE

DESCRIPTION

AD31:0

I/O

S(L)

R(X)

H(Z)

P(Q)

ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data 

to and from memory. During an address (

T

a

) cycle, bits 31:2 contain a physical word 

address (bits 0-1 indicate SIZE; see below). During a data (T

d

) cycle, read or write 

data is present on one or more contiguous bytes, comprising AD31:24, AD23:16, 

AD15:8 and AD7:0. During write operations, unused pins are driven to determinate 

values.

SIZE, which comprises bits 0-1 of the AD lines during a 

T

a

 cycle, specifies the 

number of data transfers during the bus transaction.

AD1

AD0

Bus Transfers

0

0 1 

Transfer

0

1

 2 

Transfers

1

0 3 

Transfers

1

1 4 

Transfers

When the processor enters Halt mode, if the previous bus operation was a:

write — AD31:2 are driven with the last data value on the AD bus.

read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are 

driven with the value of A3:2 from the last data cycle.

Typically, AD1:0 reflect the SIZE information of the last bus transaction (either 

instruction fetch or load/store) that was executed before entering Halt mode.

ALE

O

R(0)

H(Z)

P(0)

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is 

asserted during a 

T

a

 cycle and deasserted before the beginning of the T

d

 state. It is 

active HIGH and floats to a high impedance state during a hold cycle (T

h

).

ALE

O

R(1)

H(Z)

P(1)

ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is the 

inverted version of ALE. This signal gives the 80960Jx a high degree of compatibility 

with existing 80960Kx systems.

ADS

O

R(1)

H(Z)

P(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access. 

The processor asserts ADS for the entire 

T

a

 cycle. External bus control logic typically 

samples ADS at the end of the cycle.

A3:2

O

R(X)

H(Z)

P(Q)

ADDRESS3:2 comprise a partial demultiplexed address bus. 

32-bit memory accesses:

 the processor asserts address bits A3:2 during 

T

a

. The 

partial word address increments with each assertion of RDYRCV during a burst.

16-bit memory accesses:

 the processor asserts address bits A3:1 during 

T

a

 with A1 

driven on the BE1 pin. The partial short word address increments with each 

assertion of RDYRCV during a burst.

8-bit memory accesses: 

the processor asserts address bits A3:0 during 

T

a

, with A1:0 

driven on BE1:0. The partial byte address increments with each assertion of 

RDYRCV during a burst.

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BE3:0

O

R(1)

H(Z)

P(1)

BYTE ENABLES select which of up to four data bytes on the bus participate in the 

current bus access. Byte enable encoding is dependent on the bus width of the 

memory region accessed:

32-bit bus:

 

BE3 enables data on AD31:24

BE2 enables data on AD23:16

BE1 enables data on AD15:8

BE0 enables data on AD7:0

16-bit bus:

BE3 becomes Byte High Enable (enables data on AD15:8)

BE2 is not used (state is high)

BE1 becomes Address Bit 1 (A1)

BE0 becomes Byte Low Enable (enables data on AD7:0)

8-bit bus:

BE3 is not used (state is high)

BE2 is not used (state is high)

BE1 becomes Address Bit 1 (A1)

BE0 becomes Address Bit 0 (A0)

The processor asserts byte enables, byte high enable and byte low enable during 

T

a

Since unaligned bus requests are split into separate bus transactions, these signals 

do not toggle during a burst. They remain active through the last T

d

 cycle. 

For accesses to 8- and 16-bit memory, the processor asserts the address bits in 

conjunction with A3:2 described above.

WIDTH/

HLTD1:0

O

R(0)

H(Z)

P(1)

WIDTH/HALTED signals denote the physical memory attributes for a bus 

transaction:

WIDTH/HLTD1  WIDTH/HLTD0

0

0

8 Bits Wide

0

1

16 Bits Wide

1

0

32 Bits Wide

1

1

Processor Halted

The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in 

response to a HOLD request, regardless of prior operating state.

D/C

O

R(X)

H(Z)

P(Q)

DATA/CODE indicates that a bus access is a data access (1) or an instruction 

access (0). D/C has the same timing as W/R.

0 = instruction access

1 = data access

W/R

O

R(0)

H(Z)

P(Q)

WRITE/READ specifies, during a 

T

a

 cycle, whether the operation is a write (1) or 

read (0). It is latched on-chip and remains valid during T

d

 cycles.

0 = read

1 = write 

DT/R

O

R(0)

H(Z)

P(Q)

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the 

address/data bus. It is low during T

a

 and T

w

/T

d

 cycles for a read; it is high during 

T

a

 

and T

w

/T

d

 cycles for a write. DT/R never changes state when DEN is asserted.

0 = receive

1 = transmit

DEN

O

R(1)

H(Z)

P(1)

DATA ENABLE indicates data transfer cycles during a bus access. DEN is asserted 

at the start of the first data cycle in a bus access and deasserted at the end of the 

last data cycle. DEN is used with DT/R to provide control for data transceivers 

connected to the data bus.

0 = data cycle

1 = not data cycle

Table 3. 

Pin Description — External Bus Signals (Sheet 2 of 3)

NAME

TYPE

DESCRIPTION

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BLAST

O

R(1)

H(Z)

P(1)

BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the 

last data transfer of burst and non-burst accesses. BLAST remains active as long as 

wait states are inserted via the RDYRCV pin. BLAST becomes inactive after the final 

data transfer in a bus cycle.

0 = last data transfer

1 = not last data transfer

RDYRCV

I

S(L)

READY/RECOVER indicates that data on AD lines can be sampled or removed. If 

RDYRCV is not asserted during a T

d

 cycle, the T

d

 cycle is extended to the next cycle 

by inserting a wait state (T

w

).

0 = sample data

1 = don’t sample data

The RDYRCV pin has another function during the recovery (T

r

) state. The processor 

continues to insert additional recovery states until it samples the pin HIGH. This 

function gives slow external devices more time to float their buffers before the 

processor begins to drive address again.

0 = insert wait states

1 = recovery complete

LOCK/ 

ONCE

I/O

S(L)

R(H)

H(Z)

P(1)

BUS LOCK indicates that an atomic read-modify-write operation is in progress. The 

LOCK output is asserted in the first clock of an atomic operation and deasserted in 

the last data transfer of the sequence. The processor does not grant HOLDA while it 

is asserting LOCK. This prevents external agents from accessing memory involved 

in semaphore operations.

0 = Atomic read-modify-write in progress

1 = Atomic read-modify-write not in progress

ONCE MODE: The processor samples the ONCE input during reset. If it is asserted 

LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the 

processor stops all clocks and floats all output pins. The pin has a weak internal 

pullup which is active during reset to ensure normal operation when the pin is left 

unconnected.

0 = ONCE mode enabled

1 = ONCE mode not enabled

HOLD

I

S(L)

HOLD: A request from an external bus master to acquire the bus. When the 

processor receives HOLD and grants bus control to another master, it asserts 

HOLDA, floats the address/data and control lines and enters the T

h

 state. When 

HOLD is deasserted, the processor deasserts HOLDA and enters either the T

i

 or 

T

a

 

state, resuming control of the address/data and control lines.

0 = no hold request

1 = hold request

HOLDA

O

R(Q)

H(1)

P(Q)

HOLD ACKNOWLEDGE indicates to an external bus master that the processor has 

relinquished control of the bus. The processor can grant HOLD requests and enter 

the T

h

 state during reset and while halted as well as during regular operation.

0 = hold not acknowledged

1 = hold acknowledged

BSTAT

O

R(0)

H(Q)

P(0)

BUS STATUS indicates that the processor may soon stall unless it has sufficient 

access to the bus; see 

i960

®

 Jx Microprocessor Developer’s Manual 

(272483). 

Arbitration logic can examine this signal to determine when an external bus master 

should acquire/relinquish the bus.

0 = no potential stall

1 = potential stall

Table 3. 

Pin Description — External Bus Signals (Sheet 3 of 3)

NAME

TYPE

DESCRIPTION

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Table 4. 

Pin Description — Processor Control Signals, Test Signals and Power 

NAME

TYPE

DESCRIPTION

CLKIN

I

CLOCK INPUT provides the processor’s fundamental time base; both the processor 

core and the external bus run at the CLKIN rate. All input and output timings are 

specified relative to a rising CLKIN edge.

RESET

I

A(L)

RESET initializes the processor and clears its internal logic. During reset, the 

processor places the address/data bus and control output pins in their idle (inactive) 

states.

During reset, the input pins are ignored with the exception of LOCK/ONCE, STEST 

and HOLD.

The RESET pin has an internal synchronizer. To ensure predictable processor 

initialization during power up, RESET must be asserted a minimum of 10,000 CLKIN 

cycles with V

CC

 and CLKIN stable. On a warm reset, RESET should be asserted for 

a minimum of 15 cycles.

STEST

I

S(L)

SELF TEST enables or disables the processor’s internal self-test feature at 

initialization. STEST is examined at the end of reset. When STEST is asserted, the 

processor performs its internal self-test and the external bus confidence test. When 

STEST is deasserted, the processor performs only the external bus confidence test.

0 = self test disabled

1 = self test enabled

FAIL

O

R(0)

H(Q)

P(1)

FAIL indicates a failure of the processor’s built-in self-test performed during 

initialization. FAIL is asserted immediately upon reset and toggles during self-test to 

indicate the status of individual tests:

When self-test passes, the processor deasserts FAIL and begins operation from 

user code. 

When self-test fails, the processor asserts FAIL and then stops executing.

0 = self test failed

1 = self test passed

TCK

I

TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1 

Boundary Scan Testing (JTAG). State information and data are clocked into the 

processor on the rising edge; data is clocked out of the processor on the falling edge.

TDI

I

S(L)

TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising 

edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.

TDO

O

R(Q)

HQ)

P(Q)

TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling 

edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At 

other times, TDO floats. TDO does not float during ONCE mode.

TRST

I

A(L)

TEST RESET asynchronously resets the Test Access Port (TAP) controller function 

of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan 

feature, connect a pulldown resistor between this pin and V

SS

. If TAP is not used, 

this pin must be connected to V

SS

; however, no resistor is required. See Section 4.3, 

“Connection Recommendations” on page 40.

TMS

I

S(L)

TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of 

the test logic for IEEE 1149.1 Boundary Scan testing.

V

CC

POWER pins intended for external connection to a V

CC

 board plane.

VCCPLL

PLL POWER is a separate V

CC

 supply pin for the phase lock loop clock generator. It 

is intended for external connection to the V

CC

 board plane. In noisy environments, 

add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects 

on timing relationships.

VCC5

5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O 

buffers. This signal should be connected to +5 V for use with inputs which exceed 

3.3 V. If all inputs are from 3.3 V components, this pin should be connected to 3.3 V.

V

SS

GROUND pins intended for external connection to a V

SS

 board plane.

NC

NO CONNECT pins. Do not make any system connections to these pins.

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 Advance Information Datasheet

21

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 5. 

Pin Description — Interrupt Unit Signals 

NAME

TYPE

DESCRIPTION

XINT7:0

I

A(E/L)

EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0 

pins can be configured in three modes:

Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs 

can be programmed to be level (low) or edge (falling) sensitive.

Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins 

are level sensitive in this mode.

Mixed Mode:

 

The XINT7:5 pins act as dedicated sources and the XINT4:0 pins act 

as the five most significant bits of a vectored source. The least significant bits of the 

vectored source are set to 010

2

 internally.

Unused external interrupt pins should be connected to V

CC

.

NMI

I

A(E)

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. 

NMI is the highest priority interrupt source and is falling edge-triggered. If NMI is 

unused, it should be connected to V

CC

.

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80960JA/JF/JD/JT 3.3 V Microprocessor

22

 

 Advance Information Datasheet

3.1.2

80960Jx 132-Lead PGA Pinout

Figure 3.

132-Lead Pin Grid Array Bottom View - Pins Facing Up

AD6

AD11

AD13

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

AD18

AD19

AD22

AD25

AD3

AD7

AD10

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

AD20

AD24

AD26

AD27

AD0

AD4

AD8

AD9

AD12

AD14

AD15

AD16

AD17

AD21

AD23

AD29

AD30

NC

AD28

BE3

BE2

AD31

V

SS

V

CC

BE1

V

SS

V

CC

BE0

V

SS

V

CC

ALE

V

CC

BSTAT

V

SS

V

CC

V

SS

V

CC

DT/R

V

SS

V

CC

V

CC

AD1

V

CC

V

SS

V

CC

V

SS

NC

CLKIN

V

SS

VCCPLL

V

CC

V

SS

NC

V

CC

RDYRCV

V

CC

RESET

V

CC

V

SS

AD5

AD2

V

SS

TDI

XINT0

NC

A2

WIDTH/

ADS

A3

XINT1

TMS

XINT2

NC

STEST

TRST

HOLD

NC

FAIL

VCC5

BLAST

LOCK/ HOLDA

TCK

XINT3

XINT5

XINT7

NMI

V

CC

V

CC

V

CC

V

CC

NC

NC

ALE

XINT6

V

SS

V

SS

V

SS

V

SS

NC

TDO

WIDTH/

D/C

W/R

XINT4

P

N

M

L

K

J

H

G

F

E

D

C

B

A

P

N

M

L

K

J

H

G

F

E

D

C

B

A

14

13

12

11

10

9

8

7

6

5

4

3

2

1

14

13

12

11

10

9

8

7

6

5

4

3

2

1

V

SS

DEN

V

SS

HLTD1

HLTD0

ONCE

background image

 Advance Information Datasheet

23

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 4.

132-Lead Pin Grid Array Top View - Pins Facing Down

AD6

AD11 AD13

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

AD18

AD19 AD22

AD25

AD3

AD7

AD10

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

AD20

AD24 AD26

AD27

AD0

AD4

AD8

AD9

AD12

AD14 AD15

AD16

AD17

AD21 AD23

AD29

AD30

NC

AD28

BE3

BE2

AD31

V

SS

V

CC

BE1

V

SS

V

CC

BE0

V

SS

V

CC

ALE

V

CC

BSTAT V

SS

V

CC

V

SS

V

CC

DT/R

V

SS

V

CC

V

CC

AD1

V

CC

V

SS

V

CC

V

SS

NC

CLKIN

V

SS

VCCPLL

V

CC

V

SS

NC

V

CC

RDYRCV

V

CC

RESET

V

CC

V

SS

AD5

AD2

V

SS

TDI

XINT0

NC

A2

WIDTH/

ADS

A3

XINT1

TMS

XINT2

NC

STEST TRST

HOLD

NC

FAIL

VCC5

BLAST

LOCK/

HOLDA

TCK XINT3

XINT5 XINT7

NMI

V

CC

V

CC

V

CC

V

CC

NC

NC

ALE

XINT6

V

SS

V

SS

V

SS

V

SS

NC

TDO

WIDTH/

D/C

W/R

XINT4

P

N

M

L

K

J

H

G

F

E

D

C

B

A

P

N

M

L

K

J

H

G

F

E

D

C

B

A

14

13

12

11

10

9

8

7

6

5

4

3

2

1

14

13

12

11

10

9

8

7

6

5

4

3

2

1

V

SS

DEN

V

SS

HLTD1

HLTD0

ONCE

i

© 19xx

A80960Jx

XXXXXXXX SS

background image

80960JA/JF/JD/JT 3.3 V Microprocessor

24

 

 Advance Information Datasheet

Table 6. 

132-Lead PGA Pinout — In Signal Order 

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

A2

C5

AD31

K3

TDO

B4

V

SS

B9

A3

C4

ADS

A1

TMS

A14

V

SS

D2

AD0

M14

ALE

G3

TRST

C12

V

SS

D13

AD1

L13

ALE

A3

V

CC

A6

V

SS

E2

AD2

K12

BE0

H3

V

CC

A7

V

SS

E13

AD3

N14

BE1

J3

V

CC

A8

V

SS

F2

AD4

M13

BE2

L1

V

CC

A9

V

SS

F13

AD5

L12

BE3

L2

V

CC

D1

V

SS

G2

AD6

P14

BLAST

C3

V

CC

D14

V

SS

G13

AD7

N13

BSTAT

F3

V

CC

E1

V

SS

H2

AD8

M12

CLKIN

H14

V

CC

E14

V

SS

H13

AD9

M11

D/C

B2

V

CC

F1

V

SS

J2

AD10

N12

DEN

E3

V

CC

F14

V

SS

J13

AD11

P13

DT/R

D3

V

CC

G1

V

SS

K2

AD12

M10

FAIL

C6

V

CC

G14

V

SS

K13

AD13

P12

HOLD

C9

V

CC

H1

V

SS

N5

AD14

M9

HOLDA

C2

V

CC

J1

V

SS

N6

AD15

M8

LOCK/ONCE

C1

V

CC

J14

V

SS

N7

AD16

M7

NC

A4

V

CC

K1

V

SS

N8

AD17

M6

NC

A5

V

CC

K14

V

SS

N9

AD18

P4

NC

B5

V

CC

L14

V

SS

N10

AD19

P3

NC

B14

V

CC

P5

V

SS

N11

AD20

N4

NC

C8

V

CC

P6

W/R

B1

AD21

M5

NC

C14

V

CC

P7

WIDTH/HLTD0

B3

AD22

P2

NC

G12

V

CC

P8

WIDTH/HLTD1

A2

AD23

M4

NC

J12

V

CC

P9

XINT0

C11

AD24

N3

NC

M3

V

CC

P10

XINT1

C10

AD25

P1

NMI

A10

V

CC

P11

XINT2

A13

AD26

N2

RDYRCV

F12

VCCPLL

H12

XINT3

B12

AD27

N1

RESET

E12

VCC5

C7

XINT4

B11

AD28

L3

STEST

C13

V

SS

B6

XINT5

A12

AD29

M2

TCK

B13

V

SS

B7

XINT6

B10

AD30

M1

TDI

D12

V

SS

B8

XINT7

A11

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

background image

 Advance Information Datasheet

25

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 7. 

132-Lead PGA Pinout — In Pin Order 

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

A1

ADS

C6

FAIL

H1

V

CC

M10

AD12

A2

WIDTH/HLTD1

C7

VCC5

H2

V

SS

M11

AD9

A3

ALE

C8

NC

H3

BE0

M12

AD8

A4

NC

C9

HOLD

H12

VCCPLL

M13

AD4

A5

NC

C10

XINT1

H13

V

SS

M14

AD0

A6

V

CC

C11

XINT0

H14

CLKIN

N1

AD27

A7

V

CC

C12

TRST

J1

V

CC

N2

AD26

A8

V

CC

C13

STEST

J2

V

SS

N3

AD24

A9

V

CC

C14

NC

J3

BE1

N4

AD20

A10

NMI

D1

V

CC

J12

NC

N5

V

SS

A11

XINT7

D2

V

SS

J13

V

SS

N6

V

SS

A12

XINT5

D3

DT/R

J14

V

CC

N7

V

SS

A13

XINT2

D12

TDI

K1

V

CC

N8

V

SS

A14

TMS

D13

V

SS

K2

V

SS

N9

V

SS

B1

W/R

D14

V

CC

K3

AD31

N10

V

SS

B2

D/C

E1

V

CC

K12

AD2

N11

V

SS

B3

WIDTH/HLTD0

E2

V

SS

K13

V

SS

N12

AD10

B4

TDO

E3

DEN

K14

V

CC

N13

AD7

B5

NC

E12

RESET

L1

BE2

N14

AD3

B6

V

SS

E13

V

SS

L2

BE3

P1

AD25

B7

V

SS

E14

V

CC

L3

AD28

P2

AD22

B8

V

SS

F1

V

CC

L12

AD5

P3

AD19

B9

V

SS

F2

V

SS

L13

AD1

P4

AD18

B10

XINT6

F3

BSTAT

L14

V

CC

P5

V

CC

B11

XINT4

F12

RDYRCV

M1

AD30

P6

V

CC

B12

XINT3

F13

V

SS

M2

AD29

P7

V

CC

B13

TCK

F14

V

CC

M3

NC

P8

V

CC

B14

NC

G1

V

CC

M4

AD23

P9

V

CC

C1

LOCK/ONCE

G2

V

SS

M5

AD21

P10

V

CC

C2

HOLDA

G3

ALE

M6

AD17

P11

V

CC

C3

BLAST

G12

NC

M7

AD16

P12

AD13

C4

A3

G13

V

SS

M8

AD15

P13

AD11

C5

A2

G14

V

CC

M9

AD14

P14

AD6

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

background image

80960JA/JF/JD/JT 3.3 V Microprocessor

26

 

 Advance Information Datasheet

3.1.3

80960Jx 132-Lead PQFP Pinout

Figure 5.

132-Lead PQFP - Top View

AD

8

AD

7

AD

6

AD

5

AD

4

V

CC

 (I/O)

V

SS

 (I/O)

AD

3

AD

2

AD

1

AD

0

V

CC

 (I/O)

V

CC

 (C

or

e)

V

SS

 (C

or

e)

V

CC

 (C

or

e)

V

SS

 (C

or

e)

VCCP

L

L

V

CC

 (C

L

K

)

NC

NC

RDYRCV

V

SS

 (C

or

e

)

RESE

T

NC

ST

E

S

T

V

CC

 (I/O)

TD

I

V

SS

(I/O)

AD2

7

V

CC

 (

I/O)

V

SS

 (I/O)

AD2

8

AD2

9

AD3

0

AD3

1

V

CC

 (

C

ore)

V

SS

 (C

or

e)

V

CC

 (

I/O)

V

SS

 (I/O)

BE

3

BE

2

BE

1

BE

0

BS

T

A

T

LOC

K

/ONCE

V

CC

 (

I/O)

V

SS

 (I/O)

V

CC

 (

C

ore)

V

SS

 (C

or

e)

AL

E

HOL

D

A

DEN

DT

/R

V

CC

 (

I/O)

V

SS

 (I/O)

V

CC

 (

C

ore)

V

SS

 (C

or

e)

W/

R

ADS

D/C

BL

A

S

T

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

10

0

101

102

103

104

105

106

107

108

109

11

0

111

11

2

11

3

11

4

11

5

11

6

11

7

11

8

11

9

120

121

122

123

124

125

126

127

128

129

130

131

132

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

TRST

TCK

TMS

HOLD

XINT0

XINT1

XINT2

XINT3

V

CC

 (I/O)

V

SS

 (I/O)

XINT4

XINT5

XINT6

XINT7

NMI

V

CC

 (Core)

V

SS

 (Core)

NC

NC

VCC5

NC

NC

FAIL

ALE

TDO

V

CC

 (I/O)

V

SS

(I/O)

WIDTH/HLTD1

V

CC

(Core)

V

SS

 (Core)

WIDTH/HLTD0

A2

A3

AD9

V

CC

 (I/O)

AD10

V

SS

 (I/O)

V

CC

 (I/O)

AD11

V

SS

 (I/O)

V

CC

 (Core)

V

SS

 (Core)

AD12

AD13

AD14

AD15

V

CC

 (I/O)

V

SS

 (I/O)

AD16

AD17

AD18

AD19

NC

V

CC

 (I/O)

AD22

AD25

AD21

AD20

AD24

AD26

AD23

V

SS

 (I/O)

V

CC

 (Core)

V

CC

 (I/O)

V

SS

 (Core)

V

SS

 (I/O)

V

SS

 (I/O

)

CL

K

IN

V

SS

 (C

L

K

)

NC

V

CC

 (

C

ore)

i

XXXXXXXX SS

© 19xx

i960

®

NG80960Jx

background image

 Advance Information Datasheet

27

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 8. 

132-Lead PQFP Pinout — In Signal Order 

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

AD31

60

ALE

24

V

CC

 (Core)

47

V

SS 

(Core)

124

AD30

61

ADS

36

V

CC

 (Core)

59

V

SS

 (I/O)

10

AD29

62

A3

33

V

CC

 (Core)

74

V

SS

 (I/O)

27

AD28

63

A2

32

V

CC

 (Core)

92

V

SS 

(I/O)

40

AD27

66

BE3

55

V

CC

 (Core)

113

V

SS 

(I/O)

48

AD26

68

BE2

54

V

CC

 (Core)

115

V

SS 

(I/O)

56

AD25

69

BE1

53

V

CC 

(Core)

123

V

SS 

(I/O)

64

AD24

70

BE0

52

V

CC

 (I/O)

9

V

SS 

(I/O)

71

AD23

75

WIDTH/HLTD1

28

V

CC

 (I/O)

26

V

SS 

(I/O)

79

AD22

76

WIDTH/HLTD0

31

V

CC 

(I/O)

41

V

SS 

(I/O)

85

AD21

77

D/C

35

V

CC 

(I/O)

49

V

SS 

(I/O)

93

AD20

78

W/R

37

V

CC 

(I/O)

57

V

SS 

(I/O)

97

AD19

81

DT/R

42

V

CC 

(I/O)

65

V

SS 

(I/O)

106

AD18

82

DEN

43

V

CC 

(I/O)

72

V

SS 

(I/O)

112

AD17

83

BLAST

34

V

CC 

(I/O)

80

V

SS 

(I/O)

131

AD16

84

RDYRCV

132

V

CC 

(I/O)

86

NC

18

AD15

87

LOCK/ONCE

50

V

CC 

(I/O)

94

NC

19

AD14

88

HOLD

4

V

CC 

(I/O)

98

NC

21

AD13

89

HOLDA

44

V

CC 

(I/O)

105

NC

22

AD12

90

BSTAT

51

V

CC 

(I/O)

111

NC

67

AD11

95

CLKIN

117

V

CC 

(I/O)

129

NC

121

AD10

96

RESET

125

VCCPLL

119

NC

122

AD9

99

STEST

128

VCC5

20

NC

126

AD8

100

FAIL

23

V

SS

 (CLK)

118

NC

127

AD7

101

TCK

2

V

SS

 (Core)

17

XINT7

14

AD6

102

TDI

130

V

SS

 (Core)

30

XINT6

13

AD5

103

TDO

25

V

SS

 (Core)

38

XINT5

12

AD4

104

TRST

1

V

SS

 (Core)

46

XINT4

11

AD3

107

TMS

3

V

SS

 (Core)

58

XINT3

8

AD2

108

V

CC

 (CLK)

120

V

SS

 (Core)

73

XINT2

7

AD1

109

V

CC

 (Core)

16

V

SS

 (Core)

91

XINT1

6

AD0

110

V

CC

 (Core)

29

V

SS

 (Core)

114

XINT0

5

ALE

45

V

CC

 (Core)

39

V

SS

 (Core)

116

NMI

15

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

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80960JA/JF/JD/JT 3.3 V Microprocessor

28

 

 Advance Information Datasheet

Table 9. 

132-Lead PQFP Pinout — In Pin Order

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

1

TRST

34

BLAST

67

NC

100

AD8

2

TCK

35

D/C

68

AD26

101

AD7

3

TMS

36

ADS

69

AD25

102

AD6

4

HOLD

37

W/R

70

AD24

103

AD5

5

XINT0

38

V

SS

 (Core)

71

V

SS 

(I/O)

104

AD4

6

XINT1

39

V

CC 

(Core)

72

V

CC 

(I/O)

105

V

CC 

(I/O)

7

XINT2

40

V

SS 

(I/O)

73

V

SS 

(Core)

106

V

SS 

(I/O)

8

XINT3

41

V

CC 

(I/O)

74

V

CC 

(Core)

107

AD3

9

V

CC 

(I/O)

42

DT/R

75

AD23

108

AD2

10

V

SS 

(I/O)

43

DEN

76

AD22

109

AD1

11

XINT4

44

HOLDA

77

AD21

110

AD0

12

XINT5

45

ALE

78

AD20

111

V

CC 

(I/O)

13

XINT6

46

V

SS 

(Core)

79

V

SS 

(I/O)

112

V

SS 

(I/O)

14

XINT7

47

V

CC 

(Core)

80

V

CC 

(I/O)

113

V

CC 

(Core)

15

NMI

48

V

SS 

(I/O)

81

AD19

114

V

SS 

(Core)

16

V

CC 

(Core)

49

V

CC 

(I/O)

82

AD18

115

V

CC 

(Core)

17

V

SS 

(Core)

50

LOCK/ONCE

83

AD17

116

V

SS 

(Core)

18

NC

51

BSTAT

84

AD16

117

CLKIN

19

NC

52

BE0

85

V

SS 

(I/O)

118

V

SS 

(CLK)

20

VCC5

53

BE1

86

V

CC 

(I/O)

119

VCCPLL

21

NC

54

BE2

87

AD15

120

V

CC (CLK)

22

NC

55

BE3

88

AD14

121

NC

23

FAIL

56

V

SS 

(I/O)

89

AD13

122

NC

24

ALE

57

V

CC 

(I/O)

90

AD12

123

V

CC 

(Core)

25

TDO

58

V

SS 

(Core)

91

V

SS 

(Core)

124

V

SS

 (Core)

26

V

CC 

(I/O)

59

V

CC 

(Core)

92

V

CC 

(Core)

125

RESET

27

V

SS 

(I/O)

60

AD31

93

V

SS 

(I/O)

126

NC

28

WIDTH/HLTD1

61

AD30

94

V

CC 

(I/O)

127

NC

29

V

CC 

(Core)

62

AD29

95

AD11

128

STEST

30

V

SS 

(Core)

63

AD28

96

AD10

129

V

CC 

(I/O)

31

WIDTH/HLTD0

64

V

SS 

(I/O)

97

V

SS 

(I/O)

130

TDI

32

A2

65

V

CC 

(I/O)

98

V

CC 

(I/O)

131

V

SS 

(I/O)

33

A3

66

AD27

99

AD9

132

RDYRCV

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

background image

 Advance Information Datasheet

29

80960JA/JF/JD/JT 3.3 V Microprocessor

3.1.4

80960Jx 196-Ball MPBGA Pinout

Figure 6.

196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up

NC

AD8

V

CC

AD13

AD15

V

CC

AD18

V

CC

AD22

V

CC

NC

V

CC

AD28

NC

AD4

AD7

AD9

AD10

AD12

AD14

AD17

AD20

AD23

V

CC

AD29

AD27

AD30

V

CC

AD2

AD6

AD11

V

CC

V

CC

AD16

AD19

AD21

AD24

AD25

AD26

AD31

NC

NC

NC

NC

NC

V

CC

NC

NC

V

CC

NC

NC

V

CC

NC

NC

BE3

BE1

BSTAT

BE0

V

CC

LOCK/

ALE

V

CC

DEN

HOLDA

AD1

AD0

V

CC

V

CC

VCCPLL

V

CC

V

CC

NC

CLKIN

NC

NC

V

CC

NC

RESET

TDI

STEST

NC

RDYRCV

NC

AD5

V

CC

V

CC

NC

XINT0

HOLD

A3

ADS

NC

NC

XINT2

NC

V

CC

TCK

TRST

TMS

V

CC

VCC5

V

CC

ALE

NC

DT/R

V

CC

XINT3

XINT1

XINT5

XINT7

NMI

NC

NC

FAIL

WIDTH1

WIDTH0

V

CC

BLAST

NC

XINT4

NC

TDO

V

CC

A2

NC

NC

D/C

W/R

XINT6

P

N

M

L

K

J

H

G

F

E

D

C

B

A

P

N

M

L

K

J

H

G

F

E

D

C

B

A

14

13

12

11

10

9

8

7

6

5

4

3

2

1

14

13

12

11

10

9

8

7

6

5

4

3

2

1

BE2

V

CC

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

AD3

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

ONCE

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80960JA/JF/JD/JT 3.3 V Microprocessor

30

 

 Advance Information Datasheet

Figure 7.

196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down

P

N

M

L

K

J

H

G

F

E

D

C

B

A

P

N

M

L

K

J

H

G

F

E

D

C

B

A

14

13

12

11

10

9

8

7

6

5

4

3

2

1

14

13

12

11

10

9

8

7

6

5

4

3

2

1

NC

AD8

V

CC

AD13

AD15

V

CC

AD18

V

CC

AD22

V

CC

NC

V

CC

AD28

NC

AD4

AD7

AD9

AD10

AD12

AD14

AD17

AD20

AD23

V

CC

AD29

AD27

AD30

V

CC

AD2

AD6

AD11

V

CC

V

CC

AD16

AD19

AD21

AD24

AD25

AD26

AD31

NC

NC

NC

NC

NC

V

CC

NC

NC

V

CC

NC

NC

V

CC

NC

NC

BE3

BE1

BSTAT

BE0

V

CC

LOCK/

ALE

V

CC

DEN

HOLDA

AD1

AD0

V

CC

V

CC

VCCPLL V

CC

V

CC

NC

CLKIN

NC

NC

V

CC

NC

RESET

TDI

STEST

NC

RDYRCV NC

AD5

V

CC

V

CC

NC

XINT0

HOLD

A3

ADS

NC

NC

XINT2

NC

V

CC

TCK

TRST

TMS

V

CC

VCC5

V

CC

ALE

NC

DT/R

V

CC

XINT3 XINT1

XINT5 XINT7

NMI

NC

NC

FAIL WIDTH1 WIDTH0 V

CC

BLAST

NC

XINT4

NC

TDO

V

CC

A2

NC

NC

D/C

W/R

XINT6

BE2

V

CC

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

AD3

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

ONCE

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 Advance Information Datasheet

31

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 10. 

196-Ball MPBGA Pinout — In Signal Order  (Sheet 1 of 2)

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

A2

N5

BE0

J2

NC

M4

V

CC

J1

A3

M5

BE1

H1

NC

N3

V

CC

K3

AD0

D13

BE2

H2

NC

N4

V

CC

K13

AD1

D14

BE3

H3

NC

N8

V

CC

L3

AD2

C14

BLAST

P3

NC

N10

V

CC

M2

AD3

D11

BSTAT

J3

NC

P1

V

CC

M6

AD4

B14

CLKIN

G13

NC

P8

V

CC

M9

AD5

D12

DEN

L2

NC

P9

V

CC

N6

AD6

C13

D/C

N2

NC

P14

V

CC

P4

AD7

B13

DT/R

M1

NMI

P10

V

CC

P13

AD8

A13

FAIL

P7

RDYRCV

L14

VCCPLL

F14

AD9

B12

HOLD

N14

RESET

J14

V

SS

D4

AD10

B11

HOLDA

L1

STEST

K14

V

SS

D5

AD11

C12

LOCK/ONCE

K2

TCK

M14

V

SS

D6

AD12

B10

NC

A1

TDI

J12

V

SS

D7

AD13

A11

NC

A4

TDO

N7

V

SS

D8

AD14

B9

NC

A14

TMS

M12

V

SS

D9

AD15

A10

NC

C1

TRST

M13

V

SS

D10

AD16

C9

NC

C3

VCC5

M8

V

SS

E4

AD17

B8

NC

D1

V

CC

A3

V

SS

E5

AD18

A8

NC

D2

V

CC

A5

V

SS

E6

AD19

C8

NC

D3

V

CC

A7

V

SS

E7

AD20

B7

NC

E1

V

CC

A9

V

SS

E8

AD21

C7

NC

E2

V

CC

A12

V

SS

E9

AD22

A6

NC

F1

V

CC

B1

V

SS

E10

AD23

B6

NC

F2

V

CC

B5

V

SS

E11

AD24

C6

NC

G1

V

CC

C10

V

SS

F4

AD25

C5

NC

G2

V

CC

C11

V

SS

F5

AD26

C4

NC

G12

V

CC

E3

V

SS

F6

AD27

B3

NC

G14

V

CC

E12

V

SS

F7

AD28

A2

NC

H12

V

CC

E13

V

SS

F8

AD29

B4

NC

H14

V

CC

E14

V

SS

F9

AD30

B2

NC

J13

V

CC

F3

V

SS

F10

AD31

C2

NC

K12

V

CC

F12

V

SS

F11

ADS

P2

NC

L12

V

CC

F13

V

SS

G4

ALE

K1

NC

L13

V

CC

G3

V

SS

G5

ALE

M7

NC

M3

V

CC

H13

V

SS

G6

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

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80960JA/JF/JD/JT 3.3 V Microprocessor

32

 

 Advance Information Datasheet

VSS

G7

V

SS

H11

V

SS

K7

V

SS

L11

VSS

G8

V

SS

J4

V

SS

K8

WIDTH0

P5

VSS

G9

V

SS

J5

V

SS

K9

WIDTH1

P6

VSS

G10

V

SS

J6

V

SS

K10

W/R

N1

VSS

G11

V

SS

J7

V

SS

K11

XINT0

M11

VSS

H4

V

SS

J8

V

SS

L5

XINT1

N12

VSS

H5

V

SS

J9

V

SS

L6

XINT2

M10

VSS

H6

V

SS

J10

V

SS

L7

XINT3

N13

VSS

H7

V

SS

J11

V

SS

L8

XINT4

N9

VSS

H8

V

SS

K4

V

SS

L9

XINT5

P12

VSS

H9

V

SS

K5

V

SS

L10

XINT6

N11

VSS

H10

V

SS

K6

V

SS

L4

XINT7

P11

Table 10. 

196-Ball MPBGA Pinout — In Signal Order  (Sheet 2 of 2)

Signal

Pin

Signal

Pin

Signal

Pin

Signal

Pin

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

background image

 Advance Information Datasheet

33

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 11. 

196-Ball MPBGA Pinout — In Pin Order  (Sheet 1 of 2)

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

A1

NC

C11

V

CC

F7

V

SS

J3

BSTAT

A2

AD28

C12

AD11

F8

V

SS

J4

V

SS

A3

V

CC

C13

AD6

F9

V

SS

J5

V

SS

A4

NC

C14

AD2

F10

V

SS

J6

V

SS

A5

V

CC

D1

NC

F11

V

SS

J7

V

SS

A6

AD22

D2

NC

F12

V

CC

J8

V

SS

A7

V

CC

D3

NC

F13

V

CC

J9

V

SS

A8

AD18

D4

V

SS

F14

VCCPLL

J10

V

SS

A9

V

CC

D5

V

SS

G1

NC

J11

V

SS

A10

AD15

D6

V

SS

G2

NC

J12

TDI

A11

AD13

D7

V

SS

G3

V

CC

J13

NC

A12

V

CC

D8

V

SS

G4

V

SS

J14

RESET

A13

AD8

D9

V

SS

G5

V

SS

K1

ALE

A14

NC

D10

V

SS

G6

V

SS

K2

LOCK/ONCE

B1

V

CC

D11

AD3

G7

V

SS

K3

V

CC

B2

AD30

D12

AD5

G8

V

SS

K4

V

SS

B3

AD27

D13

AD0

G9

V

SS

K5

V

SS

B4

AD29

D14

AD1

G10

V

SS

K6

V

SS

B5

V

CC

E1

NC

G11

V

SS

K7

V

SS

B6

AD23

E2

NC

G12

NC

K8

V

SS

B7

AD20

E3

V

CC

G13

CLKIN

K9

V

SS

B8

AD17

E4

V

SS

G14

NC

K10

V

SS

B9

AD14

E5

V

SS

H1

BE1

K11

V

SS

B10

AD12

E6

V

SS

H2

BE2

K12

NC

B11

AD10

E7

V

SS

H3

BE3

K13

V

CC

B12

AD9

E8

V

SS

H4

V

SS

K14

STEST

B13

AD7

E9

V

SS

H5

V

SS

L1

HOLDA

B14

AD4

E10

V

SS

H6

V

SS

L2

DEN

C1

NC

E11

V

SS

H7

V

SS

L3

V

CC

C2

AD31

E12

V

CC

H8

V

SS

L4

V

SS

C3

NC

E13

V

CC

H9

V

SS

L5

V

SS

C4

AD26

E14

V

CC

H10

V

SS

L6

V

SS

C5

AD25

F1

NC

H11

V

SS

L7

V

SS

C6

AD24

F2

NC

H12

NC

L8

V

SS

C7

AD21

F3

V

CC

H13

V

CC

L9

V

SS

C8

AD19

F4

V

SS

H14

NC

L10

V

SS

C9

AD16

F5

V

SS

J1

V

CC

L11

V

SS

C10

V

CC

F6

V

SS

J2

BE0

L12

NC

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

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80960JA/JF/JD/JT 3.3 V Microprocessor

34

 

 Advance Information Datasheet

3.2

Package Thermal Specifications

The 80960Jx is specified for operation when T

C

 (case temperature) is within the range of 0°C to 

100°C for PGA, MPBGA and PQFP packages. An extended temperature device is also available in 

a PQFP package with T

C

 -40°C to 100°C. Case temperature may be measured in any environment 

to determine whether the 80960Jx is within its specified operating range. The case temperature 

should be measured at the center of the top surface, opposite the pins.

θ

CA

 is the thermal resistance from case to ambient. Use the following equation to calculate T

A

, the 

maximum ambient temperature to conform to a particular case temperature:

T

A

 = T

C

 - P (

θ

CA

)

Junction temperature (T

J

) is commonly used in reliability calculations. T

J

 can be calculated from 

θ

JC

 (thermal resistance from junction to case) using the following equation:

T

J

 = T

C

 + P (

θ

JC

)

Similarly, if T

A

 is known, the corresponding case temperature (T

C

) can be calculated as follows:

T

C

 = T

A

 + P (

θ

CA

)

Compute P by multiplying I

CC

 from Table 22 and V

CC

. Values for 

θ

JC

 and 

θ

CA

 are given in 

Table 12 for the PGA package, Table 13 for the MPBGA package, and Table 14 for the PQFP 

package. For high speed operation, the processor’s 

θ

JA

 may be significantly reduced by adding a 

heatsink and/or by increasing airflow.

Tables 15, 16, and 17 show the maximum ambient temperature (T

A

) permitted without exceeding 

T

C

 for the PGA, MPBGA, and PQFP packages. The values are based on typical I

CC

 and V

CC

 of 

+3.3 V, with a T

CASE

 of +100°C.

L13

NC

M10

XINT2

N7

TDO

P4

V

CC

L14

RDYRCV

M11

XINT0

N8

NC

P5

WIDTH0

M1

DT/R

M12

TMS

N9

XINT4

P6

WIDTH1

M2

V

CC

M13

TRST

N10

NC

P7

FAIL

M3

NC

M14

TCK

N11

XINT6

P8

NC

M4

NC

N1

W/R

N12

XINT1

P9

NC

M5

A3

N2

D/C

N13

XINT3

P10

NMI

M6

V

CC

N3

NC

N14

HOLD

P11

XINT7

M7

ALE

N4

NC

P1

NC

P12

XINT5

M8

VCC5

N5

A2

P2

ADS

P13

V

CC

M9

V

CC

N6

V

CC

P3

BLAST

P14

NC

Table 11. 

196-Ball MPBGA Pinout — In Pin Order  (Sheet 2 of 2)

Pin

Signal

Pin

Signal

Pin

Signal

Pin

Signal

NOTE: Do not connect any external logic to pins marked NC (no connect pins).

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 Advance Information Datasheet

35

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 12. 

132-Lead PGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Parameter

Airflow — ft./min (m/sec)

0

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.08)

θ

JC

 (Junction-to-Case)

0.7

0.7

0.7

0.7

0.7

0.7

θ

CA

 (Case-to-Ambient) (No Heatsink)

25

19

14

12

11

10

θ

CA

 (Case-to-Ambient) (Omnidirectional Heatsink)

15

9

6

5

4

4

θ

CA

 (Case-to-Ambient) (Unidirectional Heatsink)

16

8

6

5

4

4

NOTES:

1. This table applies to a PGA device plugged into a socket or soldered directly into a board.

2.

θ

JA

 = 

θ

JC

 + 

θ

CA

3.

θ

J-CAP

 = 5.6°C/W (approximate) (no heatsink)

4.

θ

J-PIN

 = 6.4°C/W (inner pins) (approximate) (no heatsink)

5.

θ

J-PIN

 = 6.2°C/W (outer pins) (approximate) (no heatsink)

6.

θ

J-CAP

 = 3°C/W (approximate) (with heatsink)

7.

θ

J-PIN

 = 3.3°C/W (inner pins) (approximate) (with heatsink)

8.

θ

J-PIN

 = 3.3°C/W (outer pins) (approximate) (with heatsink)

Table 13. 

196-Ball MPBGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

Parameter

Airflow — ft./min (m/sec)

0

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.08)

θ

JC

 (Junction-to-Case)

TBD

TBD

TBD

TBD

TBD

TBD

θ

CA

 (Case-to-Ambient) (No Heatsink)

TBD

TBD

TBD

TBD

TBD

TBD

θ

CA

 (Case-to-Ambient) (Omnidirectional Heatsink)

TBD

TBD

TBD

TBD

TBD

TBD

θ

CA

 (Case-to-Ambient) (Unidirectional Heatsink)

TBD

TBD

TBD

TBD

TBD

TBD

θ

JC

θ

JA

θ

J-CAP

θ

CA

θ

J-PIN

TBD

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80960JA/JF/JD/JT 3.3 V Microprocessor

36

 

 Advance Information Datasheet

Table 14. 

132-Lead PQFP Package Thermal Characteristics

Thermal Resistance — °C/Watt

Parameter

Airflow — ft./min (m/sec)

0

(0)

50

(0.25)

100

(0.50)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

θ

JC

 (Junction-to-Case)

4.1

4.3

4.3

4.3

4.3

4.7

4.9

θ

CA

 (Case-to-Ambient -No Heatsink)

23

19

18

16

14

11

9

NOTES:

1. This table applies to a PQFP device soldered directly into board.

2.

θ

JA

 = 

θ

JC

 + 

θ

CA

3.

θ

JL

 = 13°C/W (approx.)

4.

θ

JB

 = 13.5°C/W (approx.)

Table 15. 

Maximum T

at Various Airflows in °C (80960JT)

Airflow-ft/min (m/sec)

f

CLKIN

 (MHz)

0

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.07)

PQFP 

Package

T

A

 without Heatsink

33

25

62

71

73

79

76

82

81

86

85

88

88

91

PGA 

Package

T

A

 without Heatsink

33

25

58

68

68

75

76

82

80

84

81

86

83

87

T

A

 with Omnidirectional 

Heatsink

1

33

25

75

81

85

88

90

92

92

94

93

95

93

95

T

A

 with Unidirectional 

Heatsink

2

33

25

73

79

86

90

90

92

92

94

93

95

93

95

MPBGA 

Package

T

A

 without Heatsink

33

25

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

NOTES:

1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).

2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).

θ

JB

θ

JA

θ

JC

θ

JL

θ

CA

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37

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 16. 

Maximum T

at Various Airflows in °C (80960JD)

Airflow-ft/min (m/sec)

f

CLKIN

 (MHz)

0

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.07)

PQFP 

Package

T

A

 without Heatsink

33

25

20

16.67

61

70

75

79

73

79

82

86

76

82

85

87

81

86

88

90

85

88

90

92

86

90

91

93

PGA 

Package

T

A

 without Heatsink

33

25

20

16.67

58

68

73

78

68

75

79

83

76

82

85

87

80

84

87

89

81

86

88

90

83

87

89

91

T

A

 with Omnidirectional 

Heatsink

1

33

25

20

16.67

75

81

84

87

85

88

90

92

90

92

93

95

92

94

95

96

93

95

96

96

93

95

96

96

T

A

 with Unidirectional 

Heatsink

2

33

25

20

16.67

73

79

82

86

86

90

91

93

90

92

93

95

92

94

95

96

93

95

96

96

93

96

96

96

MPBGA 

Package

T

A

 without Heatsink

25

20

16.67

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

NOTES:

1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).

2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).

Table 17. 

Maximum T

at Various Airflows in °C (80960JA/JF)

Airflow-ft/min (m/sec)

f

CLKIN

 (MHz)

0

(0)

200

(1.01)

400

(2.03)

600

(3.04)

800

(4.06)

1000

(5.07)

PQFP 

Package

For NG80960JA/JF

T

A

 without Heatsink

33

25

16

79

84

89

86

89

92

87

90

93

90

92

95

92

94

96

93

94

96

For TG80960JA-25

T

A

 without Heatsink

25

84

89

90

92

94

94

PGA 

Package

T

A

 without Heatsink

33

25

16

78

83

88

83

87

91

87

90

93

89

92

94

90

92

95

91

93

95

T

A

 with Omnidirectional 

Heatsink

1

33

25

16

87

90

93

92

94

96

95

96

97

96

97

98

96

97

98

96

97

98

T

A

 with Unidirectional 

Heatsink

2

33

25

16

86

89

92

93

94

96

95

96

97

96

97

98

96

97

98

96

97

98

MPBGA 

Package

T

A

 without Heatsink

33

25

16

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

NOTES:

1. 0.248” high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin spacing).

2. 0.250” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).

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80960JA/JF/JD/JT 3.3 V Microprocessor

38

 

 Advance Information Datasheet

3.3

Thermal Management Accessories

The following is a list of suggested sources for 80960Jx thermal solutions. This is neither an 

endorsement or a warranty of the performance of any of the listed products and/or companies.

3.3.1

Heatsinks

1. Thermalloy, Inc.

2021 West Valley View Lane

Dallas, TX 75234-8993

(972) 243-4321 

2. Wakefield Engineering 

60 Audubon Road

Wakefield, MA 01880

(617) 245-5900

3. Aavid Thermal Technologies, Inc.

One Kool Path

Laconia, NH 03247-0400

(603) 528-3400

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 Advance Information Datasheet

39

80960JA/JF/JD/JT 3.3 V Microprocessor

4.0

Electrical Specifications

4.1

Absolute Maximum Ratings

Warning:

Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. 

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended 

and extended exposure beyond the “Operating Conditions” may affect device reliability.

Note:

This document contains information on products in the sampling and initial production phases of 

development. It is valid for the devices indicated in the revision history. The specifications within 

this data sheet are subject to change without notice. Verify with your local Intel sales office that 

you have the latest data sheet before finalizing a design.

4.2

Operating Conditions

Table 19 indicates the operating conditions for the 80960Jx.

Table 18. 

Absolute Maximum Ratings

Parameter

Maximum Rating

Storage Temperature

–65

o

C to +150

o

C

Case Temperature Under Bias

–65

o

C to +110

o

C

Supply Voltage wrt. V

SS

–0.5 V to + 4.6 V

Voltage on VCC5 wrt. V

SS

–0.5 V to + 6.5 V

Voltage on Other Pins wrt. V

SS

–0.5 V to V

CC

 + 0.5 V

Table 19. 

80960Jx Operating Conditions 

Symbol

Parameter

Min

Max

Units

Notes

V

CC

Supply Voltage

3.15

3.45

V

VCC5

Input Protection Bias

3.15

5.5

V

(1)

f

CLKIN

Input Clock Frequency

80960JT-100

80960JT-75

80960JD-66

80960JD-50

80960JD-40

80960JD-33

80960JA/JF-33

80960JA/JF-25

80960JA/JF-16

15

15

12

12

12

12

12

12

12

33.3

25

33.3

25

20

16.67

33.3

25

16

MHz

T

C

Operating Case Temperature 

PGA, MPBGA, and PQFP

Extended temp PQFP (TG80960JA-25)

0

-40

100

100

°C

NOTE:

1. See Section 4.4, “VCC5 Pin Requirements (VDIFF)” on page 40.

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80960JA/JF/JD/JT 3.3 V Microprocessor

40

 

 Advance Information Datasheet

4.3

Connection Recommendations

For clean on-chip power distribution, V

CC

 and V

SS

 pins separately feed the device’s functional units. 

Power and ground connections must be made to all 80960Jx power and ground pins. On the circuit board, 

every V

CC

 pin should connect to a power plane and every V

SS

 pin should connect to a ground plane. Place 

liberal decoupling capacitance near the 80960Jx, since the processor can cause transient power surges. 

Pay special attention to the Test Reset (TRST) pin. It is essential that the JTAG Boundary Scan Test Access 

Port (TAP) controller initializes to a known state whether it will be used or not. If the JTAG Boundary Scan 

function will be used, connect a pulldown resistor between the TRST pin and V

SS

. If the JTAG Boundary 

Scan function will not be used (even for board-level testing), connect the TRST pin to V

SS

.

Do not connect the TDI, TDO, and TCK pins if the TAP Controller will not be used.

Note:

Pins identified as NC must not be connected in the system.

4.4

VCC5 Pin Requirements (VDIFF)

In 3.3 V only systems where the 80960Jx input pins are driven from 3.3 V logic, connect the VCC5

 

pin directly to the 3.3 V V

CC

 plane.

In mixed voltage systems where the processor is powered by 3.3 V and interfaces with 5 V 

components, VCC5 must be connected to 5 V. This allows proper 5 V tolerant buffer operation, 

and prevents damage to the input pins. The voltage differential between the 80960Jx VCC5 pin and 

its 3.3 V V

CC

 pins must not exceed 2.25 V. If this requirement is not met, current flow through the 

pin may exceed the value at which the processor is damaged. Instances when the voltage can 

exceed 2.25 V is during power up or power down, where one source reaches its level faster than the 

other, briefly causing an excess voltage differential. Another instance is during steady-state 

operation, where the differential voltage of the regulator (provided a regulator is used) cannot be 

maintained within 2.25 V. Two methods are possible to prevent this from happening:

Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V, or,

As shown in Figure 8, place a 100

 resistor in series with the VCC5 pin to limit the current 

through VCC5.

If the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple and 

reliable method for limiting current. The resistor can also prevent damage in the case of a power 

failure, where the 5 V supply remains on and the 3.3 V supply goes to zero. 

 

Figure 8.

VCC5 Current-Limiting Resistor

+5 V (±0.25 V)

VCC5 Pin

100 

(±5%, 0.5 W)

Table 20. 

VDIFF Parameters

Symbol

Parameter

Min

Max

Units

Notes

VDIFF

VCC5-V

CC

 

Difference

2.25

V

VCC5 input should not exceed V

CC

 by more than 2.25 V 

during power-up and power-down, or during 

steady-state operation.

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41

80960JA/JF/JD/JT 3.3 V Microprocessor

4.5

VCCPLL Pin Requirements

To reduce clock skew on the i960 80960Jx processor, the VCCPLL pin for the Phase Lock Loop 

(PLL) circuit is isolated on the pinout. The lowpass filter, as shown in Figure 9, reduces noise 

induced clock jitter and its effects on timing relationships in system designs. The 4.7 µF capacitor 

must be low ESR solid tantalum; the 0.01 µF capacitor must be of the type X7R and the node 

connecting VCCPLL must be as short as possible.

Figure 9.

VCCPLL Lowpass Filter

100

V

CC

(Board Plane)

VCCPLL

(On 80960Jx)

Ω 

(80960JA/JF/JD)

F_CA078A

0.01 µF

4.7 µF 

+

10

Ω 

(80960JT)

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80960JA/JF/JD/JT 3.3 V Microprocessor

42

 

 Advance Information Datasheet

4.6

DC Specifications

Table 21. 

80960Jx DC Characteristics 

Symbol

Parameter

Min

Typ

Max

Units

Notes

V

IL

Input Low Voltage 

-0.3

0.8

V

V

IH

Input High Voltage

2.0

VCC5 + 0.3

V

V

OL

Output Low Voltage

0.4

0.2

V

V

I

OL

 = 3 mA

I

OL

 = 100 µA

V

OH

Output High Voltage

2.4

V

CC

 - 0.2 

V

I

OH

 = -1 mA

I

OH

 = -200 µA

V

OLP

Output Ground Bounce

<0.8

V

(1,2)

C

IN

Input Capacitance

PGA

PQFP

MPBGA

15

15

15

pF

f

CLKIN

 = f

MIN

 (2)

C

OUT

I/O or Output Capacitance

PGA

PQFP

MPBGA

15

15

15

pF

f

CLKIN

 = f

MIN

 (2)

C

CLK

CLKIN Capacitance

PGA

PQFP

MPBGA

15

15

15

pF

f

CLKIN

 = f

MIN

 (2)

NOTES:

1. Typical is measured with V

CC

 = 3.3 V and temperature = 25 °C.

2. Not tested.

Table 22. 

80960Jx I

CC

 Characteristics  (Sheet 1 of 2)

Symbol

Parameter

Typ

Max

Units

Notes

I

LI1

Input Leakage Current for each pin 

except TCK, TDI, TRST and TMS

± 1

µA

 V

IN

  

 V

CC

I

LI2

Input Leakage Current for TCK, TDI, 

TRST and TMS

-140

-250

µA

V

IN

 = 0.45V (1)

I

LO

Output Leakage Current

± 1

µA

0.4 

 V

OUT

 

 V

CC

R

pu

Internal Pull-UP Resistance for 

ONCE, TMS, TDI and TRST

20

30

k

I

CC 

Active 

(Power Supply)

80960JT-100

80960JT-75

80960JD-66

80960JD-50

80960JD-40

80960JD-33

80960JA/JF-33

80960JA/JF-25

80960JA/JF-16

600

450

580

447

367

310

320

260

194

mA

(2,3)

(2,3)

(2,3)

(2,3)

(2,3)

(2,3)

(2,3)

(2,3)

(2,3)

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 Advance Information Datasheet

43

80960JA/JF/JD/JT 3.3 V Microprocessor

I

CC 

Active

(Thermal)

80960JT-100

80960JT-75

80960JD-66

80960JD-50

80960JD-40

80960JD-33

80960JA/JF-33

80960JA/JF-25

80960JA/JF-16

500

380

510

390

320

260

271

215

152

mA

(2,4)

(2,4)

(2,4)

(2,4)

(2,4)

(2,4)

(2,4)

(2,4)

(2,4)

I

CC 

Test

(Power modes)

Reset mode

80960JT-100

80960JT-75

80960JD-66

80960JD-50

80960JD-40

80960JD-33

80960JA/JF-33

80960JA/JF-25

80960JA/JF-16

Halt mode

80960JT-100

80960JT-75

80960JD-66

80960JD-50

80960JD-40

80960JD-33

80960JA/JF-33

80960JA/JF-25

80960JA/JF-16

ONCE mode

450

400

475

425

345

300

250

200

150

50

40

50

40

34

34

31

26

21

10

mA

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

(5)

I

CC5

 Current on the 

VCC5 Pin

80960JT-100

80960JT-75

80960JD-66

80960JD-50

80960JD-40

80960JD-33

80960JA/JF-33

80960JA/JF-25

80960JA/JF-16

200

µA

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

(6)

NOTES:

1. These pins have internal pullup devices. Typical leakage current is not tested.

2. Measured with device operating and outputs loaded to the test condition in Figure 10 “AC Test Load” on 

page 47.

3. I

CC

 Active (Power Supply) value is provided for selecting your system’s power supply. It is measured using 

one of the worst case instruction mixes with V

CC

 = 3.45 V. This parameter is characterized but not tested.

4. I

CC

 Active (Thermal) value is provided for your system’s thermal management. Typical I

CC

 is measured with 

V

CC 

=3.3 V and temperature = 25°C. This parameter is characterized but not tested.

5. I

CC

 Test (Power modes) refers to the I

CC

 values that are tested when the 80960JD is in Reset mode, Halt 

mode or ONCE mode with V

CC

 = 3.45 V.

6. I

CC5

 is tested at V

CC

 = 3.3 V, VCC5 = 5.25 V.

Table 22. 

80960Jx I

CC

 Characteristics  (Sheet 2 of 2)

Symbol

Parameter

Typ

Max

Units

Notes

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80960JA/JF/JD/JT 3.3 V Microprocessor

44

 

 Advance Information Datasheet

4.7

AC Specifications

The 80960Jx AC timings are based upon device characterization.

Table 23. 

80960Jx AC Characteristics (Sheet 1 of 3)

Symbol

Parameter

Min

Max

Unit

Notes

INPUT CLOCK TIMINGS

T

F

CLKIN Frequency

80960JT-100

80960JT-75

80960JD-66

80960JD-50

80960JD-40

80960JD-33

80960JA/JF-33

80960JA/JF-25

80960JA/JF-16

15

15

12

12

12

12

12

12

12

33.3

25

33.3

25

20

16.67

33.3

25

16

MHz

T

C

CLKIN Period

80960JT-100

80960JT-75

80960JD-66

80960JD-50

80960JD-40

80960JD-33

80960JA/JF-33

80960JA/JF-25

80960JA/JF-16

30

40

30

40

50

60

30

40

62.5

66.7

66.7

83.3

83.3

83.3

83.3

83.3

83.3

83.3

ns

T

CS

CLKIN Period Stability

± 

250

ps

(1, 2)

T

CH

CLKIN High Time

8

ns

Measured at 1.5 V 

(1)

T

CL

CLKIN Low Time

8

ns

Measured at 1.5 V 

(1)

T

CR

CLKIN Rise Time

4

ns

0.8 V to 2.0 V (1)

T

CF

CLKIN Fall Time

4

ns

2.0 V to 0.8 V (1)

SYNCHRONOUS OUTPUT TIMINGS

T

OV1

Output Valid Delay, Except ALE/ALE 

Inactive and DT/R for 3.3 V input signals

Same as above, but for 5.5 V input signals

2.5

2.5

13.5

16.5

ns

(3)

T

OV2

Output Valid Delay, DT/R

80960JT

80960JD

80960JA/JF

0.5T

C

 + 7

0.5T

C

 + 7

0.5T

C

 + 4

0.5T

C

 + 9

0.5T

C

 + 9

0.5T

C

 + 18

ns

T

OF

Output Float Delay

2.5

13.5

ns

(4)

NOTE:

See Table 24 on page 47 for note definitions for this table.

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 Advance Information Datasheet

45

80960JA/JF/JD/JT 3.3 V Microprocessor

SYNCHRONOUS INPUT TIMINGS

T

IS1

Input Setup to CLKIN — AD31:0, NMI, 

XINT7:0

80960JT

80960JD

80960JA/JF

6

6

9

ns

(5)

T

IH1

Input Hold from CLKIN — AD31:0, NMI, 

XINT7:0

80960JT

80960JD

80960JA/JF

1.5

1.5

1.0

ns

(5)

T

IS2

Input Setup to CLKIN — RDYRCV and 

HOLD

80960JT

80960JD

80960JA/JF

6.5

6.5

10.0

ns

(6)

T

IH2

Input Hold from CLKIN — RDYRCV and 

HOLD

1

ns

(6)

T

IS3

Input Setup to CLKIN — RESET

80960JT

80960JD

80960JA/JF

7

7

8

ns

(7)

T

IH3

Input Hold from CLKIN — RESET

80960JT

80960JD

80960JA/JF

2

2

1

ns

(7)

T

IS4

Input Setup to RESET — ONCE, STEST

80960JT

80960JD

80960JA/JF

7

7

8

ns

(8)

T

IH4

Input Hold from RESET — ONCE, STEST

80960JT

80960JD

80960JA/JF

2

2

1

ns

(8)

RELATIVE OUTPUT TIMINGS

T

LX

Address Valid to ALE/ALE Inactive

For  3.3 V Data Input Signals

For 5.0 V Data Input Signals

0.5T

C

 - 5

0.5T

C

 - 8

ns

(9)

T

LXL

ALE/ALE Width

0.5T

C

 - 7

ns

Equal Loading (9)

T

LXA

Address Hold from ALE/ALE Inactive

T

DXD

DT/R Valid to DEN Active

BOUNDARY SCAN TEST SIGNAL TIMINGS

T

BSF

TCK Frequency

0.5T

F

 MHz

T

BSCH

TCK High Time

15

ns

Measured at 1.5 V 

(1)

T

BSCL

TCK Low Time

15

ns

Measured at 1.5 V 

(1)

T

BSCR

TCK Rise Time

5

ns

0.8 V to 2.0 V (1)

T

BSCF

TCK Fall Time

5

ns

2.0 V to 0.8 V (1)

Table 23. 

80960Jx AC Characteristics (Sheet 2 of 3)

Symbol

Parameter

Min

Max

Unit

Notes

NOTE:

See Table 24 on page 47 for note definitions for this table.

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80960JA/JF/JD/JT 3.3 V Microprocessor

46

 

 Advance Information Datasheet

T

BSIS1

Input Setup to TCK — TDI, TMS

4

ns

T

BSIH1

Input Hold from TCK — TDI, TMS

6

ns

T

BSOV1

TDO Valid Delay

3

30

ns

(1,10)

T

BSOF1

TDO Float Delay

3

30

ns

(1,10)

T

BSOV2

All Outputs (Non-Test) Valid Delay

3

30

ns

(1,10)

T

BSOF2

All Outputs (Non-Test) Float Delay

3

30

ns

(1,10)

T

BSIS2

Input Setup to TCK — All Inputs 

(Non-Test) 

4

ns

T

BSIH2

Input Hold from TCK — All Inputs 

(Non-Test)

6

ns

Table 23. 

80960Jx AC Characteristics (Sheet 3 of 3)

Symbol

Parameter

Min

Max

Unit

Notes

NOTE:

See Table 24 on page 47 for note definitions for this table.

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 Advance Information Datasheet

47

80960JA/JF/JD/JT 3.3 V Microprocessor

4.7.1

AC Test Conditions and Derating Curves

The AC Specifications in Section 4.7, “AC Specifications” are tested with the 50 pF load indicated 

in Figure 10. Figure 11 shows how timings and output rise and fall times vary with load 

capacitance.

Table 24. 

Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44)

NOTES:

1. Not tested. 

2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter 

frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN 

frequency. 

3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE 

timings, refer to Relative Output Timings in this table.

4. A float condition occurs when the output current becomes less than I

OL

. Float delay is not tested, but is 

designed to be no longer than the valid delay. 

5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI 

and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition 

at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a 

minimum of two CLKIN periods to guarantee recognition.

6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor 

operation.

7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a 

particular clock edge.

8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.

9. Guaranteed by design. May not be 100% tested.

10.Relative to falling edge of TCK.

11.Worst-case T

OV

 condition occurs on I/O pins when pins transition from a floating high input to driving a 

low output state. The Address/Data Bus pins encounter this condition between the last access of a read, 

and the address cycle of a following write. 5 V signals take 3 ns longer to discharge than 3.3 V signals at 

50 pF loads.

Figure 10.

AC Test Load

Output Pin

C

L

 = 50 pF for all signals

C

L

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80960JA/JF/JD/JT 3.3 V Microprocessor

48

 

 Advance Information Datasheet

Note:

The T

LX

 Derating curve applies only when an imbalance in the capacitive load occurs between the 

AD bus and ALE. The T

LX

 derating is based on a 50 pF load on ALE. The derating applies to ALE 

and ALE.

Figure 11.

Output Delay or Hold vs. Load Capacitance

Figure 12.

T

LX

 vs. AD Bus Load Capacitance

AC Timings vs. Load Capacitance

nom + 0

nom + 1

nom + 2

nom + 3

nom + 4

nom + 5

nom + 6

nom + 7

50

100

150

AD Bus Capacitive Load (pF)

Tov (ns)

Rising

Falling

Rise and Fall times are identical.

AC Timings vs. Load Capacitance

nom + 0

nom + 1

nom + 2

nom + 3

nom + 4

nom + 5

nom + 6

nom + 7

50

100

150

AD Bus Capacitive Load (pF)

Tlx (ns)

Rising

Falling

Rise and Fall times are identical.

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 Advance Information Datasheet

49

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 13.

80960JA/JF I

CC

 Active (Power Supply) vs. Frequency

Figure 14.

80960JA/JF I

CC

 Active (Thermal) vs. Frequency

Icc Active (Power Supply) vs Frequency

0

50

100

150

200

250

300

350

12

15

18

21

24

27

30

33

CLKIN Frequency MHz

Icc Active (Pow

e

r Supply) (mA)

I

CC

 Active (Thermal) vs. Frequency

I

CC

 Active (

T

hermal) (

mA)

Icc Active (Thermal) vs. Frequency

0

50

100

150

200

250

300

12

15

18

21

24

27

30

33

CLKIN Frequency MHz

Icc A

c

tive (Ther

m

al) (mA

)

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80960JA/JF/JD/JT 3.3 V Microprocessor

50

 

 Advance Information Datasheet

Figure 15.

80960JD I

CC

 Active (Power Supply) vs. Frequency

Figure 16.

80960JD I

CC

 Active (Thermal) vs. Frequency

Icc Active (Power Supply) vs. Frequency

0

100

200

300

400

500

600

12

15

18

21

24

27

30

33

CLKIN Frequency (MHz)

Icc A

c

tive (Pow

e

r Supply) (mA

)

Icc Active (Thermal) vs. Frequency

0

100

200

300

400

500

600

12

15

18

21

24

27

30

33

CLKIN Frequency (MHz)

Icc A

c

tive (Ther

m

al) (mA

)

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 Advance Information Datasheet

51

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 17.

80960JT I

CC

 Active  (Power Supply) vs. Frequency

Figure 18.

80960JT I

CC

 Active (Thermal) vs. Frequency

Icc Active (Power Supply) vs. Frequency

0

100

200

300

400

500

600

15

18

21

24

27

30

33

CLKIN Frequency (MHz)

Icc Active (Pow

e

r Supply) (mA)

Icc Active (Thermal) vs. Frequency

0

200

400

600

800

1000

15

18

21

24

27

30

33

CLKIN Frequency (MHz)

Icc A

c

tive (Ther

m

al) (mA

)

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80960JA/JF/JD/JT 3.3 V Microprocessor

52

 

 Advance Information Datasheet

4.7.2

AC Timing Waveforms

Figure 19.

CLKIN Waveform

Figure 20.

T

OV1

 Output Delay Waveform

2.0V

1.5V

0.8V

T

CF

T

CH

T

CL

T

C

T

CR

CLKIN

AD31:0,

ALE (active),

ALE (active),

ADS, A3:2,

BE3:0,

WIDTH/HLTD1:0,

D/C, W/R, DEN,

BLAST, LOCK,

HOLDA, BSTAT, FAIL

1.5V

1.5V

1.5V

T

OV1

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 Advance Information Datasheet

53

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 21.

T

OF

 Output Float Waveform

Figure 22.

T

IS1

 and T

IH1

 Input Setup and Hold Waveform

Figure 23.

T

IS2

 and T

IH2

 Input Setup and Hold Waveform

1.5V

1.5V

T

OF

CLKIN

AD31:0,

ALE, ALE

ADS, A3:2,

BE3:0,

WIDTH/HLTD1:0,

D/C, W/R, DT/R,

DEN, BLAST, LOCK

CLKIN

AD31:0

1.5V

1.5V

1.5V

T

IS1

T

IH1

1.5V

NMI

XINT7:0

Valid

CLKIN

Valid

HOLD,

1.5V

1.5V

1.5V

1.5V

1.5V

T

IS2

T

IH2

RDYRCV

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80960JA/JF/JD/JT 3.3 V Microprocessor

54

 

 Advance Information Datasheet

Figure 24.

T

IS3

 and T

IH3

 Input Setup and Hold Waveform

Figure 25.

T

IS4

 and T

IH4

 Input Setup and Hold Waveform

CLKIN

RESET

1.5V

1.5V

T

IH3

T

IS3

RESET

Valid

ONCE,

T

IS4

T

IH4

STEST

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 Advance Information Datasheet

55

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 26.

T

LX

, T

LXL

 and T

LXA

 Relative Timings Waveform

Figure 27.

DT/R and DEN Timings Waveform

CLKIN

ALE

1.5V

1.5V

1.5V

ALE

1.5V

1.5V

AD31:0

Valid

T

LXA

T

a

T

w

/T

d

1.5V

Valid

1.5V

T

LXL

T

LX

CLKIN

DT/R

1.5V

1.5V

1.5V

DEN

Valid

T

DXD

T

a

T

w

/T

d

T

OV1

T

OV2

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80960JA/JF/JD/JT 3.3 V Microprocessor

56

 

 Advance Information Datasheet

Figure 28.

TCK Waveform

Figure 29.

T

BSIS1

 and T

BSIH1

 Input Setup and Hold Waveforms

Figure 30.

T

BSOV1

 and T

BSOF1

 Output Delay and Output Float Waveform

2.0V

1.5V

0.8V

T

BSCH

T

BSCL

T

BSCF

T

BSCR

TCK

TMS

1.5V

1.5V

1.5V

TDI

1.5V

1.5V

Valid

T

BSIS1

T

BSIH1

TCK

1.5V

1.5V

1.5V

T

BSOV1

TDO

Valid

T

BSOF1

1.5V

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 Advance Information Datasheet

57

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 31.

T

BSOV2

 and T

BSOF2

 Output Delay and Output Float Waveform

Figure 32.

T

BSIS2

 and T

BSIH2

 Input Setup and Hold Waveform

TCK

1.5V

1.5V

1.5V

T

BSOV2

Non-Test

Valid

T

BSOF2

Outputs

1.5V

TCK

Non-Test

1.5V

1.5V

1.5V

1.5V

1.5V

Valid

T

BSIS2

T

BSIH2

Inputs

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80960JA/JF/JD/JT 3.3 V Microprocessor

58

 

 Advance Information Datasheet

5.0

Bus Functional Waveforms

Figure 33 through Figure 38 illustrate typical 80960Jx bus transactions. Figure 39 depicts the bus 

arbitration sequence. Figure 40 illustrates the processor reset sequence from the time power is 

applied to the device. Figure 41 illustrates the processor reset sequence when the processor is in 

operation. Figure 42 illustrates the processor ONCE sequence from the time power is applied to the 

device. Figure 44 and Figure 45 also show accesses on 32-bit buses. Table 27 through Table 29 

summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to 

data alignment.

Figure 33.

Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus

CLKIN

AD31:0

ALE

ADS

A3:2

BE3:0

WIDTH1:0

D/C

W/R

DT/R

DEN

RDYRCV

BLAST

ADDR

D

In

Invalid

ADDR

DATA Out

10

10

T

a

T

d

T

r

T

i

T

i

T

a

T

d

T

r

T

i

T

i

F_JF030A

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 Advance Information Datasheet

59

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 34.

Burst Read and Write Transactions Without Wait States, 32-Bit Bus

ADDR

D

D

ADDR

DATA DATA DATA

DATA

1 0

1 0

CLKIN

AD31:0

ALE

ADS

A3:2

BE3:0

WIDTH1:0

D/C

W/R

BLAST

DT/R

DEN

RDYRCV

T

A

T

D

T

D

T

R

T

A

T

D

T

D

T

D

T

D

T

R

In

In

Out

Out

Out

Out

00 or 10

01 or 11

00

01

10

11

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80960JA/JF/JD/JT 3.3 V Microprocessor

60

 

 Advance Information Datasheet

Figure 35.

Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus

ADDR

DATA

1 0

DATA

DATA

DATA

CLKIN

AD31:0

ALE

ADS

A3:2

BE3:0

WIDTH1:0

D/C

W/R

BLAST

DT/R

DEN

RDYRCV

T

A

T

W

T

W

T

D

T

W

T

D

T

W

T

D

T

W

T

D

T

R

Out

Out

Out

Out

F_JF032A

0 0

0 1

1 0

1 1

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61

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 36.

Burst Read and Write Transactions Without Wait States, 8-Bit Bus

ADDR

D

D

ADDR

DATA DATA DATA

DATA

CLKIN

AD31:0

ALE

ADS

A3:2

BE1/A1

WIDTH1:0

D/C

W/R

BLAST

DT/R

DEN

RDYRCV

T

A

T

D

T

D

T

R

T

A

T

D

T

D

T

D

T

D

T

R

00,01,10 or 11

00,01,10 or 11

00

01

10

11

00

00

BE0/A0

In

In

Out

Out

Out

Out

F_JF033A

00 or 10

01 or

 11

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80960JA/JF/JD/JT 3.3 V Microprocessor

62

 

 Advance Information Datasheet

Figure 37.

Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on 

Read, 16-Bit Bus

ADDR

D

D

ADDR

DATA

DATA

CLKIN

AD31:0

ALE

ADS

A3:2

BE3/BHE

WIDTH1:0

D/C

W/R

BLAST

DT/R

DEN

RDYRCV

T

W

T

D

T

D

T

R

T

R

T

A

T

W

T

D

T

D

T

R

00,01,10, or 11

00,01,10, or 11

T

A

BE0/BLE

BE1/A1

01

01

0

1

0

1

Out

Out

In

In

F_JF034A

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 Advance Information Datasheet

63

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 38.

Double Word Read Bus Request, Misaligned One Byte From 

Quad Word Boundary, 32-Bit Bus, Little Endian

T

A

T

D

T

R

T

A

T

D

T

R

T

A

T

D

T

R

T

A

T

D

T

R

CLKIN

AD31:0

ALE

ADS

A3:2

BE3:0

WIDTH1:0

D/C

W/R

BLAST

DT/R

DEN

RDYRCV

00

00

01

10

1 1 0 1

0 0 1 1

0 0 0 0

 

1 1 1 0

1 0

Valid

A

A

A

D

A

D

In

In

D

In

D

In

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80960JA/JF/JD/JT 3.3 V Microprocessor

64

 

 Advance Information Datasheet

Figure 39.

HOLD/HOLDA Waveform For Bus Arbitration

CLKIN

Valid

Outputs:

AD31:0,

ALE, ALE,

ADS, A3:2,

BE3:0,

WIDTH/HLTD1:0,

D/C, W/R,

DT/R, DEN,

BLAST, LOCK

HOLD

HOLDA

~ ~

~ ~

~ ~

~ ~

(Note)

NOTE: HOLD is sampled on the rising edge of CLKIN. The processor asserts HOLDA to grant the bus on the

same edge in which it recognizes HOLD if the last state was T

or the last T

r

 of a bus transaction. Similarly,

Valid

~ ~

~ ~

~ ~

~ ~

~ ~

T

I

 or T

R

T

H

T

H

T

I

 or T

A

the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.

background image

 Advance Information Datasheet

65

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 40.

Cold Reset Waveform

CL

KIN

AL

E

, A

D

S

,

AL

E

,W

/R

,

RE

SET

LOC

K

/

ST

EST

V

CC

 

DT

/R

FA

IL

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

Fi

rs

Bu

Act

ivit

y

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

V

a

lid

~ ~

(Ou

tpu

t)

O

NCE

A

D

3

1

:0

, A

3

:2

,D/C

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

(N

ote

 1)

~ ~

~ ~

Id

le

 (N

o

te 

2)

HO

L

D

~ ~

V

a

lid

 In

put

 (N

o

te 3

)

~ ~

~ ~

~ ~

~ ~

BE3

:0

, DE

N

,

BL

AST

~ ~

~ ~

~ ~

V

a

lid Outp

ut (Not

e

3

)

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

HO

L

D

A

V

1

0

,0

0

0

 CL

KIN p

e

ri

o

d

s

, fo

r PL

L

 sta

b

iliza

tio

n

.

CC a

n

d

 CL

K

IN st

a

b

le

 t

o

 RESET

 Hig

h

, m

in

im

u

m

~ ~

B

u

ilt

-i

n se

lf

-te

s

t (

N

ote

 4)

(I

np

ut)

~ ~

1

. T

he 

pro

c

esso

r a

sser

ts F

A

IL

 du

ri

ng

 bu

ilt

-i

n s

e

lf

-t

es

t.

 If

 s

e

lf

- t

e

s

t pa

s

s

e

s

, t

h

e

 F

A

IL

 p

in

 i

s

 d

eas

sert

ed.

Th

e p

roce

ssor

 al

so

 as

sert

s F

A

IL

du

ring

 th

e bu

s co

nfid

ence

 te

st. If

 the

 bu

s co

nfide

n

ce

 tes

t pa

sses,

 F

A

IL

 i

s

 de

asse

rte

d

 a

n

d

 the

 pr

oce

ssor

 beg

in

s u

s

er

 pr

og

ram

 exe

c

ut

io

n.

No

te

s:

2

. If 

the

 pro

c

ess

o

fai

ls

 b

u

ilt

-i

n

 se

lf

-te

s

t, i

in

it

ia

te

s o

ne 

dum

my 

load

 bu

s ac

cess. 

Th

e l

o

a

d

 a

d

d

ress

 i

ndi

c

a

tes

 the

 po

in

t o

f s

e

lf-te

st fa

ilure

3

. S

ince

 th

e b

u

s i

s

 i

d

le

hol

d

 re

que

sts a

re 

hon

or

ed 

dur

ing 

rese

t a

nd 

bui

lt

-i

n se

lf

-t

est.

~ ~

~ ~

WI

DT

H/

HL

T

D

1

:0

4

. W

h

en 

sel

e

ct

ed,

 bu

ilt

-i

n

 sel

f t

e

st r

e

q

u

ir

e

s

 ap

pro

x

im

a

tel

(i

C

L

K

IN

 p

e

ri

o

d

s)

: 39

3,0

00 

for

 80

960

JT

, 2

07,

000

 fo

r 8

096

0JD

and

 4

1

4

,0

00 

for

 809

60

JA

/JF

.

~ ~

background image

80960JA/JF/JD/JT 3.3 V Microprocessor

66

 

 Advance Information Datasheet

Figure 41.

Warm Reset Waveform

~

~

~

~

Ma

x

imu

m R

E

S

E

T

 Lo

w to

 Rese

t S

ta

te

4

 C

L

KIN Cycle

s

~

~

~

~

~

~

CL

K

IN

A

D

31

:0, 

A

3

:2,

 D/C

ST

EST

RE

SET

 

~

~

~

~

RESET

 H

igh to 

F

irst

 B

u

s

M

in

im

u

m

 RESET

 Lo

w

 T

im

e

 

1

5

 CL

KI

N Cycle

s

~

~

~

~

~

~

~

~

HO

L

D

A

~

~

~

~

~

~

~

~

V

a

lid

AL

E

, A

D

S

, B

E

3

:0

,

DEN

, BL

AST

AL

E,

 W/

R

,DT

/R

, BST

A

T

,

WIDT

H/HL

T

D

1

:0

~

~

~

~

FA

IL

~

~

~

~

~

~

HO

L

D

~

~

~

~

~

~

~

~

~

~

LO

C

K

/ON

CE

~

~

~

~

~

~

~

~

~

~

Activit

y

:

~

~

~

~

~

~

~

~

80

96

0JD

 -

 46

 C

L

K

IN

 

8

096

0JA

/J

F

 -

 92

 C

L

K

IN

 

Cycle

s

Cy

cle

s

80

96

0JT

 - 2

6

 C

L

K

IN

 

Cycle

s

background image

 Advance Information Datasheet

67

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 42.

Entering the ONCE State

CL

KIN

AL

E

, A

D

S

,

AL

E

,W/

R

,

RESET

LOC

K

/

V

CC

 

DT

/R

, WIDT

H/HL

T

D

1

:0

FA

IL

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

ONC

E

A

D

3

1

:0

, A

3

:2

,

D/C

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

HO

L

D

~ ~

~ ~

~ ~

BE3

:0

, DE

N

, BL

AST

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

HOL

D

A

~ ~

~ ~

(I

npu

t)

mi

ni

m

u

m

 10

,0

0

0

 C

L

K

IN

 pe

ri

od

s

, f

o

r P

L

L

V

CC

 a

n

d

 CL

KI

N st

a

b

le

 t

o

 RESET

 H

igh,

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

(N

ot

e 1)

1

. ONCE

 m

o

d

e

 m

a

y b

e

 e

n

te

re

d

 p

rio

to

 t

h

e

 r

isin

g

 e

d

g

e

 o

f RESET

: O

NCE

 i

n

p

u

t i

s

 not 

la

tch

ed 

unt

il 

the

 ri

si

n

g

 ed

ge

 of 

R

E

S

E

T

NO

T

ES:

CLK

IN m

a

y n

o

be 

allowe

d to

 floa

t. 

~ ~

~ ~

ST

EST

~ ~

~ ~

~ ~

 

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

2.

 Th

e O

N

C

E

 i

npu

t m

a

y b

e

 r

e

m

o

ve

d af

ter

 the

 pr

oce

ssor

 en

ter

s

 ON

C

E

 M

o

d

e

~ ~

 

 s

ta

b

iliza

tio

n

.

 It m

u

st

 be

 dr

iv

en 

hi

gh

 or

 l

o

w

 o

r co

nti

n

ue 

to r

u

n

.

background image

80960JA/JF/JD/JT 3.3 V Microprocessor

68

 

 Advance Information Datasheet

5.1

Basic Bus States

The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold 

(Th). During system operation, the processor continuously enters and exits different bus states.

The bus occupies the idle (Ti) state when no address/data transactions are in progress and when RESET is 

asserted.   When the processor needs to initiate a bus access, it enters the Ta state to transmit the address.

Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data 

lines. Assertion of the RDYRCV input signal indicates completion of each transfer. When data is 

not ready, the processor can wait as long as necessary for the memory or I/O device to respond.

After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case of a 

burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next data word. 

The processor asserts the BLAST signal during the last Tw/Td states of an access. Once all data words 

transfer in a burst access (up to four), the bus enters the Tr state to allow devices on the bus to recover.

The processor remains in the Tr state until RDYRCV is deasserted. When the recovery state 

completes, the bus enters the Ti state if no new accesses are required. If an access is pending, the 

bus enters the Ta state to transmit the new address.

Figure 43.

Bus States with Arbitration

Ti — IDLE STATE

Ta — ADDRESS STATE

Tw / Td — WAIT/DATA STATE

Tr — RECOVERY STATE

Th — HOLD STATE

To — ONCE STATE

READY — RDYRCV ASSERTED

NOT READY — RDYRCV NOT ASSERTED

BURST — BLAST NOT ASSERTED

NO BURST — BLAST ASSERTED

RECOVERED — RDYRCV NOT ASSERTED

NOT RECOVERED — RDYRCV ASSERTED

REQUEST PENDING — NEW TRANSACTION

NO REQUEST  — NO NEW TRANSACTION

HOLD — HOLD REQUEST ASSERTED

NO HOLD — HOLD REQUEST NOT ASSERTED

LOCKED — ATOMIC EXECUTION (ATADD, ATMOD) IN PROGRESS

NOT LOCKED — NO ATOMIC EXECUTION IN PROGRESS

                        

 RESET — RESET ASSERTED

        

 ONCE — ONCE ASSERTED

Tw/Td

Tr

Th

Ti

Ta

HOLD AND 

NOT LOCKED

HOLD

RECOVERED AND 

NO REQUEST AND 

(NO HOLD OR 

LOCKED)

RECOVERED AND 

REQUEST 

PENDING AND (NO 

HOLD OR LOCKED)

NO REQUEST 

AND NO HOLD

To

RESET

NOT 

RECOVERED

RECOVERED AND 

HOLD AND NOT 

LOCKED

READY AND NO BURST 

(READY AND BURST) 

OR NOT READY

REQUEST PENDING 

AND (NO HOLD OR 

LOCKED)

NO REQUEST 

AND (NO HOLD 

OR LOCKED)

ONCE & RESET 

DEASSERTION

REQUEST 

PENDING AND 

NO HOLD

background image

 Advance Information Datasheet

69

80960JA/JF/JD/JT 3.3 V Microprocessor

5.2

Boundary-Scan Register

The Boundary-Scan register contains a cell for each pin as well as cells for control of I/O and HIGHZ pins. 

Table 25 shows the bit order of the 80960Jx processor Boundary-Scan register. All table cells that 

contain “CTL” select the direction of bidirectional pins or HIGHZ output pins. If a “1” is loaded 

into the control cell, the associated pin(s) are HIGHZ or selected as input. 

 

Table 25. 

Boundary-Scan Register Bit Order

Bit

Signal

Input/ 

Output

Bit

Signal

Input/

Output

Bit

Signal

Input/

Output

0

RDYRCV (TDI)

I

24

DEN

O

48

AD17

I/O

1

HOLD

I

25

HOLDA

O

49

AD16

I/O

2

XINT0

I

26

ALE

O

50

AD15

I/O

3

XINT1

I

27

LOCK/ONCE 

cell

Enable cell

1

51

AD14

I/O

4

XINT2

I

28

LOCK/ONCE

I/O

52

AD13

I/O

5

XINT3

I

29

BSTAT

O

53

AD12

I/O

6

XINT4

I

30

BE0

O

54

AD cells

Enable 

cell

1

7

XINT5

I

31

BE1

O

55

AD11

I/O

8

XINT6

I

32

BE2

O

56

AD10

I/O

9

XINT7

I

33

BE3

O

57

AD9

I/O

10

NMI

I

34

AD31

I/O

58

AD8

I/O

11

FAIL

I

35

AD30

I/O

59

AD7

I/O

12

ALE

O

36

AD29

I/O

60

AD6

I/O

13

WIDTH/HLTD1

O

37

AD28

I/O

61

AD5

I/O

14

WIDTH/HLTD0

O

38

AD27

I/O

62

AD4

I/O

15

A2

O

39

AD26

I/O

63

AD3

I/O

16

A3

O

40

AD25

I/O

64

AD2

I/O

17

CONTROL1

Enable cell

1

41

AD24

I/O

65

AD1

I/O

18

CONTROL2

Enable cell

1

42

AD23

I/O

66

AD0

I/O

19

BLAST

O

43

AD22

I/O

67

CLKIN

I

20

D/C

O

44

AD21

I/O

68

RESET

I

21

ADS

O

45

AD20

I/O

69

STEST 

(TDO)

I

22

W/R

O

46

AD19

I/O

23

DT/R

O

47

AD18

I/O

NOTE:

1. Enable cells are active low.

background image

80960JA/JF/JD/JT 3.3 V Microprocessor

70

 

 Advance Information Datasheet

Table 26. 

Natural Boundaries for Load and Store Accesses

Data Width

Natural Boundary (Bytes)

Byte

1

Short Word

2

Word

4

Double Word

8

Triple Word

16

Quad Word

16

Table 27. 

Summary of Byte Load and Store Accesses

Address Offset from 

Natural Boundary 

(in Bytes)

Accesses on 8-Bit Bus 

(WIDTH1:0=00)

Accesses on 16 Bit 

Bus (WIDTH1:0=01)

Accesses on 32 Bit 

Bus (WIDTH1:0=10)

+0 (aligned)

byte access

byte access

byte access

Table 28. 

Summary of Short Word Load and Store Accesses

Address Offset from 

Natural Boundary 

(in Bytes)

Accesses on 8-Bit Bus 

(WIDTH1:0=00)

Accesses on 16 Bit 

Bus (WIDTH1:0=01)

Accesses on 32 Bit 

Bus (WIDTH1:0=10)

+0 (aligned)

burst of 2 bytes

short-word access

short-word access

+1

2 byte accesses

2 byte accesses

2 byte accesses

background image

 Advance Information Datasheet

71

80960JA/JF/JD/JT 3.3 V Microprocessor

Table 29. 

Summary of 

n

-Word Load and Store Accesses (

n

 = 1, 2, 3, 4)

Address Offset 

from Natural 

Boundary in Bytes

Accesses on 8-Bit Bus 

(WIDTH1:0=00)

Accesses on 16 Bit Bus 

(WIDTH1:0=01)

Accesses on 32 Bit 

Bus (WIDTH1:0=10)

+0 (aligned) 

(

n

 =1, 2, 3, 4)

n

 burst(s) of 4 bytes

case 

n

=1:

burst of 2 short words

case 

n

=2:

burst of 4 short words

case 

n

=3:

burst of 4 short words

burst of 2 short words

case 

n

=4:

2 bursts of 4 short words

burst of 

n

 word(s)

+1 (

n

 =1, 2, 3, 4)

+5 (

n

 = 2, 3, 4)

+9 (

n

 = 3, 4)

+13 (

n

 = 3, 4)

byte access

burst of 2 bytes

n

-1 burst(s) of 4 bytes

byte access

byte access

short-word access

n

-1 burst(s) of 2 short 

words

byte access

byte access

short-word access

n

-1 word 

access(es)

byte access

+2 (

n

 =1, 2, 3, 4)

+6 (

n

 = 2, 3, 4)

+10 (

n

 = 3, 4)

+14 (

n

 = 3, 4)

burst of 2 bytes

n

-1 burst(s) of 4 bytes

burst of 2 bytes

short-word access

n

-1 burst(s) of 2 short 

words

short-word access

short-word access

n

-1 word 

access(es)

short-word access

+3 (

n

 =1, 2, 3, 4)

+7 (

n

 = 2, 3, 4)

+11 (

n

 = 3, 4)

+15 (

n

 = 3, 4)

byte access

n

-1 burst(s) of 4 bytes

burst of 2 bytes

byte access

 byte access

n

-1 burst(s) of 2 short 

words

short-word access

byte access

byte access

n

-1 word 

access(es)

short-word access

byte access

+4 (

n

 = 2, 3, 4)

+8 (

n

 = 3, 4)

+12 (

n

 = 3, 4)

n

 burst(s) of 4 bytes

n

 burst(s) of 2 short words

n

 word access(es)

background image

80960JA/JF/JD/JT 3.3 V Microprocessor

72

 

 Advance Information Datasheet

Figure 44.

Summary of Aligned and Unaligned Accesses (32-Bit Bus)

0

4

8

12

16

20

24

0

1

2

3

4

5

6

One Double-Word 

Short-Word

Load/Store

Word

Load/Store

Double-Word

Load/Store

Byte, Byte Accesses

Short Access (Aligned)

Short Access (Aligned)

Byte, Byte Accesses

Word Access (Aligned)

Byte, Short, Byte, Accesses

Short, Short Accesses

Byte, Short, Byte Accesses

Byte Offset

Word Offset

One Double-Word Burst (Aligned)

Byte, Short, Word, Byte Accesses

Short, Word, Short Accesses

Byte, Word, Short, Byte Accesses

Word, Word Accesses

Burst (Aligned)

background image

 Advance Information Datasheet

73

80960JA/JF/JD/JT 3.3 V Microprocessor

Figure 45.

Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)

0

4

8

12

16

20