background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 1

 

Devices included in this data sheet:

 

• PIC17CR42

• PIC17C42A

• PIC17C43

• PIC17CR43

• PIC17C44

• PIC17C42†

 

Microcontroller Core Features:

 

• Only 58 single word instructions to learn

• All single cycle instructions (121 ns) except for 

program branches and table reads/writes which 

are two-cycle

• Operating speed:

- DC - 33 MHz clock input

- DC - 121 ns instruction cycle   

 

   

 

 

• Hardware Multiplier 

(Not available on the PIC17C42)

• Interrupt capability

• 16 levels deep hardware stack

• Direct, indirect and relative addressing modes

• Internal/External program memory execution

• 64K x 16 addressable program memory space

 

Peripheral Features:

 

• 33 I/O pins with individual direction control

• High current sink/source for direct LED drive

- RA2 and RA3 are open drain, high voltage 

(12V), high current (60 mA), I/O

• Two capture inputs and two PWM outputs

- Captures are 16-bit, max resolution 160 ns

- PWM resolution is 1- to 10-bit

• TMR0: 16-bit timer/counter with 8-bit programma-

ble prescaler

• TMR1: 8-bit timer/counter

 

Device

Program Memory

Data Memory

EPROM

ROM

 

PIC17CR42

-

2K

232

PIC17C42A

2K

-

232

PIC17C43

4K

-

454

PIC17CR43

-

4K

454

PIC17C44

8K

-

454

PIC17C42†

2K

-

232

B

B

 

Pin Diagram

 

• TMR2: 8-bit timer/counter

• TMR3: 16-bit timer/counter

• Universal Synchronous Asynchronous Receiver 

Transmitter (USART/SCI)

 

Special Microcontroller Features:

 

• Power-on Reset (POR), Power-up Timer (PWRT) 

and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC 

oscillator for reliable operation

• Code-protection

• Power saving SLEEP mode

• Selectable oscillator options

 

CMOS Technology:

 

• Low-power, high-speed CMOS EPROM/ROM 

technology

• Fully static design

• Wide operating voltage range (2.5V to 6.0V)

• Commercial and Industrial Temperature Range

• Low-power consumption

- < 5 mA @ 5V, 4 MHz

- 100 

 

µ

 

A typical @ 4.5V, 32 kHz

- < 1 

 

µ

 

A typical standby current @ 5V

PIC17C4X

RD0/AD8

RD1/AD9

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

MCLR/V

PP

V

SS

RE0/ALE

RE1/OE

RE2/WR

TEST

RA0/INT

RA1/T0CKI

RA2

RA3

RA4/RX/DT

RA5/TX/CK

V

DD

RC0/AD0

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

V

SS

RB0/CAP1

RB1/CAP2

RB2/PWM1

RB3/PWM2

RB4/TCLK12

RB5/TCLK3

RB6

RB7

OSC1/CLKIN

OSC2/CLKOUT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

PDIP, CERDIP, Windowed CERDIP

 

PIC17C4X

 

High-Performance 8-Bit CMOS EPROM/ROM Microcontroller 

 

†NOT recommended for new designs, use 17C42A.

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 2

 

©

 

 1996 Microchip Technology Inc.

 

Pin Diagrams Cont.’d  

 

 

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

MCLR/V

PP

V

SS

V

SS

RE0/ALE

RE1/OE

RE2/WR

TEST

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

V

SS

V

SS

RB0/CAP1

RB1/CAP2

RB2/PWM1

RB3/PWM2

RB4/TCLK12

RC3/AD3

RC2/AD2

RC1/AD1

RC0/AD0

NC

V

DD

V

DD

RD0/AD8

RD1/AD9

RD2/AD10

RD3/AD11

7

8

9

10

11

12

13

14

15

16

17

39

38

37

36

35

34

33

32

31

30

29

RA0/INT

RA1/T0CKI

RA2

RA3

RA4/RX/DT

RA5/TX/CK

OSC2/CLK

OUT

OSC1/CLKIN

RB7

RB6

RB5/TCLK3

6

5

4

3

2

1

44

43

42

41

40

28

27

26

25

24

23

22

21

20

19

18

RB4/TCLK12

RB3/PWM2

RB2/PWM1

RB1/CAP2

RB0/CAP1

V

SS

V

SS

RC7/AD7

RC6/AD6

RC5/AD5

RC4/AD4

TEST

RE2/WR

RE1/OE

RE0/ALE

V

SS

V

SS

MCLR/V

PP

RD7/AD15

RD6/AD14

RD5/AD13

RD4/AD12

RA0/INT

RA1/T0CKI

RA2

RA3

RA4/RX/DT

RA5/TX/CK

OSC2/CLK

OUT

OSC1/CLKIN

RB7

RB6

RB5/TCLK3

1

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

25

24

23

RC3/AD3

RC2/AD2

RC1/AD1

RC0/AD0

NC

V

DD

V

DD

RD0/AD8

RD1/AD9

RD2/AD10

RD3/AD11

44

43

42

41

40

39

38

37

36

35

34

22

21

20

19

18

17

16

15

14

13

12

PLCC

MQFP

TQFP

All devices are available in all package types, listed in Section 21.0, with the following exceptions:

• ROM devices are not available in Windowed CERDIP Packages

• TQFP is not available for the PIC17C42.

PIC17C4X

PIC17C4X

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 3

 

PIC17C4X

 

Table of Contents

 

1.0

Overview .............................................................................................................................................................. 5

2.0

PIC17C4X Device Varieties ................................................................................................................................. 7

3.0

Architectural Overview ......................................................................................................................................... 9

4.0

Reset .................................................................................................................................................................. 15

5.0

Interrupts ............................................................................................................................................................ 21

6.0

Memory Organization ......................................................................................................................................... 29

7.0

Table Reads and Table Writes........................................................................................................................... 43

8.0

Hardware Multiplier ............................................................................................................................................ 49

9.0

I/O Ports ............................................................................................................................................................. 53

10.0

Overview of Timer Resources ............................................................................................................................ 65

11.0

Timer0 ................................................................................................................................................................ 67

12.0

Timer1, Timer2, Timer3, PWMs and Captures................................................................................................... 71

13.0

Universal Synchronous Asynchronous Receiver Transmitter (USART) Module ................................................ 83

14.0

Special Features of the CPU.............................................................................................................................. 99

15.0

Instruction Set Summary .................................................................................................................................. 107

16.0

Development Support....................................................................................................................................... 143

17.0

PIC17C42 Electrical Characteristics ................................................................................................................ 147

18.0

PIC17C42 DC and AC Characteristics............................................................................................................. 163

19.0

PIC17CR42/42A/43/R43/44 Electrical Characteristics..................................................................................... 175

20.0

PIC17CR42/42A/43/R43/44 DC and AC Characteristics ................................................................................. 193

21.0

Packaging Information...................................................................................................................................... 205

Appendix A: Modifications .......................................................................................................................................... 211

Appendix B: Compatibility........................................................................................................................................... 211

Appendix C: What’s New ............................................................................................................................................ 212

Appendix D: What’s Changed..................................................................................................................................... 212

Appendix E: PIC16/17 Microcontrollers ...................................................................................................................... 213

Appendix F: Errata for PIC17C42 Silicon ................................................................................................................... 223

Index ............................................................................................................................................................................ 226

PIC17C4X Product Identification System .................................................................................................................... 237

For register and module descriptions in this data sheet, device legends show which devices apply to those sections.

For example, the legend below shows that some features of only the PIC17C43, PIC17CR43, PIC17C44 are described

in this section.

 

            

 

Applicable Devices

 

42 R42 42A 43 R43 44

 

To Our Valued Customers

 

We constantly strive to improve the quality of all our products and documentation. We have spent an excep-

tional amount of time to ensure that these documents are correct. However, we realize that we may have 

missed a few things. If you find any information that is missing or appears in error from the previous version of 

the PIC17C4X Data Sheet (Literature Number DS30412B), please use the reader response form in the back 

of this data sheet to inform us. We appreciate your assistance in making this a better document.

To assist you in the use of this document, Appendix C contains a list of new information in this data sheet, 

while Appendix D contains information that has changed

background image

 

PIC17C4X

 

DS30412C-page 4

 

©

 

 1996 Microchip Technology Inc.

 

NOTES:

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 5

 

PIC17C4X

 

1.0

OVERVIEW

 

This data sheet covers the PIC17C4X group of the

PIC17CXX family of microcontrollers. The following

devices are discussed in this data sheet:

• PIC17C42

• PIC17CR42

• PIC17C42A

• PIC17C43

• PIC17CR43

• PIC17C44

The PIC17CR42, PIC17C42A, PIC17C43,

PIC17CR43, and PIC17C44 devices include architec-

tural enhancements over the PIC17C42. These

enhancements will be discussed throughout this data

sheet.

The PIC17C4X devices are 40/44-Pin,

EPROM/ROM-based members of the versatile

PIC17CXX family of low-cost, high-performance,

CMOS, fully-static, 8-bit microcontrollers.

All PIC16/17 microcontrollers employ an advanced

RISC architecture. The PIC17CXX has enhanced core

features, 16-level deep stack, and multiple internal and

external interrupt sources. The separate instruction and

data buses of the Harvard architecture allow a 16-bit

wide instruction word with a separate 8-bit wide data.

The two stage instruction pipeline allows all instructions

to execute in a single cycle, except for program

branches (which require two cycles). A total of 55

instructions (reduced instruction set) are available in

the PIC17C42 and 58 instructions in all the other

devices. Additionally, a large register set gives some of

the architectural innovations used to achieve a very

high performance. For mathematical intensive applica-

tions all devices, except the PIC17C42, have a single

cycle 8 x 8 Hardware Multiplier.

PIC17CXX microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in their class.

PIC17C4X devices have up to 454 bytes of RAM and

33 I/O pins. In addition, the PIC17C4X adds several

peripheral features useful in many high performance

applications including:

• Four timer/counters

• Two capture inputs

• Two PWM outputs 

• A Universal Synchronous Asynchronous Receiver 

Transmitter (USART)

These special features reduce external components,

thus reducing cost, enhancing system reliability and

reducing power consumption. There are four oscillator

options, of which the single pin RC oscillator provides a

low-cost solution, the LF oscillator is for low frequency

crystals and minimizes power consumption, XT is a

standard crystal, and the EC is for external clock input.

The SLEEP (power-down) mode offers additional

power saving. The user can wake-up the chip from

SLEEP through several external and internal interrupts

and device resets.

There are four configuration options for the device oper-

ational modes:

• Microprocessor

• Microcontroller

• Extended microcontroller

• Protected microcontroller

The microprocessor and extended microcontroller

modes allow up to 64K-words of external program

memory.

A highly reliable Watchdog Timer with its own on-chip

RC oscillator provides protection against software mal-

function. 

Table 1-1 lists the features of the PIC17C4X devices.

A UV-erasable CERDIP-packaged version is ideal for

code development while the cost-effective One-Time

Programmable (OTP) version is suitable for production

in any volume. 

The PIC17C4X fits perfectly in applications ranging

from precise motor control and industrial process con-

trol to automotive, instrumentation, and telecom appli-

cations. Other applications that require extremely fast

execution of complex software programs or the flexibil-

ity of programming the software code as one of the last

steps of the manufacturing process would also be well

suited. The EPROM technology makes customization

of application programs (with unique security codes,

combinations, model numbers, parameter storage,

etc.) fast and convenient. Small footprint package

options make the PIC17C4X ideal for applications with

space limitations that require high performance. High

speed execution, powerful peripheral features, flexible

I/O, and low power consumption all at low cost make

the PIC17C4X ideal for a wide range of embedded con-

trol applications.

 

1.1

Family and Upward Compatibility

 

Those users familiar with the PIC16C5X and

PIC16CXX families of microcontrollers will see the

architectural enhancements that have been imple-

mented. These enhancements allow the device to be

more efficient in software and hardware requirements.

Please refer to Appendix A for a detailed list of

enhancements and modifications. Code written for

PIC16C5X or PIC16CXX can be easily ported to

PIC17CXX family of devices (Appendix B).

 

1.2

Development Support

 

The PIC17CXX family is supported by a full-featured

macro assembler, a software simulator, an in-circuit

emulator, a universal programmer, a “C” compiler, and

fuzzy logic support tools.

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 6

 

©

 

 1996 Microchip Technology Inc.

 

TABLE 1-1:

PIC17CXX FAMILY OF DEVICES        

 

Features

PIC17C42

PIC17CR42

PIC17C42A

PIC17C43

PIC17CR43

PIC17C44

 

Maximum Frequency of Operation

25 MHz

33 MHz

33 MHz

33 MHz

33 MHz

33 MHz

Operating Voltage Range

4.5 - 5.5V

2.5 - 6.0V

2.5 - 6.0V

2.5 - 6.0V

2.5 - 6.0V

2.5 - 6.0V

Program Memory x16 

(EPROM)

2K

-

2K

4K

-

8K

(ROM)

-

2K

-

-

4K

-

Data Memory (bytes)

232

232

232

454

454

454

Hardware Multiplier (8 x 8)

-

Yes

Yes

Yes

Yes

Yes

Timer0 (16-bit + 8-bit postscaler)

Yes

Yes

Yes

Yes

Yes

Yes

Timer1 (8-bit)

Yes

Yes

Yes

Yes

Yes

Yes

Timer2 (8-bit)

Yes

Yes

Yes

Yes

Yes

Yes

Timer3 (16-bit)

Yes

Yes

Yes

Yes

Yes

Yes

Capture inputs (16-bit)

2

2

2

2

2

2

PWM outputs (up to 10-bit)

2

2

2

2

2

2

USART/SCI

Yes

Yes

Yes

Yes

Yes

Yes

Power-on Reset

Yes

Yes

Yes

Yes

Yes

Yes

Watchdog Timer

Yes

Yes

Yes

Yes

Yes

Yes

External Interrupts

Yes

Yes

Yes

Yes

Yes

Yes

Interrupt Sources

11

11

11

11

11

11

Program Memory Code Protect

Yes

Yes

Yes

Yes 

Yes 

Yes 

I/O Pins

33

33

33

33

33

33

I/O High Current Capabil-

ity 

Source

25 mA

25 mA

25 mA

25 mA

25 mA

25 mA

Sink

25 mA

 

(1)

 

25 mA

 

(1)

 

25 mA

 

(1)

 

25 mA

 

(1)

 

25 mA

 

(1)

 

25 mA

 

(1)

 

Package Types

40-pin DIP

44-pin PLCC

44-pin MQFP

40-pin DIP

44-pin PLCC

44-pin MQFP

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin MQFP 

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin MQFP

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin MQFP

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin MQFP

44-pin TQFP

Note 1:

Pins RA2 and RA3 can sink up to 60 mA.

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 7

 

PIC17C4X

 

2.0

PIC17C4X DEVICE VARIETIES

 

A variety of frequency ranges and packaging options

are available. Depending on application and production

requirements, the proper device option can be selected

using the information in the PIC17C4X Product Selec-

tion System section at the end of this data sheet. When

placing orders, please use the “PIC17C4X Product

Identification System” at the back of this data sheet to

specify the correct part number.

For the PIC17C4X family of devices, there are four

device “types” as indicated in the device number:

1.

 

C

 

, as in PIC17

 

C

 

42. These devices have

EPROM type memory and operate over the

standard voltage range.

2.

 

LC

 

, as in PIC17

 

LC

 

42. These devices have

EPROM type memory, operate over an

extended voltage range, and reduced frequency

range.

3.

 

CR

 

, as in PIC17

 

CR

 

42. These devices have

ROM type memory and operate over the stan-

dard voltage range.

4.

 

LCR

 

, as in PIC17

 

LCR

 

42. These devices have

ROM type memory, operate over an extended

voltage range, and reduced frequency range.

 

2.1

UV Erasable Devices

 

The UV erasable version, offered in CERDIP package,

is optimal for prototype development and pilot pro-

grams.

The UV erasable version can be erased and repro-

grammed to any of the configuration modes.

Microchip's  PRO MATE

 

 

 programmer supports pro-

gramming of the PIC17C4X. Third party programmers

also are available; refer to the 

 

Third Party Guide

 

 for a

list of sources.

 

2.2

One-Time-Programmable (OTP)

Devices

 

The availability of OTP devices is especially useful for

customers expecting frequent code changes and

updates. 

The OTP devices, packaged in plastic packages, per-

mit the user to program them once. In addition to the

program memory, the configuration bits must also be

programmed.

 

2.3

Quick-Turnaround-Production (QTP)

Devices

 

Microchip offers a QTP Programming Service for fac-

tory production orders. This service is made available

for users who choose not to program a medium to high

quantity of units and whose code patterns have stabi-

lized. The devices are identical to the OTP devices but

with all EPROM locations and configuration options

already programmed by the factory. Certain code and

prototype verification procedures apply before produc-

tion shipments are available. Please contact your local

Microchip Technology sales office for more details.

 

2.4

Serialized Quick-Turnaround

Production (SQTP

 

SM

 

) Devices

 

Microchip offers a unique programming service where

a few user-defined locations in each device are pro-

grammed with different serial numbers. The serial num-

bers may be random, pseudo-random or sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

ROM devices do not allow serialization information in

the program memory space.

For information on submitting ROM code, please con-

tact your regional sales office.

 

2.5

Read Only Memory (ROM) Devices

 

Microchip offers masked ROM versions of several of

the highest volume parts, thus giving customers a low

cost option for high volume, mature products.

For information on submitting ROM code, please con-

tact your regional sales office.

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 8

 

©

 

 1996 Microchip Technology Inc.

 

NOTES:

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 9

 

PIC17C4X

 

3.0

ARCHITECTURAL OVERVIEW

 

The high performance of the PIC17C4X can be attrib-

uted to a number of architectural features commonly

found in RISC microprocessors. To begin with, the

PIC17C4X uses a modified Harvard architecture. This

architecture has the program and data accessed from

separate memories. So the device has a program

memory bus and a data memory bus. This improves

bandwidth over traditional von Neumann architecture,

where program and data are fetched from the same

memory (accesses over the same bus). Separating

program and data memory further allows instructions to

be sized differently than the 8-bit wide data word.

PIC17C4X opcodes are 16-bits wide, enabling single

word instructions. The full 16-bit wide program memory

bus fetches a 16-bit instruction in a single cycle. A two-

stage pipeline overlaps fetch and execution of instruc-

tions. Consequently, all instructions execute in a single

cycle (121 ns @ 33 MHz), except for program branches

and two special instructions that transfer data between

program and data memory.

The PIC17C4X can address up to 64K x 16 of program

memory space. 

The 

 

PIC17C42

 

 and 

 

PIC17C42A

 

 integrate 2K x 16 of

EPROM program memory on-chip, while the

 

PIC17CR42

 

 has 2K x 16 of ROM program memory on-

chip. 

The 

 

PIC17C43

 

 integrates 4K x 16 of EPROM program

memory, while the 

 

PIC17CR43

 

 has 4K x 16 of ROM

program memory.

The 

 

PIC17C44

 

 integrates 8K x 16 EPROM program

memory. 

Program execution can be internal only (microcontrol-

ler or protected microcontroller mode), external only

(microprocessor mode) or both (extended microcon-

troller mode). Extended microcontroller mode does not

allow code protection.

The PIC17CXX can directly or indirectly address its

register files or data memory. All special function regis-

ters, including the Program Counter (PC) and Working

Register (WREG), are mapped in the data memory.

The PIC17CXX has an orthogonal (symmetrical)

instruction set that makes it possible to carry out any

operation on any register using any addressing mode.

This symmetrical nature and lack of ‘special optimal sit-

uations’ make programming with the PIC17CXX simple

yet efficient. In addition, the learning curve is reduced

significantly.

One of the PIC17CXX family architectural enhance-

ments from the PIC16CXX family allows two file regis-

ters to be used in some two operand instructions. This

allows data to be moved directly between two registers

without going through the WREG register. This

increases performance and decreases program mem-

ory usage.

The PIC17CXX devices contain an 8-bit ALU and work-

ing register. The ALU is a general purpose arithmetic

unit. It performs arithmetic and Boolean functions

between data in the working register and any register

file.

The ALU is 8-bits wide and capable of addition, sub-

traction, shift, and logical operations. Unless otherwise

mentioned, arithmetic operations are two's comple-

ment in nature.

The WREG register is an 8-bit working register used for

ALU operations.

All PIC17C4X devices (except the PIC17C42) have an

8 x 8 hardware multiplier. This multiplier generates a

16-bit result in a single cycle.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a borrow and digit borrow out bit, respec-

tively, in subtraction. See the 

 

SUBLW

 

 and 

 

SUBWF

 

instructions for examples.

Although the ALU does not perform signed arithmetic,

the Overflow bit (OV) can be used to implement signed

math. Signed arithmetic is comprised of a magnitude

and a sign bit. The overflow bit indicates if the magni-

tude overflows and causes the sign bit to change state.

Signed math can have greater than 7-bit values (mag-

nitude), if more than one byte is used. The use of the

overflow bit only operates on bit6 (MSb of magnitude)

and bit7 (sign bit) of the value in the ALU. That is, the

overflow bit is not useful if trying to implement signed

math where the magnitude, for example, is 11-bits. If

the signed math values are greater than 7-bits (15-, 24-

or 31-bit), the algorithm must ensure that the low order

bytes ignore the overflow status bit.

Care should be taken when adding and subtracting

signed numbers to ensure that the correct operation is

executed. Example 3-1 shows an item that must be

taken into account when doing signed arithmetic on an

ALU which operates as an unsigned machine.

 

EXAMPLE 3-1:

SIGNED MATH

 

Signed math requires the result in REG to

be FEh (-126). This would be accomplished

by subtracting one as opposed to adding

one.

 

Simplified block diagrams are shown in Figure 3-1 and

Figure 3-2. The descriptions of the device pins are

listed in Table 3-1.

 

Hex Value

Signed Value 

Math

Unsigned Value 

Math

  FFh

+ 01h

=  ?

  -127 

+    1

= -126 (FEh)

  255

+   1

=   0 (00h);

Carry bit = 1

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 10

 

©

 

 1996 Microchip Technology Inc.

 

FIGURE 3-1:

PIC17C42 BLOCK DIAGRAM      

CLOCK GENERA

T

O

R

PO

WER ON RESET

W

A

TCHDOG TIMER

OSC ST

AR

TUP 

TIMER

TEST MODE SELECT 

SYSTEM

D

A

T

A

 LA

TCH

ADDRESS LA

TCH

PR

OGRAM

MEMOR

Y

(EPR

OM/R

OM)

T

ABLE PTR<16>

ST

A

C

K

16 x 16

PCH

PCL

PCLA

TH<8>

T

ABLE LA

TCH <16>

R

OM LA

TCH <16>

LITERAL

INSTR

UCTION

DECODER

CONTR

OL OUTPUTS

IR LA

TCH <16>

FSR0

FSR1

8

8

8

IR BUS <16>

RAM ADDR B

UFFER

D

A

T

A

 LA

TCH

READ/WRITE

DECODE

FOR REGISTERS

MAPPED

IN D

A

T

A

 

SP

A

C

E

WREG <8>

BIT

OP

ALU

SHIFTER

IR BUS <16>

POR

TB

POR

T

A

RB0/CAP1

RB1/CAP2

RB2/PWM1

RB2/PWM2

RB4/TCLK12

RB5/TCLK3

RB6

RB7

RA0/INT

RA1/T0CKI

RA2

RA3

RA4/RX/DT

RA5/TX/CK

RA1/

Timer1, Timer2, Timer3

CAPTURE

PWM

DIGIT

AL I/O

POR

TS A, B

SERIAL POR

T

Timer0 MODULE

D

A

T

A

 B

US <8>

IR BUS <7:0>

RA1/T0CKI

RA0/INT

86

8

6

2

6

4

3

IR <2:0>

DA

T A

 BUS <8>

CONTR

OL

SIGNALS

T

O

 CPU

CHIP_RESET

AND O

THER

CONTR

OL

SIGNALS

Q1, Q2, Q3, Q4

16

16

11

AD <15:0>

POR

TC and 

ALE, WR

, OE

POR

TE

OSC1, OSC2

V

DD

, V

SS

MCLR

/V

PP

TEST

DECODE

BSR

INTERR

UPT

MODULE

8

RDF

WRF

T0CKI

PERIPHERALS

IR <7>

BU

S

INTER

-

FA

C

E

16

D

A

T

A

 RAM

232x8

2K x 16

POR

TD

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 11

 

PIC17C4X

 

FIGURE 3-2:

PIC17CR42/42A/43/R43/44 BLOCK DIAGRAM           

CLOCK GENERA

T

O

R

PO

WER ON RESET

W

A

TCHDOG TIMER

OSC ST

AR

TUP 

TIMER

TEST MODE SELECT 

SYSTEM

D

A

T

A

 LA

TCH

ADDRESS LA

TCH

PR

OGRAM

MEMOR

Y

(EPR

OM/R

OM)

T

ABLE PTR<16>

ST

A

C

K

16 x 16

PCH

PCL

PCLA

TH<8>

T

ABLE LA

TCH <16>

R

OM LA

TCH <16>

LITERAL

INSTR

UCTION

DECODER

CONTR

OL OUTPUTS

IR LA

TCH <16>

FSR0

FSR1

8

8

8

IR BUS <16>

RAM ADDR B

UFFER

D

A

T

A

 LA

TCH

READ/WRITE

DECODE

FOR REGISTERS

MAPPED

IN D

A

T

A

 

SP

A

C

E

WREG <8>

BIT

OP

ALU

SHIFTER

IR BUS <16>

POR

TB

POR

T

A

RB0/CAP1

RB1/CAP2

RB2/PWM1

RB2/PWM2

RB4/TCLK12

RB5/TCLK3

RB6

RB7

RA0/INT

RA1/T0CKI

RA2

RA3

RA4/RX/DT

RA5/TX/CK

RA1/

Timer1, Timer2, Timer3

CAPTURE

PWM

DIGIT

AL I/O

POR

TS A, B

SERIAL POR

T

Timer0 MODULE

D

A

T

A

 B

US <8>

BSR<7:4>

RA1/T0CKI

RA0/INT

86

8

6

2

6

4

3

IR <2:0>

DA

T A

 BUS <8>

CONTR

OL

SIGNALS

T

O

 CPU

CHIP_RESET

AND O

THER

CONTR

OL

SIGNALS

Q1, Q2, Q3, Q4

16

16

13

AD <15:0>

POR

TC and

ALE, WR

, OE

POR

TE

OSC1, OSC2

V

DD

, V

SS

MCLR

/V

PP

TEST

DECODE

BSR

INTERR

UPT

MODULE

12

RDF

WRF

T0CKI

PERIPHERALS

IR <7>

BU

S

INTER

-

FA

C

E

16

8 x 8 mult

PR

ODH

PR

ODL

D

A

T

A

 RAM

454 x 8 PIC17C43

8K x 16 - PIC17C44

4K x 16 - PIC17C43

IR BUS<7:0>

4K x 16 - PIC17CR43

454 x 8 PIC17CR43

454 x 8 PIC17C44

232 x 

8 PIC17C42A

232 x 

8 PIC17CR42

2K x 16 - PIC17C4

2A

2K x 16 - PIC17C

R42

POR

TD

background image

 

PIC17C4X

 

DS30412C-page 12

 

©

 

 1996 Microchip Technology Inc.

 

TABLE 3-1:

 

PINOUT DESCRIPTIONS

 

Name

DIP

No.

PLCC

No.

QFP

No.

I/O/P

Type

Buffer

Type

Description

 

OSC1/CLKIN

19

21

37

I

ST

Oscillator input in crystal/resonator or RC oscillator mode. 

External clock input in external clock mode.

OSC2/CLKOUT

20

22

38

O

Oscillator output. Connects to crystal or resonator in crystal 

oscillator mode. In RC oscillator or external clock modes 

OSC2 pin outputs CLKOUT which has one fourth the fre-

quency of OSC1 and denotes the instruction cycle rate.

MCLR/V

 

PP

 

32

35

7

I/P

ST

Master clear (reset) input/Programming Voltage (V

 

PP

 

) input. 

This is the active low reset input to the chip.

PORTA is a bi-directional I/O Port except for RA0 and RA1 

which are input only.

RA0/INT

26

28

44

I

ST

RA0/INT can also be selected as an external interrupt 

input. Interrupt can be configured to be on positive or 

negative edge.

RA1/T0CKI

25

27

43

I

ST

RA1/T0CKI can also be selected as an external interrupt 

input, and the interrupt can be configured to be on posi-

tive or negative edge. RA1/T0CKI can also be selected 

to be the clock input to the Timer0 timer/counter.

RA2

24

26

42

I/O

ST

High voltage, high current, open drain input/output port 

pins.

RA3

23

25

41

I/O

ST

High voltage, high current, open drain input/output port 

pins.

RA4/RX/DT

22

24

40

I/O

ST

RA4/RX/DT can also be selected as the USART (SCI) 

Asynchronous Receive or USART (SCI) Synchronous 

Data.

RA5/TX/CK

21

23

39

I/O

ST

RA5/TX/CK can also be selected as the USART (SCI) 

Asynchronous Transmit or USART (SCI) Synchronous 

Clock.

PORTB is a bi-directional I/O Port with software configurable 

weak pull-ups.

RB0/CAP1

11

13

29

I/O

ST

RB0/CAP1 can also be the CAP1 input pin.

RB1/CAP2

12

14

30

I/O

ST

RB1/CAP2 can also be the CAP2 input pin.

RB2/PWM1

13

15

31

I/O

ST

RB2/PWM1 can also be the PWM1 output pin.

RB3/PWM2

14

16

32

I/O

ST

RB3/PWM2 can also be the PWM2 output pin.

RB4/TCLK12

15

17

33

I/O

ST

RB4/TCLK12 can also be the external clock input to 

Timer1 and Timer2.

RB5/TCLK3

16

18

34

I/O

ST

RB5/TCLK3 can also be the external clock input to 

Timer3.

RB6

17

19

35

I/O

ST

RB7

18

20

36

I/O

ST

PORTC is a bi-directional I/O Port.

RC0/AD0

2

3

19

I/O

TTL

This is also the lower half of the 16-bit wide system bus 

in microprocessor mode or extended microcontroller 

mode. In multiplexed system bus configuration, these 

pins are address output as well as data input or output.

RC1/AD1

3

4

20

I/O

TTL

RC2/AD2

4

5

21

I/O

TTL

RC3/AD3

5

6

22

I/O

TTL

RC4/AD4

6

7

23

I/O

TTL

RC5/AD5

7

8

24

I/O

TTL

RC6/AD6

8

9

25

I/O

TTL

RC7/AD7

9

10

26

I/O

TTL

Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input; 

ST = Schmitt Trigger input.

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 13

 

PIC17C4X

 

PORTD is a bi-directional I/O Port.

RD0/AD8

40

43

15

I/O

TTL

This is also the upper byte of the 16-bit system bus in 

microprocessor mode or extended microprocessor mode 

or extended microcontroller mode. In multiplexed system 

bus configuration these pins are address output as well 

as data input or output.

RD1/AD9

39

42

14

I/O

TTL

RD2/AD10

38

41

13

I/O

TTL

RD3/AD11

37

40

12

I/O

TTL

RD4/AD12

36

39

11

I/O

TTL

RD5/AD13

35

38

10

I/O

TTL

RD6/AD14

34

37

9

I/O

TTL

RD7/AD15

33

36

8

I/O

TTL

PORTE is a bi-directional I/O Port.

RE0/ALE

30

32

4

I/O

TTL

In microprocessor mode or extended microcontroller 

mode, it is the Address Latch Enable (ALE) output. 

Address should be latched on the falling edge of ALE 

output.

RE1/OE

29

31

3

I/O

TTL

In microprocessor or extended microcontroller mode, it is 

the Output Enable (OE) control output (active low).

RE2/WR

28

30

2

I/O

TTL

In microprocessor or extended microcontroller mode, it is 

the Write Enable (WR) control output (active low).

TEST

27

29

1

I

ST

Test mode selection control input.  Always tie to V

 

SS

 

 for nor-

mal operation.

V

 

SS

 

10, 

31

11, 

12, 

33, 34

5, 6, 

27, 28

P

Ground reference for logic and I/O pins.

V

 

DD

 

1

1, 44

16, 17

P

Positive supply for logic and I/O pins.

 

TABLE 3-1:

 

PINOUT DESCRIPTIONS

 

Name

DIP

No.

PLCC

No.

QFP

No.

I/O/P

Type

Buffer

Type

Description

 

Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input; 

ST = Schmitt Trigger input.

background image

 

PIC17C4X

 

DS30412C-page 14

 

©

 

 1996 Microchip Technology Inc.

 

3.1

Clocking Scheme/Instruction Cycle

 

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3, and Q4. Internally, the pro-

gram counter (PC) is incremented every Q1, and the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

are shown in Figure 3-3.

 

3.2

Instruction Flow/Pipelining

 

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3, and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g. 

 

GOTO

 

) then

two cycles are required to complete the instruction

(Example 3-2).

A fetch cycle begins with the program counter incre-

menting in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register (IR)” in cycle Q1.  This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

 

FIGURE 3-3:

CLOCK/INSTRUCTION CYCLE    

EXAMPLE 3-2:

INSTRUCTION PIPELINE FLOW   

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

OSC1

Q1

Q2

Q3

Q4

PC

OSC2/CLKOUT

(RC mode)

PC

PC+1

PC+2

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 

Tcy0

Tcy1

Tcy2

Tcy3

Tcy4

Tcy5

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. CALL SUB_1

Fetch 3

Execute 3

4. BSF   PORTA, BIT3 (Forced NOP)

Fetch 4

Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 15

 

PIC17C4X

 

4.0

RESET

 

The PIC17CXX differentiates between various kinds of

reset: 

• Power-on Reset (POR)

• MCLR reset during normal operation

• WDT Reset (normal operation)

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any

other reset. Most other registers are forced to a “reset

state” on Power-on Reset (POR), on MCLR or WDT

Reset and on MCLR reset during SLEEP. They are not

affected by a WDT Reset during SLEEP, since this reset

is viewed as the resumption of normal operation. The

TO and PD bits are set or cleared differently in different

reset situations as indicated in Table 4-3. These bits are

used in software to determine the nature of reset. See

Table 4-4 for a full description of reset states of all reg-

isters.  

A simplified block diagram of the on-chip reset circuit is

shown in Figure 4-1.

 

Note:

 

While the device is in a reset state, the

internal phase clock is held in the Q1 state.

Any processor mode that allows external

execution will force the RE0/ALE pin as a

low output and the RE1/OE and RE2/WR

pins as high outputs.

 

4.1

Power-on Reset (POR), Power-up 

Timer (PWRT), and Oscillator Start-up 

Timer (OST)

 

4.1.1

POWER-ON RESET (POR)

The Power-on Reset circuit holds the device in reset

until V

 

DD

 

 is above the trip point (in the range of 1.4V -

2.3V). The PIC17C42 does not produce an internal

reset when V

 

DD

 

 declines. All other devices will produce

an internal reset for both rising and falling V

 

DD

 

. To take

advantage of the POR, just tie the MCLR/V

 

PP

 

 pin

directly (or through a resistor) to V

 

DD

 

. This will eliminate

external RC components usually needed to create

Power-on Reset. A minimum rise time for V

 

DD

 

 is

required. See Electrical Specifications for details.

4.1.2

POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 96 ms time-out

(nominal) on power-up. This occurs from rising edge of

the POR signal and after the first rising edge of MCLR

(detected high). The Power-up Timer operates on an

internal RC oscillator. The chip is kept in RESET as

long as the PWRT is active. In most cases the PWRT

delay allows the V

 

DD

 

 to rise to an acceptable level.

The power-up time delay will vary from chip to chip and

to V

 

DD

 

 and temperature. See DC parameters for

details.

 

FIGURE 4-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT   

S

R

Q

External

Reset

MCLR

V

DD

OSC1

WDT

Module

V

DD

 rise

detect

OST/PWRT

On-chip

RC OSC† 

WDT

Time_Out

Power_On_Reset

OST

10-bit Ripple counter

PWRT

Chip_Reset

10-bit Ripple counter

Power_Up

(Enable the PWRT timer

only during Power_Up)

(Power_Up + Wake_Up) (XT + LF)

(Enable the OST if it is Power_Up or Wake_Up

from SLEEP and OSC type is XT or LF)

Reset

Enab

le OST

Enab

le PWR

T

† This RC oscillator is shared with the WDT

when not in a power-up sequence.

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 16

 

©

 

 1996 Microchip Technology Inc.

 

4.1.3

OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (1024T

 

OSC

 

) delay after MCLR is

detected high or a wake-up from SLEEP event occurs.

The OST time-out is invoked only for XT and LF oscilla-

tor modes on a Power-on Reset or a Wake-up from

SLEEP.

The OST counts the oscillator pulses on the

OSC1/CLKIN pin. The counter only starts incrementing

after the amplitude of the signal reaches the oscillator

input thresholds. This delay allows the crystal oscillator

or resonator to stabilize before the device exits reset.

The length of time-out is a function of the crystal/reso-

nator frequency. 

4.1.4

TIME-OUT SEQUENCE

On power-up the time-out sequence is as follows: First

the internal POR signal goes high when the POR trip

point is reached. If MCLR is high, then both the OST

and PWRT timers start. In general the PWRT time-out

is longer, except with low frequency crystals/resona-

tors. The total time-out also varies based on oscillator

configuration. Table 4-1 shows the times that are asso-

ciated with the oscillator configuration. Figure 4-2 and

Figure 4-3 display these time-out sequences.

If the device voltage is not within electrical specification

at the end of a time-out, the MCLR/V

 

PP

 

 pin must be

held low until the voltage is within the device specifica-

tion. The use of an external RC delay is sufficient for

many of these applications.

 

TABLE 4-1:

TIME-OUT IN VARIOUS 

SITUATIONS   

 

The time-out sequence begins from the first rising edge

of MCLR.

Table 4-3 shows the reset conditions for some special

registers, while Table 4-4 shows the initialization condi-

tions for all the registers. The shaded registers (in

Table 4-4) are for all devices except the PIC17C42. In

the PIC17C42, the PRODH and PRODL registers are

general purpose RAM. 

 

TABLE 4-2:

STATUS BITS AND THEIR 

SIGNIFICANCE   

 

In Figure 4-2, Figure 4-3 and Figure 4-4, T

 

PWRT

 

  >

T

 

OST

 

, as would be the case in higher frequency crys-

tals. For lower frequency crystals, (i.e., 32 kHz) T

 

OST

 

would be greater.

 

Oscillator

Configuration

Power-up

Wake up 

from

SLEEP

MCLR 

Reset

 

XT, LF

Greater of: 

96 ms or

1024T

 

OSC

 

1024T

 

OSC

 

EC, RC

Greater of: 

96 ms or

1024T

 

OSC

 

 

TO

PD

Event

 

1

1

 

Power-on Reset, MCLR Reset during normal 

operation, or 

 

CLRWDT

 

 instruction executed

 

1

0

 

MCLR Reset during SLEEP or interrupt wake-up 

from SLEEP

 

0

1

 

WDT Reset during normal operation

 

0

0

 

WDT Reset during SLEEP

 

TABLE 4-3:

RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER   

 

Event

PCH:PCL

CPUSTA

OST Active

 

Power-on Reset

0000h

 

--11 11--

 

Yes

MCLR Reset during normal operation

0000h

 

--11 11--

 

No

MCLR Reset during SLEEP

0000h

 

--11 10--

 

Yes 

 

(2)

 

WDT Reset during normal operation

0000h

 

--11 01--

 

No

WDT Reset during SLEEP 

 

(3)

 

0000h

 

--11 00--

 

Yes 

 

(2)

 

Interrupt wake-up from SLEEP

GLINTD is set

PC + 1

 

--11 10--

 

Yes 

 

(2)

 

GLINTD is clear

PC + 1 

 

(1)

 

--10 10--

 

Yes 

 

(2)

 

Legend:

 

u

 

 = unchanged, 

 

x

 

 = unknown, 

 

-

 

 =   unimplemented read as '0'.

Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and 

then executed.

2: The OST is only active when the Oscillator is configured for XT or LF modes.

3: The Program Counter = 0, that is the device branches to the reset vector. This is different from the 

mid-range devices.

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 17

 

PIC17C4X

 

FIGURE 4-2:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V

 

DD

 

)       

FIGURE 4-3:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V

 

DD

 

)   

FIGURE 4-4:

SLOW RISE TIME (MCLR TIED  TO V

 

DD

 

)    

T

PWRT

T

OST

V

DD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

T

PWRT

T

OST

V

DD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

V

DD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

0V

1V

5V

T

PWRT

T

OST

background image

 

PIC17C4X

 

DS30412C-page 18

 

©

 

 1996 Microchip Technology Inc.

 

FIGURE 4-5:

OSCILLATOR START-UP TIME   

FIGURE 4-6:

USING ON-CHIP POR   

FIGURE 4-7:

BROWN-OUT PROTECTION 

CIRCUIT 1    

V

DD

MCLR

OSC2

OST TIME_OUT

PWRT TIME_OUT

INTERNAL RESET

T

OSC

1

T

OST

T

PWRT

This figure shows in greater detail the timings involved

with the oscillator start-up timer. In this example the

low frequency crystal start-up time is larger than

power-up time (T

PWRT

).

Tosc1 = time for the crystal oscillator to react to an

oscillation level detectable by the Oscillator Start-up

Timer (ost).

T

OST

 = 1024T

OSC

.

V

DD

MCLR

PIC17CXX

V

DD

This circuit will activate reset when V

DD

 goes below 

(Vz + 0.7V) where Vz = Zener voltage.

V

DD

33k

10k

40 k

V

DD

MCLR

PIC17CXX

 

FIGURE 4-8:

PIC17C42 EXTERNAL 

POWER-ON RESET CIRCUIT 

(FOR SLOW V

 

DD

 

 

POWER-UP)   

FIGURE 4-9:

BROWN-OUT PROTECTION 

CIRCUIT 2      

Note 1: An external Power-on Reset circuit is 

required only if V

DD

 power-up time is too 

slow. The diode D helps discharge the 

capacitor quickly when V

DD

 powers 

down.

2: R < 40 k

 is recommended to ensure 

that the voltage drop across R does not 

exceed 0.2V (max. leakage current spec. 

on the MCLR/V

PP

 pin is 5 

µ

A). A larger 

voltage drop will degrade V

IH

 level on the 

MCLR/V

PP

 pin.

3: R1 = 100

 to 1 k

 will limit any current 

flowing into MCLR from external capaci-

tor C in the event of MCLR/V

PP

 pin 

breakdown due to Electrostatic Dis-

charge (ESD) or (Electrical Overstress) 

EOS.

C

R1

R

D

V

DD

MCLR

PIC17C42

V

DD

This brown-out circuit is less expensive, albeit less

accurate. Transistor Q1 turns off when V

DD

 is below a

certain level such that:

V

DD

 •

R1

R1 + R2

= 0.7V

R2

40 k

V

DD

MCLR

PIC17CXX

R1

Q1

V

DD

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 19

 

PIC17C4X

 

               

 

TABLE 4-4:

INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS       

 

Register

Address

Power-on Reset

MCLR Reset

WDT Reset

Wake-up from SLEEP 

through interrupt

Unbanked

 

INDF0

00h

 

0000 0000

0000 0000

0000 0000

 

FSR0

01h

 

xxxx xxxx

uuuu uuuu

uuuu uuuu

 

PCL

02h

 

0000h

0000h

 PC + 1

 

(2)

 

PCLATH

03h

 

0000 0000

0000 0000

uuuu uuuu

 

ALUSTA

04h

 

1111 xxxx

1111 uuuu

1111 uuuu

 

T0STA

05h

 

0000 000-

0000 000-

0000 000-

CPUSTA

(3)

06h

--11 11--

--11 qq--

--uu qq--

INTSTA

07h

0000 0000

0000 0000

uuuu uuuu

(1)

INDF1

08h

0000 0000

0000 0000

uuuu uuuu

FSR1

09h

xxxx xxxx

uuuu uuuu

uuuu uuuu

WREG

0Ah

xxxx xxxx

uuuu uuuu

uuuu uuuu

TMR0L

0Bh

xxxx xxxx

uuuu uuuu

uuuu uuuu

TMR0H

0Ch

xxxx xxxx

uuuu uuuu

uuuu uuuu

TBLPTRL 

(4)

0Dh

xxxx xxxx

uuuu uuuu

uuuu uuuu

TBLPTRH 

(4)

0Eh

xxxx xxxx

uuuu uuuu

uuuu uuuu

TBLPTRL 

(5)

 

0Dh

0000 0000

0000 0000

uuuu uuuu

TBLPTRH 

(5)

 

0Eh

0000 0000

0000 0000

uuuu uuuu

BSR

0Fh

0000 0000

0000 0000

uuuu uuuu

Bank 0

PORTA

10h

0-xx xxxx

0-uu uuuu

uuuu uuuu

DDRB

11h

1111 1111

1111 1111

uuuu uuuu

PORTB

12h

xxxx xxxx

uuuu uuuu

uuuu uuuu

RCSTA

13h

0000 -00x

0000 -00u

uuuu -uuu

RCREG

14h

xxxx xxxx

uuuu uuuu

uuuu uuuu

TXSTA

15h

0000 --1x

0000 --1u

uuuu --uu

TXREG

16h

xxxx xxxx

uuuu uuuu

uuuu uuuu

SPBRG

17h

xxxx xxxx

uuuu uuuu

uuuu uuuu

Bank 1

DDRC

10h

1111 1111

1111 1111

uuuu uuuu

PORTC

11h

xxxx xxxx

uuuu uuuu

uuuu uuuu

DDRD

12h

1111 1111

1111 1111

uuuu uuuu

PORTD

13h

xxxx xxxx

uuuu uuuu

uuuu uuuu

DDRE

14h

---- -111

---- -111

---- -uuu

PORTE

15h

---- -xxx

---- -uuu

---- -uuu

PIR

16h

0000 0010

0000 0010

uuuu uuuu

(1)

PIE

17h

0000 0000

0000 0000

uuuu uuuu

Legend:

u

 = unchanged,   

x

 = unknown,   

-

 =   unimplemented read as '0',    

q

 = value depends on condition.

Note 1: One or more bits in INTSTA, PIR will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt 

vector.

3: See Table 4-3 for reset value of specific condition.

4: Only applies to the PIC17C42.

5: Does not apply to the PIC17C42.

background image

PIC17C4X

DS30412C-page 20

©

 1996 Microchip Technology Inc.

Bank 2

TMR1

10h

xxxx xxxx

uuuu uuuu

uuuu uuuu

TMR2

11h

xxxx xxxx

uuuu uuuu

uuuu uuuu

TMR3L

12h

xxxx xxxx

uuuu uuuu

uuuu uuuu

TMR3H

13h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PR1

14h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PR2

15h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PR3/CA1L

16h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PR3/CA1H

17h

xxxx xxxx

uuuu uuuu

uuuu uuuu

Bank 3

PW1DCL

10h

xx-- ----

uu-- ----

uu-- ----

PW2DCL

11h

xx-- ----

uu-- ----

uu-- ----

PW1DCH

12h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PW2DCH

13h

xxxx xxxx

uuuu uuuu

uuuu uuuu

CA2L

14h

xxxx xxxx

uuuu uuuu

uuuu uuuu

CA2H

15h

xxxx xxxx

uuuu uuuu

uuuu uuuu

TCON1

16h

0000 0000

0000 0000

uuuu uuuu

TCON2

17h

0000 0000

0000 0000

uuuu uuuu

Unbanked

PRODL 

(5)

 

18h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PRODH 

(5)

 

19h

xxxx xxxx

uuuu uuuu

uuuu uuuu

TABLE 4-4:

INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS    (Cont.’d)   

Register

Address

Power-on Reset

MCLR Reset

WDT Reset

Wake-up from SLEEP 

through interrupt

Legend:

u

 = unchanged,   

x

 = unknown,   

-

 =   unimplemented read as '0',    

q

 = value depends on condition.

Note 1: One or more bits in INTSTA, PIR will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt 

vector.

3: See Table 4-3 for reset value of specific condition.

4: Only applies to the PIC17C42.

5: Does not apply to the PIC17C42.

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 21

 

PIC17C4X

 

5.0

INTERRUPTS

 

The PIC17C4X devices have 11 sources of interrupt:

• External interrupt from the RA0/INT pin

• Change on RB7:RB0 pins

• TMR0 Overflow

• TMR1 Overflow

• TMR2 Overflow

• TMR3 Overflow

• USART Transmit buffer empty

• USART Receive buffer full

• Capture1

• Capture2 

• T0CKI edge occurred

There are four registers used in the control and status

of interrupts. These are:

• CPUSTA

• INTSTA

• PIE

• PIR

The CPUSTA register contains the GLINTD bit. This is

the Global Interrupt Disable bit. When this bit is set, all

interrupts are disabled. This bit is part of the controller

core functionality and is described in the Memory Orga-

nization section.

When an interrupt is responded to, the GLINTD bit is

automatically set to disable any further interrupt, the

return address is pushed onto the stack and the PC is

loaded with the interrupt vector address. There are four

interrupt vectors. Each vector address is for a specific

interrupt source (except the peripheral interrupts which

have the same vector address). These sources are:

• External interrupt from the RA0/INT pin

• TMR0 Overflow

• T0CKI edge occurred

• Any peripheral interrupt

When program execution vectors to one of these inter-

rupt vector addresses (except for the peripheral inter-

rupt address), the interrupt flag bit is automatically

cleared. Vectoring to the peripheral interrupt vector

address does not automatically clear the source of the

interrupt. In the peripheral interrupt service routine, the

source(s) of the interrupt can be determined by testing

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid infinite interrupt requests. 

All of the individual interrupt flag bits will be set regard-

less of the status of their corresponding mask bit or the

GLINTD bit.

For external interrupt events, there will be an interrupt

latency. For two cycle instructions, the latency could be

one instruction cycle longer. 

The “return from interrupt” instruction, 

 

RETFIE

 

, can be

used to mark the end of the interrupt service routine.

When this instruction is executed, the stack is

“POPed”, and the GLINTD bit is cleared (to re-enable

interrupts). 

 

FIGURE 5-1:

INTERRUPT LOGIC   

TMR1IF

TMR1IE

TMR2IF

TMR2IE

TMR3IF

TMR3IE

CA1IF

CA1IE

CA2IF

CA2IE

TXIF

TXIE

RCIF

RCIE

RBIF

RBIE

T0IF

T0IE

INTF

INTE

T0CKIF

T0CKIE

GLINTD

PEIE

Wake-up (If in SLEEP mode)

or terminate long write

Interrupt to CPU

PEIF

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 22

 

©

 

 1996 Microchip Technology Inc.

 

5.1

Interrupt Status Register (INTSTA)

 

The Interrupt Status/Control register (INTSTA) records

the individual interrupt requests in flag bits, and con-

tains the individual interrupt enable bits (not for the

peripherals).

The PEIF bit is a read only, bit wise OR of all the periph-

eral flag bits in the PIR register (Figure 5-4).

Care should be taken when clearing any of the INTSTA

register enable bits when interrupts are enabled

(GLINTD is clear). If any of the INTSTA flag bits (T0IF,

INTF, T0CKIF, or PEIF) are set in the same instruction

cycle as the corresponding interrupt enable bit is

cleared, the device will vector to the reset address

(0x00).

When disabling any of the INTSTA enable bits, the

GLINTD bit should be set (disabled).  

 

Note:

 

T0IF, INTF, T0CKIF, or PEIF will be set by

the specified condition, even if the corre-

sponding interrupt enable bit is clear (inter-

rupt disabled) or the GLINTD bit is set (all

interrupts disabled).

 

FIGURE 5-2: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)   

 

R - 0

R/W - 0 R/W - 0 R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

PEIF

T0CKIF

T0IF

INTF

PEIE

T0CKIE

T0IE

INTE

 

R = Readable bit

W = Writable bit

- n = Value at POR reset

 

bit7

bit0

bit 7:

 

PEIF

 

: Peripheral Interrupt Flag bit

This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.

1 = A peripheral interrupt is pending

0 = No peripheral interrupt is pending

bit 6:

 

T0CKIF

 

: External Interrupt on T0CKI Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h).

1 = The software specified edge occurred on the RA1/T0CKI pin

0 = The software specified edge did not occur on the RA1/T0CKI pin

bit 5:

 

T0IF

 

: TMR0 Overflow Interrupt Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h).

1 = TMR0 overflowed

0 = TMR0 did not overflow

bit  4:

 

INTF

 

: External Interrupt on INT Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h).

1 = The software specified edge occurred on the RA0/INT pin

0 = The software specified edge did not occur on the RA0/INT pin

bit 3:

 

PEIE

 

: Peripheral Interrupt Enable bit

This bit enables all peripheral interrupts that have their corresponding enable bits set.

1 = Enable peripheral interrupts

0 = Disable peripheral interrupts

bit 2:

 

T0CKIE

 

: External Interrupt on T0CKI Pin Enable bit

1 = Enable software specified edge interrupt on the RA1/T0CKI pin

0 = Disable interrupt on the RA1/T0CKI pin

bit 1:

 

T0IE

 

: TMR0 Overflow Interrupt Enable bit

1 = Enable TMR0 overflow interrupt

0 = Disable TMR0 overflow interrupt

bit 0:

 

INTE

 

: External Interrupt on RA0/INT Pin Enable bit

1 = Enable software specified edge interrupt on the RA0/INT pin

0 = Disable software specified edge interrupt on the RA0/INT pin

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 23

 

PIC17C4X

 

5.2

Peripheral Interrupt Enable Register 

(PIE)

 

This register contains the individual flag bits for the

Peripheral interrupts.

 

FIGURE 5-3: PIE REGISTER (ADDRESS: 17h, BANK 1)   

 

R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0

RBIE

TMR3IE TMR2IE TMR1IE CA2IE

CA1IE

TXIE

RCIE

 

R = Readable bit

W = Writable bit

-n = Value at POR reset

 

bit7

bit0

bit 7:

 

RBIE

 

: PORTB Interrupt on Change Enable bit

1 = Enable PORTB interrupt on change

0 = Disable PORTB interrupt on change

bit 6:

 

TMR3IE

 

: Timer3 Interrupt Enable bit

1 = Enable Timer3 interrupt

0 = Disable Timer3 interrupt

bit 5:

 

TMR2IE

 

: Timer2 Interrupt Enable bit

1 = Enable Timer2 interrupt

0 = Disable Timer2 interrupt

bit 4:

 

TMR1IE

 

: Timer1 Interrupt Enable bit

1 = Enable Timer1 interrupt

0 = Disable Timer1 interrupt

bit 3:

 

CA2IE

 

: Capture2 Interrupt Enable bit

1 = Enable Capture interrupt on RB1/CAP2 pin

0 = Disable Capture interrupt on RB1/CAP2 pin

bit 2:

 

CA1IE

 

: Capture1 Interrupt Enable bit

1 = Enable Capture interrupt on RB2/CAP1 pin

0 = Disable Capture interrupt on RB2/CAP1 pin

bit 1:

 

TXIE

 

: USART Transmit Interrupt Enable bit

1 = Enable Transmit buffer empty interrupt

0 = Disable Transmit buffer empty interrupt

bit 0:

 

RCIE

 

: USART Receive Interrupt Enable bit

1 = Enable Receive buffer full interrupt

0 = Disable Receive buffer full interrupt

background image

 

PIC17C4X

 

DS30412C-page 24

 

©

 

 1996 Microchip Technology Inc.

 

5.3

Peripheral Interrupt Request Register 

(PIR)

 

This register contains the individual flag bits for the

peripheral interrupts.       

 

Note:

 

These bits will be set by the specified con-

dition, even if the corresponding interrupt

enable bit is cleared (interrupt disabled), or

the GLINTD bit is set (all interrupts dis-

abled). Before enabling an interrupt, the

user may wish to clear the interrupt flag to

ensure that the program does not immedi-

ately branch to the peripheral interrupt ser-

vice routine.

 

FIGURE 5-4: PIR REGISTER (ADDRESS: 16h, BANK 1)   

 

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R - 1

R - 0

RBIF

TMR3IF TMR2IF TMR1IF

CA2IF

CA1IF

TXIF

RCIF

 

R = Readable bit

W = Writable bit

-n = Value at POR reset

 

bit7

bit0

bit 7:

 

RBIF

 

: PORTB Interrupt on Change Flag bit

1 = One of the PORTB inputs changed (Software must end the mismatch condition)

0 = None of the PORTB inputs have changed

bit 6:

 

TMR3IF

 

: Timer3 Interrupt Flag bit

If Capture1 is enabled (CA1/PR3 = 1)

1 = Timer3 overflowed

0 = Timer3 did not overflow

If Capture1 is disabled (CA1/PR3 = 0)

1 = Timer3 value has rolled over to 0000h from equalling the period register (PR3H:PR3L) value

0 = Timer3 value has not rolled over to 0000h from equalling the period register (PR3H:PR3L) value

bit 5:

 

TMR2IF

 

: Timer2 Interrupt Flag bit

1 = Timer2 value has rolled over to 0000h from equalling the period register (PR2) value

0 = Timer2 value has not rolled over to 0000h from equalling the period register (PR2) value

bit 4:

 

TMR1IF

 

: Timer1 Interrupt Flag bit

If Timer1 is in 8-bit mode (T16 = 0)

1 = Timer1 value has rolled over to 0000h from equalling the period register (PR) value

0 = Timer1 value has not rolled over to 0000h from equalling the period register (PR2) value

If Timer1 is in 16-bit mode (T16 = 1)

1 = TMR1:TMR2 value has rolled over to 0000h from equalling the period register (PR1:PR2) value

0 = TMR1:TMR2 value has not rolled over to 0000h from equalling the period register (PR1:PR2) value

bit 3:

 

CA2IF

 

: Capture2 Interrupt Flag bit

1 = Capture event occurred on RB1/CAP2 pin

0 = Capture event did not occur on RB1/CAP2 pin

bit 2:

 

CA1IF

 

: Capture1 Interrupt Flag bit

1 = Capture event occurred on RB0/CAP1 pin

0 = Capture event did not occur on RB0/CAP1 pin

bit 1:

 

TXIF

 

: USART Transmit Interrupt Flag bit

1 = Transmit buffer is empty

0 = Transmit buffer is full

bit 0:

 

RCIF

 

: USART Receive Interrupt Flag bit

1 = Receive buffer is full

0 = Receive buffer is empty

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 25

 

PIC17C4X

 

5.4

Interrupt Operation

 

Global Interrupt Disable bit, GLINTD (CPUSTA<4>),

enables all unmasked interrupts (if clear) or disables all

interrupts (if set). Individual interrupts can be disabled

through their corresponding enable bits in the INTSTA

register. Peripheral interrupts need either the global

peripheral enable PEIE bit disabled, or the specific

peripheral enable bit disabled. Disabling the peripher-

als via the global peripheral enable bit, disables all

peripheral interrupts. GLINTD is set on reset (interrupts

disabled).

The 

 

RETFIE

 

 instruction allows returning from interrupt

and re-enable interrupts at the same time.

When an interrupt is responded to, the GLINTD bit is

automatically set to disable any further interrupt, the

return address is pushed onto the stack and the PC is

loaded with interrupt vector. There are four interrupt

vectors to reduce interrupt latency.

The peripheral interrupt vector has multiple interrupt

sources. Once in the peripheral interrupt service rou-

tine, the source(s) of the interrupt can be determined by

polling the interrupt flag bits. The peripheral interrupt

flag bit(s) must be cleared in software before re-

enabling interrupts to avoid continuous interrupts. 

The PIC17C4X devices have four interrupt vectors.

These vectors and their hardware priority are shown in

Table 5-1. If two enabled interrupts occur “at the same

time”, the interrupt of the highest priority will be ser-

viced first. This means that the vector address of that

interrupt will be loaded into the program counter (PC).

 

TABLE 5-1:

INTERRUPT VECTORS/

PRIORITIES        

 

Address

Vector

Priority

 

0008h

External Interrupt on RA0/

INT pin (INTF)

1 (Highest)

0010h

TMR0 overflow interrupt 

(T0IF)

2

0018h

External Interrupt on T0CKI 

(T0CKIF)

3

0020h

Peripherals (PEIF)

4 (Lowest)

 

Note 1:

 

Individual interrupt flag bits are set regard-

less of the status of their corresponding 

mask bit or the GLINTD bit.

 

Note 2:

 

When disabling any of the INTSTA enable

bits, the GLINTD bit should be set

(disabled).  

 

Note 3:

 

For the PIC17C42 only:

If an interrupt occurs while the Global Inter-

rupt Disable (GLINTD) bit is being set, the

GLINTD bit may unintentionally be re-

enabled by the user’s Interrupt Service

Routine (the 

 

RETFIE

 

 instruction). The

events that would cause this to occur are:

1.

An interrupt occurs simultaneously

with an instruction that sets the

GLINTD bit.

2.

The program branches to the Interrupt

vector and executes the Interrupt Ser-

vice Routine.

3.

The Interrupt Service Routine com-

pletes with the execution of the 

 

RET-

FIE

 

 instruction. This causes the

GLINTD bit to be cleared (enables

interrupts), and the program returns to

the instruction after the one which was

meant to disable interrupts.

The method to ensure that interrupts are

globally disabled is:

1.

Ensure that the GLINTD bit was set by

the instruction, as shown in the follow-

ing code:

 

LOOP   BSF    CPUSTA, GLINTD ; Disable Global

                             ; Interrupt

       BTFSS  CPUSTA, GLINTD ; Global Interrupt

                             ; Disabled?

       GOTO   LOOP           ; NO, try again

                             ; YES, continue

                             ; with program

                             ; low

background image

 

PIC17C4X

 

DS30412C-page 26

 

©

 

 1996 Microchip Technology Inc.

 

5.5

RA0/INT Interrupt

 

The external interrupt on the RA0/INT pin is edge trig-

gered. Either the rising edge, if INTEDG bit

(T0STA<7>) is set, or the falling edge, if INTEDG bit is

clear. When a valid edge appears on the RA0/INT pin,

the INTF bit (INTSTA<4>) is set. This interrupt can be

disabled by clearing the INTE control bit (INTSTA<0>).

The INT interrupt can wake the processor from SLEEP.

See Section 14.4 for details on SLEEP operation.

 

5.6

TMR0 Interrupt

 

An overflow (FFFFh 

 

 

 0000h) in TMR0 will set the

T0IF (INTSTA<5>) bit. The interrupt can be enabled/

disabled by setting/clearing the T0IE control bit

(INTSTA<1>). For operation of the Timer0 module, see

Section 11.0. 

 

5.7

T0CKI Interrupt

 

The external interrupt on the RA1/T0CKI pin is edge

triggered. Either the rising edge, if the T0SE bit

(T0STA<6>) is set, or the falling edge, if the T0SE bit is

clear. When a valid edge appears on the RA1/T0CKI

pin, the T0CKIF bit (INTSTA<6>) is set. This interrupt

can be disabled by clearing the T0CKIE control bit

(INTSTA<2>). The T0CKI interrupt can wake up the

processor from SLEEP. See Section 14.4 for details on

SLEEP operation.

 

5.8

Peripheral Interrupt

 

The peripheral interrupt flag indicates that at least one

of the peripheral interrupts occurred (PEIF is set). The

PEIF bit is a read only bit, and is a bit wise OR of all the

flag bits in the PIR register AND’ed with the corre-

sponding enable bits in the PIE register. Some of the

peripheral interrupts can wake the processor from

SLEEP. See Section 14.4 for details on SLEEP opera-

tion.

 

FIGURE 5-5:

INT PIN / T0CKI PIN INTERRUPT TIMING     

Q2

Q1

Q3 Q4

Q2

Q1

Q3 Q4

Q2

Q1

Q3 Q4

Q2

Q1

Q3 Q4

Q2

Q1

Q3 Q4

Q2

Q1

Q3 Q4

Q2

Q1

Q3 Q4

OSC1

OSC2

RA0/INT or 

RA1/T0CKI 

INTF or

T0CKIF

GLINTD

PC

Instruction

executed

System Bus

Instruction

Fetched

PC

PC + 1

Addr (Vector)

PC

Inst (PC)

Inst (PC+1)

Inst (PC)

Dummy

Dummy

YY

YY + 1

RETFIE

RETFIE

Inst (PC+1)

Inst (Vector)

Addr

Addr

Addr

Addr

Addr

Inst (YY + 1)

Dummy

PC + 1

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 27

 

PIC17C4X

 

5.9

Context Saving During Interrupts

 

During an interrupt, only the returned PC value is saved

on the stack. Typically, users may wish to save key reg-

isters during an interrupt; e.g. WREG, ALUSTA and the

BSR registers. This requires implementation in soft-

ware.

Example 5-1 shows the saving and restoring of infor-

mation for an interrupt service routine. The PUSH and

POP routines could either be in each interrupt service

routine or could be subroutines that were called.

Depending on the application, other registers may also

need to be saved, such as PCLATH.

 

EXAMPLE 5-1:

SAVING STATUS AND WREG IN RAM

 

;

; The addresses that are used to store the CPUSTA and WREG values

; must be in the data memory address range of 18h - 1Fh. Up to 

; 8 locations can be saved and restored using

; the MOVFP instruction. This instruction neither affects the status

; bits, nor corrupts the WREG register.

;

;

PUSH    MOVFP   WREG, TEMP_W         ; Save WREG

        MOVFP   ALUSTA, TEMP_STATUS  ; Save ALUSTA

        MOVFP   BSR, TEMP_BSR        ; Save BSR

ISR     :                            ; This is the interrupt service routine

        :

POP     MOVFP   TEMP_W, WREG         ; Restore WREG

        MOVFP   TEMP_STATUS, ALUSTA  ; Restore ALUSTA

        MOVFP   TEMP_BSR, BSR        ; Restore BSR

        RETFIE                       ; Return from Interrupts enabled

background image

 

PIC17C4X

 

DS30412C-page 28

 

©

 

 1996 Microchip Technology Inc.

 

NOTES:

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 29

 

PIC17C4X

 

6.0

MEMORY ORGANIZATION

 

There are two memory blocks in the PIC17C4X; pro-

gram memory and data memory. Each block has its

own bus, so that access to each block can occur during

the same oscillator cycle.

The data memory can further be broken down into Gen-

eral Purpose RAM and the Special Function Registers

(SFRs). The operation of the SFRs that control the

“core” are described here. The SFRs used to control

the peripheral modules are described in the section dis-

cussing each individual peripheral module.

 

6.1

Program Memory Organization

 

PIC17C4X devices have a 16-bit program counter

capable of addressing a 64K  x 16 program memory

space. The reset vector is at 0000h and the interrupt

vectors are at 0008h, 0010h, 0018h, and 0020h

(Figure 6-1).

6.1.1

PROGRAM MEMORY OPERATION

The PIC17C4X can operate in one of four possible pro-

gram memory configurations. The configuration is

selected by two configuration bits. The possible modes

are:

• Microprocessor

• Microcontroller

• Extended Microcontroller

• Protected Microcontroller

The microcontroller and protected microcontroller

modes only allow internal execution. Any access

beyond the program memory reads unknown data.

The protected microcontroller mode also enables the

code protection feature.

The extended microcontroller mode accesses both the

internal program memory as well as external program

memory. Execution automatically switches between

internal and external memory. The 16-bits of address

allow a program memory range of 64K-words.

The microprocessor mode only accesses the external

program memory. The on-chip program memory is

ignored. The 16-bits of address allow a program mem-

ory range of 64K-words. Microprocessor mode is the

default mode of an unprogrammed device.

The different modes allow different access to the con-

figuration bits, test memory, and boot ROM. Table 6-1

lists which modes can access which areas in memory.

Test Memory and Boot Memory are not required for

normal operation of the device. Care should be taken to

ensure that no unintended branches occur to these

areas.

 

FIGURE 6-1:

PROGRAM MEMORY MAP 

AND STACK       

PC<15:0>

Stack Level 1

Stack Level 16

Reset Vector

INT Pin Interrupt Vector

Timer0 Interrupt Vector

T0CKI Pin Interrupt Vector

Peripheral Interrupt Vector

FOSC0

FOSC1

WDTPS0

WDTPS1

PM0

Reserved

PM1

Reserved

Configur

ation Memor

y

Space

User Memor

y

Space 

(1)

CALL, RETURN

RETFIE, RETLW

16

0000h

0008h

0010h

0020h

0021h

0018h

7FFh

FDFFh

FE00h

FE01h

FE02h

FE03h

FE04h

FE05h

FE06h

FE07h

FE0Fh

Test EPROM

Boot ROM

FE10h

FF5Fh

FF60h

FFFFh

FFFh

1FFFh

(PIC17C42,

(PIC17C43

(PIC17C44)

Reserved

PM2

(2)

FE08h

 PIC17CR42,

 PIC17C42A)

 PIC17CR43)

Note 1:

User memory space may be internal, external, or 

both. The memory configuration depends on the 

processor mode.

2:

This location is reserved on the PIC17C42.

FE0Eh

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 30

 

©

 

 1996 Microchip Technology Inc.

 

TABLE 6-1:

MODE MEMORY ACCESS  

 

Operating

Mode

Internal 

Program 

Memory

Configuration Bits,

Test Memory,

Boot ROM

 

Microprocessor

No Access

No Access

Microcontroller

Access

Access

Extended

Microcontroller

Access

No Access

Protected

Microcontroller

Access

Access

 

The PIC17C4X can operate in modes where the pro-

gram memory is off-chip. They are the microprocessor

and extended microcontroller modes. The micropro-

cessor mode is the default for an unprogrammed

device.

Regardless of the processor mode, data memory is

always on-chip.

 

FIGURE 6-2:

MEMORY MAP IN DIFFERENT MODES   

Microprocessor

Mode

0000h

FFFFh

External

Program

Memory

External

Program

Memory

0800h

FFFFh

0000h

07FFh

On-chip

Program

Memory

Extended

Microcontroller

Mode

Microcontroller

Modes

0000h

07FFh

0800h

FE00h

FFFFh

OFF-CHIP

ON-CHIP

OFF-CHIP

ON-CHIP

OFF-CHIP

ON-CHIP

00h

FFh

00h

FFh

00h

FFh

OFF-CHIP

ON-CHIP

OFF-CHIP

ON-CHIP

OFF-CHIP

ON-CHIP

PR

OGRAM SP

A

C

E

D

A

T

A

 SP

A

C

E

Config. Bits

Test Memory

Boot ROM

PIC17C42,

0000h

FFFFh

External

Program

Memory

External

Program

Memory

1000h/

FFFFh

0000h

0000h

0FFFh/1FFFh

1000h/2000h

FE00h

FFFFh

OFF-CHIP

ON-CHIP

OFF-CHIP

ON-CHIP

OFF-CHIP

ON-CHIP

Config. Bits

Test Memory

Boot ROM

PR

OGRAM SP

A

C

E

D

A

T

A

 SP

A

C

E

00h

FFh

1FFh

120h

OFF-CHIP

ON-CHIP

00h

FFh

1FFh

120h

OFF-CHIP

ON-CHIP

00h

FFh

1FFh

120h

OFF-CHIP

ON-CHIP

0FFFh/1FFFh

2000h

PIC17CR42,

PIC17C42A

PIC17C43,

PIC17CR43,

PIC17C44

On-chip

Program

Memory

On-chip

Program

Memory

On-chip

Program

Memory

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 31

 

PIC17C4X

 

6.1.2

EXTERNAL MEMORY INTERFACE

When either microprocessor or extended microcontrol-

ler mode is selected, PORTC, PORTD and PORTE are

configured as the system bus. PORTC and PORTD are

the multiplexed address/data bus and PORTE is for the

control signals. External components are needed to

demultiplex the address and data. This can be done as

shown in Figure 6-4. The waveforms of address and

data are shown in Figure 6-3. For complete timings,

please refer to the electrical specification section.

 

FIGURE 6-3:

EXTERNAL PROGRAM 

MEMORY ACCESS 

WAVEFORMS   

 

The system bus requires that there is no bus conflict

(minimal leakage), so the output value (address) will be

capacitively held at the desired value.

As the speed of the processor increases, external

EPROM memory with faster access time must be used.

Table 6-2 lists external memory speed requirements for

a given PIC17C4X device frequency.

Q3

Q1

Q2

Q4

Q3

Q1

Q2

Q4

AD

<15:0>

ALE

OE

WR

'1'

Read cycle

Write cycle

Address out Data in

Address out

Data out

Q1

 

In extended microcontroller mode, when the device is

executing out of internal memory, the control signals

will continue to be active. That is, they indicate the

action that is occurring in the internal memory. The

external memory access is ignored.

This following selection is for use with Microchip

EPROMs. For interfacing to other manufacturers mem-

ory, please refer to the electrical specifications of the

desired PIC17C4X device, as well as the desired mem-

ory device to ensure compatibility. 

 

TABLE 6-2:

EPROM MEMORY ACCESS 

TIME ORDERING SUFFIX    

 

PIC17C4X

Oscillator 

Frequency

Instruction

 Cycle 

Time (T

 

CY

 

)

EPROM Suffix

PIC17C42

PIC17C43

PIC17C44

 

8 MHz

500 ns

-25

-25

16 MHz

250 ns

-12

-15

20 MHz

200 ns

-90

-10

25 MHz

160 ns

N.A.

-70

33 MHz

121 ns

N.A.

(1)

Note 1: The access times for this requires the use of 

fast SRAMS.

 

Note:

 

The external memory interface is not sup-

ported for the LC devices.

 

FIGURE 6-4:

TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM   

AD7-AD0

PIC17C4X

AD15-AD8

ALE

I/O

(1)

AD15-AD0

373

Memory

(MSB)

Ax-A0

D7-D0

A15-A0

Memory

(LSB)

Ax-A0

D7-D0

373

138

(1)

OE

WR

OE

OE

WR

WR

CE

CE

(2)

(2)

Note 1:

Use of I/O pins is only required for paged memory.

2:

This signal is unused for ROM and EPROM devices.

background image

 

PIC17C4X

 

DS30412C-page 32

 

©

 

 1996 Microchip Technology Inc.

 

6.2

Data Memory Organization

 

Data memory is partitioned into two areas. The first is

the General Purpose Registers (GPR) area, while the

second is the Special Function Registers (SFR) area.

The SFRs control the operation of the device.

Portions of data memory are banked, this is for both

areas. The GPR area is banked to allow greater than

232 bytes of general purpose RAM. SFRs are for the

registers that control the peripheral functions. Banking

requires the use of control bits for bank selection.

These control bits are located in the Bank Select Reg-

ister (BSR). If an access is made to a location outside

this banked region, the BSR bits are ignored.

Figure 6-5 shows the data memory map organization

for the PIC17C42 and Figure 6-6 for all of the other

PIC17C4X devices.

Instructions 

 

MOVPF

 

 and 

 

MOVFP

 

 provide the means to

move values from the peripheral area (“P”) to any loca-

tion in the register file (“F”), and vice-versa. The defini-

tion of the “P” range is from 0h to 1Fh, while the “F”

range is 0h to FFh. The “P” range has six more loca-

tions than peripheral registers (eight locations for the

PIC17C42 device) which can be used as General Pur-

pose Registers. This can be useful in some applications

where variables need to be copied to other locations in

the general purpose RAM (such as saving status infor-

mation during an interrupt).

The entire data memory can be accessed either directly

or indirectly through file select registers FSR0 and

FSR1 (Section 

6.4). Indirect addressing uses the

appropriate control bits of the BSR for accesses into the

banked areas of data memory. The BSR is explained in

greater detail in Section 6.8.

6.2.1

GENERAL PURPOSE REGISTER (GPR)

All devices have some amount of GPR area. The GPRs

are 8-bits wide. When the GPR area is greater than

232, it must be banked to allow access to the additional

memory space.

Only the PIC17C43 and PIC17C44 devices have

banked memory in the GPR area. To facilitate switching

between these banks, the 

 

MOVLR bank

 

 instruction has

been added to the instruction set. GPRs are not initial-

ized by a Power-on Reset and are unchanged on all

other resets.

6.2.2

SPECIAL FUNCTION REGISTERS (SFR)

The SFRs are used by the CPU and peripheral func-

tions to control the operation of the device (Figure 6-5

and Figure 6-6). These registers are static RAM.

The SFRs can be classified into two sets, those associ-

ated with the “core” function and those related to the

peripheral functions. Those registers related to the

“core” are described here, while those related to a

peripheral feature are described in the section for each

peripheral feature.

The peripheral registers are in the banked portion of

memory, while the core registers are in the unbanked

region. To facilitate switching between the peripheral

banks, the 

 

MOVLB bank

 

 instruction has been provided.

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 33

 

PIC17C4X

 

FIGURE 6-5:

PIC17C42 REGISTER FILE 

MAP  

 

Addr Unbanked

 

00h

 

INDF0

 

01h

 

FSR0

 

02h

 

PCL

 

03h

 

PCLATH

 

04h

 

ALUSTA

 

05h

 

T0STA

 

06h

 

CPUSTA

 

07h

 

INTSTA

 

08h

 

INDF1

 

09h

 

FSR1

 

0Ah

 

WREG

 

0Bh

 

TMR0L

 

0Ch

 

TMR0H

 

0Dh

 

TBLPTRL

 

0Eh

 

TBLPTRH

 

0Fh

 

BSR

 

Bank 0

Bank 1 

 

(1)

 

Bank 2 

 

(1)

 

Bank 3 

 

(1)

 

10h

 

PORTA

DDRC

TMR1

PW1DCL

 

11h

 

DDRB

PORTC

TMR2

PW2DCL

 

12h

 

PORTB

DDRD

TMR3L

PW1DCH

 

13h

 

RCSTA

PORTD

TMR3H

PW2DCH

 

14h

 

RCREG

DDRE

PR1

CA2L

 

15h

 

TXSTA

PORTE

PR2

CA2H

 

16h

 

TXREG

PIR

PR3L/CA1L

TCON1

 

17h

 

SPBRG

PIE

PR3H/CA1H

TCON2

 

18h

1Fh

 

General 

Purpose 

RAM

 

20h

FFh

Note 1: SFR file locations 10h - 17h are banked. All 

other SFRs ignore the Bank Select Register 

(BSR) bits.

 

FIGURE 6-6:

PIC17CR42/42A/43/R43/44 

REGISTER FILE MAP             

 

 

 

Addr Unbanked

 

00h

 

INDF0

 

01h

 

FSR0

 

02h

 

PCL

 

03h

 

PCLATH

 

04h

 

ALUSTA

 

05h

 

T0STA

 

06h

 

CPUSTA

 

07h

 

INTSTA

 

08h

 

INDF1

 

09h

 

FSR1

 

0Ah

 

WREG

 

0Bh

 

TMR0L

 

0Ch

 

TMR0H

 

0Dh

 

TBLPTRL

 

0Eh

 

TBLPTRH

 

0Fh

 

BSR

 

Bank 0

Bank 1 

 

(1)

 

Bank 2 

 

(1)

 

Bank 3 

 

(1)

 

10h

 

PORTA

DDRC

TMR1

PW1DCL

 

11h

 

DDRB

PORTC

TMR2

PW2DCL

 

12h

 

PORTB

DDRD

TMR3L

PW1DCH

 

13h

 

RCSTA

PORTD

TMR3H

PW2DCH

 

14h

 

RCREG

DDRE

PR1

CA2L

 

15h

 

TXSTA

PORTE

PR2

CA2H

 

16h

 

TXREG

PIR

PR3L/CA1L

TCON1

 

17h

 

SPBRG

PIE

PR3H/CA1H

TCON2

 

18h

 

PRODL

 

19h

 

PRODH

 

1Ah

1Fh

 

General 

Purpose 

RAM 

 

(2)

 

20h

FFh

 

General 

Purpose 

RAM 

 

(2)

 

Note 1: SFR file locations 10h - 17h are banked. All 

other SFRs ignore the Bank Select Register 

(BSR) bits.

2: General Purpose Registers (GPR) locations 

20h - FFh and 120h - 1FFh are banked. All 

other GPRs ignore the Bank Select Register 

(BSR) bits.

background image

 

PIC17C4X

 

DS30412C-page 34

 

©

 

 1996 Microchip Technology Inc.

 

TABLE 6-3:

SPECIAL FUNCTION REGISTERS   

 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on 

Power-on 

Reset

Value on all 

other 

resets (3) 

 

 

 

Unbanked

 

00h

INDF0

Uses contents of FSR0 to address data memory (not a physical register)

 

---- ----

---- ----

 

01h

FSR0

Indirect data memory address pointer 0

 

xxxx xxxx

uuuu uuuu

 

02h

PCL

Low order 8-bits of PC

 

0000 0000

0000 0000

 

03h

 

(1)

 

PCLATH 

Holding register for upper 8-bits of PC

 

0000 0000

uuuu uuuu

 

04h

ALUSTA

FS3

FS2

FS1

FS0

OV

Z

DC

C

 

1111 xxxx

1111 uuuu

 

05h

T0STA

INTEDG

T0SE

T0CS

PS3

PS2

PS1

PS0

 

0000 000-

0000 000-

 

06h

 

(2)

 

CPUSTA   

STKAV

GLINTD

TO

PD

 

--11 11--

--11 qq--

 

07h

INTSTA

PEIF

T0CKIF

T0IF

INTF

PEIE

T0CKIE

T0IE

INTE

 

0000 0000

0000 0000

 

08h

INDF1

Uses contents of FSR1 to address data memory (not a physical register)

 

---- ----

---- ----

09h

FSR1

Indirect data memory address pointer 1

xxxx xxxx

uuuu uuuu

0Ah

WREG

Working register

xxxx xxxx

uuuu uuuu

0Bh

TMR0L

TMR0 register; low byte 

xxxx xxxx

uuuu uuuu

0Ch

TMR0H

TMR0 register; high byte 

xxxx xxxx

uuuu uuuu

0Dh

TBLPTRL

Low byte of program memory table pointer

(4)

(4)

0Eh

TBLPTRH

High byte of program memory table pointer

(4)

(4)

0Fh

BSR

Bank select register

0000 0000

0000 0000

Bank 0

10h

PORTA

RBPU

RA5

RA4

RA3

RA2

RA1/T0CKI

RA0/INT

0-xx xxxx

0-uu uuuu

11h

DDRB

Data direction register for PORTB

1111 1111

1111 1111

12h

PORTB

PORTB data latch

xxxx xxxx

uuuu uuuu

13h

RCSTA

SPEN

RX9

SREN

CREN

FERR

OERR

RX9D

0000 -00x

0000 -00u

14h

RCREG

Serial port receive register

xxxx xxxx

uuuu uuuu

15h

TXSTA

CSRC

TX9

TXEN

SYNC

TRMT

TX9D

0000 --1x

0000 --1u

16h

TXREG

Serial port transmit register

xxxx xxxx

uuuu uuuu

17h

SPBRG

Baud rate generator register

xxxx xxxx

uuuu uuuu

Bank 1

10h

DDRC

Data direction register for PORTC

1111 1111

1111 1111

11h

PORTC

RC7/

AD7

RC6/

AD6

RC5/

AD5

RC4/

AD4

RC3/

AD3

RC2/

AD2

RC1/

AD1

RC0/

AD0

xxxx xxxx

uuuu uuuu

12h

DDRD

Data direction register for PORTD

1111 1111

1111 1111

13h

PORTD

RD7/

AD15

RD6/

AD14

RD5/

AD13

RD4/

AD12

RD3/

AD11

RD2/

AD10

RD1/

AD9

RD0/

AD8

xxxx xxxx

uuuu uuuu

14h

DDRE

Data direction register for PORTE

---- -111

---- -111

15h

PORTE

RE2/WR

RE1/OE

RE0/ALE

---- -xxx

---- -uuu

16h

PIR

RBIF

TMR3IF

TMR2IF

TMR1IF

CA2IF

CA1IF

TXIF

RCIF

0000 0010

0000 0010

17h

PIE

RBIE

TMR3IE

TMR2IE

TMR1IE

CA2IE

CA1IE

TXIE

RCIE

0000 0000

0000 0000

Legend:

x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.

Note 1:

The upper byte of the program counter is not directly accessible.  PCLATH is a holding register for PC<15:8> whose contents are updated 

from or transferred to the upper byte of the program counter.

2:

The TO and PD status bits in CPUSTA are not affected by a MCLR reset. 

3:

Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

4:

The following values are for both TBLPTRL and TBLPTRH:

All PIC17C4X devices (Power-on Reset 0000 0000) and (All other resets 0000 0000)

except the PIC17C42 (Power-on Reset xxxx xxxx) and (All other resets uuuu uuuu)

5:

The PRODL and PRODH registers are not implemented on the PIC17C42.

background image

©

 1996 Microchip Technology Inc.

DS30412C-page 35

PIC17C4X

Bank 2

10h

TMR1

Timer1

xxxx xxxx

uuuu uuuu

11h

TMR2

Timer2

xxxx xxxx

uuuu uuuu

12h

TMR3L

TMR3 register; low byte 

xxxx xxxx

uuuu uuuu

13h

TMR3H

TMR3 register; high byte 

xxxx xxxx

uuuu uuuu

14h

PR1

Timer1 period register

xxxx xxxx

uuuu uuuu

15h

PR2

Timer2 period register

xxxx xxxx

uuuu uuuu

16h

PR3L/CA1L

Timer3 period register, low byte/capture1 register; low byte

xxxx xxxx

uuuu uuuu

17h

PR3H/CA1H

Timer3 period register, high byte/capture1 register; high byte

xxxx xxxx

uuuu uuuu

Bank 3

10h

PW1DCL

DC1

DC0

xx-- ----

uu-- ----

11h

PW2DCL

DC1

DC0

TM2PW2

xx0- ----

uu0- ----

12h

PW1DCH

DC9

DC8

DC7

DC6

DC5

DC4

DC3

DC2

xxxx xxxx

uuuu uuuu

13h

PW2DCH

DC9

DC8

DC7

DC6

DC5

DC4

DC3

DC2

xxxx xxxx

uuuu uuuu

14h

CA2L

Capture2 low byte

xxxx xxxx

uuuu uuuu

15h

CA2H

Capture2 high byte

xxxx xxxx

uuuu uuuu

16h

TCON1

CA2ED1

CA2ED0

CA1ED1

CA1ED0

T16

TMR3CS

TMR2CS

TMR1CS

0000 0000

0000 0000

17h

TCON2

CA2OVF CA1OVF PWM2ON

PWM1ON

CA1/PR3 TMR3ON

TMR2ON

TMR1ON

0000 0000

0000 0000

 Unbanked

18h 

(5)

  PRODL

Low Byte of 16-bit Product (8 x 8 Hardware Multiply)

xxxx xxxx

uuuu uuuu

19h 

(5)

  PRODH

High Byte of 16-bit Product (8 x 8 Hardware Multiply)

xxxx xxxx

uuuu uuuu

TABLE 6-3:

SPECIAL FUNCTION REGISTERS  (Cont.’d) 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on 

Power-on 

Reset

Value on all 

other 

resets (3) 

Legend:

x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.

Note 1:

The upper byte of the program counter is not directly accessible.  PCLATH is a holding register for PC<15:8> whose contents are updated 

from or transferred to the upper byte of the program counter.

2:

The TO and PD status bits in CPUSTA are not affected by a MCLR reset. 

3:

Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

4:

The following values are for both TBLPTRL and TBLPTRH:

All PIC17C4X devices (Power-on Reset 0000 0000) and (All other resets 0000 0000)

except the PIC17C42 (Power-on Reset xxxx xxxx) and (All other resets uuuu uuuu)

5:

The PRODL and PRODH registers are not implemented on the PIC17C42.

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PIC17C4X

DS30412C-page 36

©

 1996 Microchip Technology Inc.

6.2.2.1

ALU STATUS REGISTER (ALUSTA)

The ALUSTA register contains the status bits of the

Arithmetic and Logic Unit and the mode control bits for

the indirect addressing register.

As with all the other registers, the ALUSTA register can

be the destination for any instruction. If the ALUSTA

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Therefore, the result of an instruction with

the ALUSTA register as destination may be different

than intended.

For example, 

CLRF ALUSTA

 will clear the upper four bits

and set the Z bit. This leaves the ALUSTA register as

0000u1uu

 (where 

u

 = unchanged).

It is recommended, therefore, that only 

BCF

BSF

SWAPF

and 

MOVWF

 instructions be used to alter the ALUSTA

register because these instructions do not affect any

status bit. To see how other instructions affect the sta-

tus bits, see the “Instruction Set Summary.”   

Arithmetic and Logic Unit (ALU) is capable of carrying

out arithmetic or logical operations on two operands or

a single operand. All single operand instructions oper-

ate either on the WREG register or a file register. For

two operand instructions, one of the operands is the

WREG register and the other one is either a file register

or an 8-bit immediate constant.

Note 1: The C and DC bits operate as a borrow

out bit in subtraction. See the 

SUBLW

 and

SUBWF

 instructions for examples.

Note 2: The overflow bit will be set if the 2’s com-

plement result exceeds +127 or is less

than -128.

FIGURE 6-7:

ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)    

   

R/W - 1

R/W - 1

R/W - 1

R/W - 1

R/W - x

R/W - x 

R/W - x

R/W - x

FS3

FS2

FS1

FS0

OV

Z

DC

C

R = Readable bit

W = Writable bit

-n = Value at POR reset

       (x = unknown)

bit7

bit0

bit 7-6:

FS3:FS2: FSR1 Mode Select bits

00 = Post auto-decrement FSR1 value

01 = Post auto-increment FSR1 value

1x = FSR1 value does not change

bit 5-4:

FS1:FS0: FSR0 Mode Select bits

00 = Post auto-decrement FSR0 value

01 = Post auto-increment FSR0 value

1x = FSR0 value does not change

bit 3:

OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude,

which causes the sign bit (bit7) to change state.

1 = Overflow occurred for signed arithmetic, (in this arithmetic operation)

0 = No overflow occurred

bit 2:

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The results of an arithmetic or logic operation is not zero

bit 1:

DC: Digit carry/borrow bit

For 

ADDWF

 and 

ADDLW

 instructions.

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

Note: For borrow the polarity is reversed.

bit 0:

C: carry/borrow bit

For 

ADDWF

 and 

ADDLW

 instructions.

1 = A carry-out from the most significant bit of the result occurred 

Note that a subtraction is executed by adding the two’s complement of the second operand. For rotate

(

RRCF

RLCF

) instructions, this bit is loaded with either the high or low order bit of the source register.

0 = No carry-out from the most significant bit of the result

Note: For borrow the polarity is reversed.

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©

 1996 Microchip Technology Inc.

DS30412C-page 37

PIC17C4X

6.2.2.2

CPU STATUS REGISTER (CPUSTA)

The CPUSTA register contains the status and control

bits for the CPU. This register is used to globally

enable/disable interrupts. If only a specific interrupt is

desired to be enabled/disabled, please refer to the

INTerrupt STAtus (INTSTA) register and the Peripheral

Interrupt Enable (PIE) register. This register also indi-

cates if the stack is available and contains the

Power-down (PD) and Time-out (TO) bits. The TO, PD,

and STKAV bits are not writable. These bits are set and

cleared according to device logic. Therefore, the result

of an instruction with the CPUSTA register as destina-

tion may be different than intended.

FIGURE 6-8:

CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)   

U - 0

U - 0

R - 1

R/W - 1

R - 1

R - 1 

U - 0

U - 0

STKAV GLINTD

TO

PD

R = Readable bit

W = Writable bit

U = Unimplemented bit, 

       Read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7-6:

Unimplemented: Read as '0'

bit 5:

STKAV: Stack Available bit

This bit indicates that the 4-bit stack pointer value is Fh, or has rolled over from Fh 

→ 

0h (stack overflow).

1 = Stack is available

0 = Stack is full, or a stack overflow may have occurred (Once this bit has been cleared by a 

stack overflow, only a device reset will set this bit)

bit 4:

GLINTD: Global Interrupt Disable bit

This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can

cause an interrupt.

1 = Disable all interrupts

0 = Enables all un-masked interrupts

bit 3:

TO: WDT Time-out Status bit

1 = After power-up or by a 

CLRWDT

 instruction

0 = A Watchdog Timer time-out occurred

bit 2:

PD: Power-down Status bit

1 = After power-up or by the 

CLRWDT

 instruction

0 = By execution of the 

SLEEP

 instruction

bit 1-0:

Unimplemented: Read as '0'

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PIC17C4X

DS30412C-page 38

©

 1996 Microchip Technology Inc.

6.2.2.3

TMR0 STATUS/CONTROL REGISTER 

(T0STA)

This register contains various control bits. Bit7

(INTEDG) is used to control the edge upon which a sig-

nal on the RA0/INT pin will set the RB0/INT interrupt

flag. The other bits configure the Timer0 prescaler and

clock source. (Figure 11-1).

FIGURE 6-9:

T0STA REGISTER (ADDRESS: 05h, UNBANKED)   

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

U - 0

INTEDG

T0SE

T0CS

PS3

PS2

PS1

PS0

R = Readable bit

W = Writable bit

U = Unimplemented, 

       reads as ‘0’

-n = Value at POR reset

bit7

bit0

bit 7:

INTEDG: RA0/INT Pin Interrupt Edge Select bit

This bit selects the edge upon which the interrupt is detected.

1 = Rising edge of RA0/INT pin generates interrupt

0 = Falling edge of RA0/INT pin generates interrupt

bit 6:

T0SE: Timer0 Clock Input Edge Select bit

This bit selects the edge upon which TMR0 will increment.

When T0CS = 0  

1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt

0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt

When T0CS = 1   

Don’t care

bit 5:

T0CS: Timer0 Clock Source Select bit

This bit selects the clock source for Timer0.

1 = Internal instruction clock cycle (T

CY

)

0 = T0CKI pin

bit 4-1:

PS3:PS0: Timer0 Prescale Selection bits

These bits select the prescale value for Timer0.      

bit  0:

Unimplemented: Read as '0'

PS3:PS0

Prescale Value

0000

0001

0010

0011

0100

0101

0110

0111

1xxx

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

1:256

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©

 1996 Microchip Technology Inc.

DS30412C-page 39

PIC17C4X

6.3

Stack Operation

The PIC17C4X devices have a 16 x 16-bit wide hard-

ware stack (Figure 6-1). The stack is not part of either

the program or data memory space, and the stack

pointer is neither readable nor writable. The PC is

“PUSHed” onto the stack when a 

CALL

 instruction is

executed or an interrupt is acknowledged. The stack is

“POPed” in the event of a 

RETURN

RETLW

, or a 

RETFIE

instruction execution. PCLATH is not affected by a

“PUSH” or a “POP” operation.

The stack operates as a circular buffer, with the stack

pointer initialized to '0' after all resets. There is a stack

available bit (STKAV) to allow software to ensure that

the stack has not overflowed. The STKAV bit is set after

a device reset. When the stack pointer equals Fh,

STKAV is cleared. When the stack pointer rolls over

from Fh to 0h, the STKAV bit will be held clear until a

device reset.   

After the device is “PUSHed” sixteen times (without a

“POP”), the seventeenth push overwrites the value

from the first push. The eighteenth push overwrites the

second push (and so on).  

 

Note 1: There is not a status bit for stack under-

flow. The STKAV bit can be used to detect

the underflow which results in the stack

pointer being at the top of stack.

Note 2: There are no instruction mnemonics

called PUSH or POP. These are actions

that occur from the execution of the 

CALL

,

RETURN

RETLW

, and 

RETFIE

 instruc-

tions, or the vectoring to an interrupt vec-

tor.

Note 3: After a reset, if a “POP” operation occurs

before a “PUSH” operation, the STKAV bit

will be cleared. This will appear as if the

stack is full (underflow has occurred). If a

“PUSH” operation occurs next (before

another “POP”), the STKAV bit will be

locked clear. Only a device reset will

cause this bit to set.

6.4

Indirect Addressing

Indirect addressing is a mode of addressing data

memory where the data memory address in the

instruction is not fixed. That is, the register that is to be

read or written can be modified by the program. This

can be useful for data tables in the data memory.

Figure 6-10 shows the operation of indirect address-

ing. This shows the moving of the value to the data

memory address specified by the value of the FSR

register.

Example 6-1 shows the use of indirect addressing to

clear RAM in a minimum number of instructions. A

similar concept could be used to move a defined num-

ber of bytes (block) of data to the USART transmit reg-

ister (TXREG). The starting address of the block of

data to be transmitted could easily be modified by the

program.

FIGURE 6-10: INDIRECT ADDRESSING   

Opcode

Address

File = INDFx

FSR

Instruction

Executed

Instruction

Fetched

RAM

Opcode

File

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PIC17C4X

DS30412C-page 40

©

 1996 Microchip Technology Inc.

6.4.1

INDIRECT ADDRESSING REGISTERS

The PIC17C4X has four registers for indirect address-

ing. These registers are:

• INDF0 and FSR0

• INDF1 and FSR1

Registers INDF0 and INDF1 are not physically imple-

mented. Reading or writing to these registers activates

indirect addressing, with the value in the correspond-

ing FSR register being the address of the data. The

FSR is an 8-bit register and allows addressing any-

where in the 256-byte data memory address range.

For banked memory, the bank of memory accessed is

specified by the value in the BSR.

If file INDF0 (or INDF1) itself is read indirectly via an

FSR, all '0's are read (Zero bit is set). Similarly, if

INDF0 (or INDF1) is written to indirectly, the operation

will be equivalent to a NOP, and the status bits are not

affected.

6.4.2

INDIRECT ADDRESSING OPERATION

The indirect addressing capability has been enhanced

over that of the PIC16CXX family. There are two con-

trol bits associated with each FSR register. These two

bits configure the FSR register to:

• Auto-decrement the value (address) in the FSR 

after an indirect access

• Auto-increment the value (address) in the FSR 

after an indirect access

• No change to the value (address) in the FSR after 

an indirect access

These control bits are located in the ALUSTA register.

The FSR1 register is controlled by the FS3:FS2 bits

and FSR0 is controlled by the FS1:FS0 bits.

When using the auto-increment or auto-decrement

features, the effect on the FSR is not reflected in the

ALUSTA register. For example, if the indirect address

causes the FSR to equal '0', the Z bit will not be set.

If the FSR register contains a value of 0h, an indirect

read will read 0h (Zero bit is set) while an indirect write

will be equivalent to a NOP (status bits are not

affected).

Indirect addressing allows single cycle data transfers

within the entire data space. This is possible with the

use of the 

MOVPF

 and 

MOVFP

 instructions, where either

'p' or 'f' is specified as INDF0 (or INDF1). 

If the source or destination of the indirect address is in

banked memory, the location accessed will be deter-

mined by the value in the BSR.

A simple program to clear RAM from 20h - FFh is

shown in Example 6-1.

EXAMPLE 6-1:

INDIRECT ADDRESSING

    MOVLW    0x20         ;

    MOVWF    FSR0         ; FSR0 = 20h

    BCF      ALUSTA, FS1  ; Increment FSR

    BSF      ALUSTA, FS0  ; after access

    BCF      ALUSTA, C    ; C = 0

    MOVLW    END_RAM + 1  ;

LP  CLRF     INDF0        ; Addr(FSR) = 0

    CPFSEQ   FSR0         ; FSR0 = END_RAM+1?

    GOTO     LP           ; NO, clear next

    :                     ; YES, All RAM is

    :                     ; cleared

6.5

Table Pointer (TBLPTRL and 

TBLPTRH)

File registers TBLPTRL and TBLPTRH form a 16-bit

pointer to address the 64K program memory space.

The table pointer is used by instructions 

TABLWT

 and

TABLRD

The 

TABLRD

 and the 

TABLWT

 instructions allow trans-

fer of data between program and data space. The table

pointer serves as the 16-bit address of the data word

within the program memory. For a more complete

description of these registers and the operation of Table

Reads and Table Writes, see Section 7.0.

6.6

Table Latch (TBLATH, TBLATL)

The table latch (TBLAT) is a 16-bit register, with

TBLATH and TBLATL referring to the high and low

bytes of the register. It is not mapped into data or pro-

gram memory. The table latch is used as a temporary

holding latch during data transfer between program and

data memory (see descriptions of instructions 

TABLRD

,

TABLWT

TLRD

 and 

TLWT

). For a more complete

description of these registers and the operation of Table

Reads and Table Writes, see Section 7.0.

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©

 1996 Microchip Technology Inc.

DS30412C-page 41

PIC17C4X

6.7

Program Counter Module

The Program Counter (PC) is a 16-bit register. PCL, the

low byte of the PC, is mapped in the data memory. PCL

is readable and writable just as is any other register.

PCH is the high byte of the PC and is not directly

addressable. Since PCH is not mapped in data or pro-

gram memory, an 8-bit register PCLATH (PC high latch)

is used as a holding latch for the high byte of the PC.

PCLATH is mapped into data memory. The user can

read or write PCH through PCLATH. 

The 16-bit wide PC is incremented after each instruc-

tion fetch during Q1 unless:

• Modified by 

GOTO

CALL

LCALL

RETURN

RETLW

or 

RETFIE

 instruction

• Modified by an interrupt response

• Due to destination write to PCL by an instruction

“Skips” are equivalent to a forced NOP cycle at the

skipped address.   

Figure 6-11 and Figure 6-12 show the operation of the

program counter for various situations.

FIGURE 6-11: PROGRAM COUNTER 

OPERATION

FIGURE 6-12: PROGRAM COUNTER USING 

THE CALL AND GOTO 

INSTRUCTIONS

Internal data bus <8>

PCLATH

8

8

8

PCH

PCL

8

15

0

7

5 4

0

12

8 7

0

8 7

Last write

to PCLATH

PCLATH

Opcode

5

3

8

PCH

PCL

13

15

Using Figure 6-11, the operations of the PC and

PCLATH for different instructions are as follows:

a)

LCALL

 instructions:

An 8-bit destination address is provided in the

instruction (opcode). PCLATH is unchanged.

PCLATH  

 PCH 

Opcode<7:0>  

 PCL 

b)

Read instructions on PCL:    

Any instruction that reads PCL.

PCL 

 data bus 

 ALU or destination

PCH 

 PCLATH

c)

Write instructions on PCL:    

Any instruction that writes to PCL.

8-bit data 

 data bus 

 PCL

PCLATH 

 PCH

d)

Read-Modify-Write instructions on PCL: 

Any instruction that does a read-write-modify

operation on PCL, such as 

ADDWF PCL

.

Read:

PCL 

 data bus 

 ALU

Write:

8-bit result 

 data bus 

 PCL

PCLATH 

 PCH

e)

RETURN

 instruction:   

PCH 

 PCLATH

Stack<MRU> 

 PC<15:0>

Using Figure 

6-12, the operation of the PC and

PCLATH for 

GOTO

 and 

CALL

 instructions is a follows:

CALL

GOTO

 instructions:

A 13-bit destination address is provided in the

instruction (opcode).

Opcode<12:0> 

 PC <12:0>

PC<15:13> 

 PCLATH<7:5>

Opcode<12:8> 

 PCLATH <4:0>

The read-modify-write only affects the PCL with the

result. PCH is loaded with the value in the PCLATH.

For example, 

ADDWF PCL

 will result in a jump within the

current page. If PC = 03F0h, WREG = 30h and

PCLATH = 03h before instruction, PC = 0320h after the

instruction. To accomplish a true 16-bit computed jump,

the user needs to compute the 16-bit destination

address, write the high byte to PCLATH and then write

the low value to PCL. 

The following PC related operations do not change

PCLATH:

a)

LCALL

RETLW

, and 

RETFIE

 instructions.

b)

Interrupt vector is forced onto the PC.

c)

Read-modify-write instructions on PCL (e.g. 

BSF

PCL

).

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PIC17C4X

DS30412C-page 42

©

 1996 Microchip Technology Inc.

6.8

Bank Select Register (BSR)

The BSR is used to switch between banks in the data

memory area (Figure 

6-13). In the PIC17C42,

PIC17CR42, and PIC17C42A only the lower nibble is

implemented. While in the PIC17C43, PIC17CR43,

and PIC17C44 devices, the entire byte is implemented.

The lower nibble is used to select the peripheral regis-

ter bank. The upper nibble is used to select the general

purpose memory bank.

All the Special Function Registers (SFRs) are mapped

into the data memory space. In order to accommodate

the large number of registers, a banking scheme has

been used. A segment of the SFRs, from address 10h

to address 17h, is banked. The lower nibble of the bank

select register (BSR) selects the currently active

“peripheral bank.” Effort has been made to group the

peripheral registers of related functionality in one bank.

However, it will still be necessary to switch from bank

to bank in order to address all peripherals related to a

single task. To assist this, a 

MOVLB bank

 instruction is

in the instruction set. 

For the PIC17C43, PIC17CR43, and PIC17C44

devices, the need for a large general purpose memory

space dictated a general purpose RAM banking

scheme. The upper nibble of the BSR selects the cur-

rently active general purpose RAM bank. To assist this,

MOVLR bank

 instruction has been provided in the

instruction set.

If the currently selected bank is not implemented (such

as Bank 13), any read will read all '0's. Any write is com-

pleted to the bit bucket and the ALU status bits will be

set/cleared as appropriate.  

Note:

Registers in Bank 15 in the Special Func-

tion Register area, are reserved for

Microchip use. Reading of registers in this

bank may cause random values to be read.

FIGURE 6-13: BSR OPERATION (PIC17C43/R43/44)   

7

4 3

0

10h

17h

BSR

0

1

2

3

4

15

• • •

20h

FFh

• • •

• • •

(1)

(2)

Bank 15

Bank 4

Bank 3

Bank 2

Bank 1

Bank 0

0

1

2

Bank 2

Bank 1

Bank 0

15

Bank 15

SFR

Banks

GPR

Banks

Address

Range

Note 1:

Only Banks 0 through Bank 3 are implemented. Selection of an unimplemented bank is not recommended

Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.

2:

Only Banks 0 and Bank 1 are implemented. Selection of an unimplemented bank is not recommended.

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©

 

 1996 Microchip Technology Inc.

DS30412C-page 43

 

PIC17C4X

 

7.0

TABLE READS AND TABLE 

WRITES

 

The PIC17C4X has four instructions that allow the pro-

cessor to move data from the data memory space to

the program memory space, and vice versa. Since the

program memory space is 16-bits wide and the data

memory space is 8-bits wide, two operations are

required to move 16-bit values to/from the data mem-

ory.

The 

 

TLWT t,f

 

 and 

 

TABLWT t,i,f

 

 instructions are

used to write data from the data memory space to the

program memory space. The 

 

TLRD t,f

 

 and 

 

TABLRD

t,i,f

 

 instructions are used to write data from the pro-

gram memory space to the data memory space.

The program memory can be internal or external. For

the program memory access to be external, the device

needs to be operating in extended microcontroller or

microprocessor mode.

Figure 7-1 through Figure 7-4 show the operation of

these four instructions.

 

FIGURE 7-1:

TLWT INSTRUCTION 

OPERATION   

TABLE POINTER

TABLE LATCH (16-bit)

PROGRAM MEMORY

DATA

MEMORY

TBLPTRH

TBLPTRL

TABLATH

TABLATL

f

TLWT  1,f

TLWT  0,f

1

Note 1: 8-bit value, from register 'f', loaded into the     

high or low byte in TABLAT (16-bit).

 

FIGURE 7-2:

TABLWT INSTRUCTION 

OPERATION   

TABLE POINTER

TABLE LATCH (16-bit)

PROGRAM MEMORY

DATA

MEMORY

TBLPTRH

TBLPTRL

TABLATH

TABLATL

f

TABLWT  1,i,f

TABLWT  0,i,f

1

Prog-Mem

(TBLPTR)

2

Note 1: 8-bit value, from register 'f', loaded into 

the     high or low byte in TABLAT (16-bit).

2: 16-bit TABLAT value written to address 

Program Memory (TBLPTR).

3: If “i” = 1, then TBLPTR = TBLPTR + 1, 

If “i” = 0, then TBLPTR is unchanged.

3

3

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 44

 

©

 

 1996 Microchip Technology Inc.

 

FIGURE 7-3:

TLRD INSTRUCTION 

OPERATION   

TABLE POINTER

TABLE LATCH (16-bit)

PROGRAM MEMORY

DATA

MEMORY

TBLPTRH

TBLPTRL

TABLATH

TABLATL

f

TLRD  1,f

TLRD  0,f

1

Note 1: 8-bit value, from TABLAT (16-bit) high or 

low byte,  loaded into register 'f'.

 

FIGURE 7-4:

TABLRD INSTRUCTION 

OPERATION   

TABLE POINTER

TABLE LATCH (16-bit)

PROGRAM MEMORY

DATA

MEMORY

TBLPTRH

TBLPTRL

TABLATH

TABLATL

f

TABLRD  1,i,f

TABLRD  0,i,f

1

Prog-Mem

(TBLPTR)

2

Note 1: 8-bit value, from TABLAT (16-bit) high or 

low byte, loaded into register 'f'.

2: 16-bit value at Program Memory (TBLPTR) 

loaded into TABLAT register.

3: If “i” = 1, then TBLPTR = TBLPTR + 1,

If “i” = 0, then TBLPTR is unchanged.

3

3

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 45

 

PIC17C4X

 

7.1

Table Writes to Internal Memory

 

A table write operation to internal memory causes a

long write operation. The long write is necessary for

programming the internal EPROM. Instruction execu-

tion is halted while in a long write cycle. The long write

will be terminated by any enabled interrupt. To ensure

that the EPROM location has been well programmed,

a minimum programming time is required (see specifi-

cation #D114 ). Having only one interrupt enabled to

terminate the long write ensures that no unintentional

interrupts will prematurely terminate the long write.

The sequence of events for programming an internal

program memory location should be:

1.

Disable all interrupt sources, except the source

to terminate EPROM program write.

2.

Raise MCLR/V

 

PP

 

 pin to the programming volt-

age.

3.

Clear the WDT.

4.

Do the table write. The interrupt will terminate

the long write.

5.

Verify the memory location (table read).   

 

Note:

 

Programming requirements must be met.

See timing specification in electrical spec-

ifications for the desired device. Violating

these specifications (including tempera-

ture) may result in EPROM locations that

are not fully programmed and may lose

their state over time.

7.1.1

TERMINATING LONG WRITES

An interrupt source or reset are the only events that

terminate a long write operation. Terminating the long

write from an interrupt source requires that the inter-

rupt enable and flag bits are set. The GLINTD bit only

enables the vectoring to the interrupt address.

If the T0CKI, RA0/INT, or TMR0 interrupt source is

used to terminate the long write; the interrupt flag, of

the highest priority enabled interrupt, will terminate the

long write and automatically be cleared.    

If a peripheral interrupt source is used to terminate the

long write, the interrupt enable and flag bits must be

set. The interrupt flag will not be automatically cleared

upon the vectoring to the interrupt vector address.

If the GLINTD bit is cleared prior to the long write,

when the long write is terminated, the program will

branch to the interrupt vector.

If the GLINTD bit is set prior to the long write, when

the long write is terminated, the program will not vector

to the interrupt address.

 

Note 1:

 

If an interrupt is pending, the TABLWT is

aborted (an NOP is executed). The

highest priority pending interrupt, from

the T0CKI, RA0/INT, or TMR0 sources

that is enabled, has its flag cleared.

 

Note 2:

 

If the interrupt is not being used for the

program write timing, the interrupt

should be disabled. This will ensure that

the interrupt is not lost, nor will it termi-

nate the long write prematurely.

 

TABLE 7-1:

INTERRUPT - TABLE WRITE INTERACTION

 

Interrupt

Source

GLINTD

Enable

Bit

Flag

Bit

Action

 

RA0/INT, TMR0, 

T0CKI

 

0

0

1

1

1

1

0

1

1

0

x

1

 

Terminate long table write (to internal program 

memory), branch to interrupt vector (branch clears 

flag bit).

None

None

Terminate table write, do not branch to interrupt 

vector (flag is automatically cleared).

Peripheral

 

0

0

1

1

1

1

0

1

1

0

x

1

 

Terminate table write, branch to interrupt vector.

None

None

Terminate table write, do not branch to interrupt 

vector (flag is set).

background image

 

PIC17C4X

 

DS30412C-page 46

 

©

 

 1996 Microchip Technology Inc.

 

7.2

Table Writes to External Memory

 

Table writes to external memory are always two-cycle

instructions. The second cycle writes the data to the

external memory location. The sequence of events for

an external memory write are the same for an internal

write.    

 

Note:

 

If an interrupt is pending or occurs during

the 

 

TABLWT

 

, the two cycle table write

completes. The RA0/INT, TMR0, or T0CKI

interrupt flag is automatically cleared or

the pending peripheral interrupt is

acknowledged.

7.2.2

TABLE WRITE CODE

The “i” operand of the 

 

TABLWT

 

 instruction can specify

that the value in the 16-bit TBLPTR register is auto-

matically incremented for the next write. In

Example 7-1, the TBLPTR register is not automatically

incremented.

 

EXAMPLE 7-1:

TABLE WRITE

 

  CLRWDT                  ; Clear WDT

  MOVLW   HIGH (TBL_ADDR) ; Load the Table

  MOVWF   TBLPTRH         ;   address

  MOVLW   LOW (TBL_ADDR)  ;

  MOVWF   TBLPTRL         ;

  MOVLW   HIGH (DATA)     ; Load HI byte

  TLWT    1, WREG         ;   in TABLATCH

  MOVLW   LOW (DATA)      ; Load LO byte

  TABLWT  0,0,WREG        ;   in TABLATCH

                          ;   and write to

                          ;   program memory

                          ;   (Ext. SRAM)

 

FIGURE 7-5:

TABLWT WRITE TIMING (EXTERNAL MEMORY)   

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

AD15:AD0

Instruction

fetched

Instruction

executed

ALE

OE

WR

TABLWT

INST (PC+1)

INST (PC-1)

TABLWT cycle1

TABLWT cycle2

INST (PC+2)

Data write cycle

'1'

PC

PC+1

TBL

PC+2

Data out

INST (PC+1) 

Note:

If external write GLINTD = '1', Enable bit = '1', '1' 

 Flag bit, Do table write. The highest pending interrupt is cleared.

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 47

 

PIC17C4X

 

FIGURE 7-6:

CONSECUTIVE TABLWT WRITE TIMING (EXTERNAL MEMORY)   

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

Instruction

fetched

Instruction

executed

ALE

OE

WR

PC

TABLWT1

TABLWT2

INST (PC+2)

INST (PC-1)

TABLWT1 cycle1 TABLWT1 cycle2 TABLWT2 cycle1 TABLWT2 cycle2

Data write cycle

Data write cycle

INST (PC+3)

PC+1

TBL1

PC+2

TBL2

PC+3

Data out 1

Data out 2

INST (PC+2)

background image

 

PIC17C4X

 

DS30412C-page 48

 

©

 

 1996 Microchip Technology Inc.

 

7.3

Table Reads

 

The table read allows the program memory to be read.

This allows constant data to be stored in the program

memory space, and retrieved into data memory when

needed. Example 7-2 reads the 16-bit value at pro-

gram memory address TBLPTR. After the dummy byte

has been read from the TABLATH, the TABLATH is

loaded with the 16-bit data from program memory

address TBLPTR + 1. The first read loads the data into

the latch, and can be considered a dummy read

(unknown data loaded into 'f'). INDF0 should be con-

figured for either auto-increment or auto-decrement.

 

EXAMPLE 7-2:

TABLE READ

 

  MOVLW   HIGH (TBL_ADDR) ; Load the Table

  MOVWF   TBLPTRH         ;   address

  MOVLW   LOW (TBL_ADDR)  ;

  MOVWF   TBLPTRL         ;

  TABLRD  0,0,DUMMY       ; Dummy read,

                          ;  Updates TABLATCH

  TLRD    1, INDF0        ; Read HI byte

                          ;   of TABLATCH

  TABLRD  0,1,INDF0       ; Read LO byte 

                          ;   of TABLATCH and

                          ;   Update TABLATCH

 

FIGURE 7-7:

TABLRD TIMING   

FIGURE 7-8:

TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)     

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

Instruction

fetched

Instruction

executed

ALE

OE

WR

TABLRD

INST (PC+1)

INST (PC+2)

INST (PC-1)

TABLRD cycle1

TABLRD cycle2

INST (PC+1)

Data read cycle

PC

PC+1

TBL

Data in

PC+2

'1'

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

Instruction

fetched

Instruction

executed

TABLRD1

TABLRD2

INST (PC+2)

INST (PC+3)

INST (PC+2)

ALE

OE

WR

INST (PC-1)

TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1 TABLRD2 cycle2

Data read cycle

Data read cycle

'1'

PC

PC+1

PC+2

PC+3

TBL1 Data in 1

TBL2

Data in 2

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 49

 

PIC17C4X

 

8.0

HARDWARE MULTIPLIER

 

All PIC17C4X devices except the PIC17C42, have an

8 x 8 hardware multiplier included in the ALU of the

device. By making the multiply a hardware operation, it

completes in a single instruction cycle. This is an

unsigned multiply that gives a 16-bit result. The result

is stored into the 16-bit PRODuct register

(PRODH:PRODL). The multiplier does not affect any

flags in the ALUSTA register.

Making the 8 x 8 multiplier execute in a single cycle

gives the following advantages:

• Higher computational throughput

• Reduces code size requirements for multiply 

algorithms

The performance increase allows the device to be used

in applications previously reserved for Digital Signal

Processors.

Table 8-1 shows a performance comparison between

the PIC17C42 and all other PIC17CXX devices, which

have the single cycle hardware multiply.

Example 8-1 shows the sequence to do an 8 x 8

unsigned multiply. Only one instruction is required

when one argument of the multiply is already loaded in

the WREG register.

Example 8-2 shows the sequence to do an 8 x 8 signed

multiply. To account for the sign bits of the arguments,

each argument’s most significant bit (MSb) is tested

and the appropriate subtractions are done.

 

EXAMPLE 8-1:

8 x 8 MULTIPLY ROUTINE

 

     MOVFP    ARG1, WREG

     MULWF    ARG2        ; ARG1 * ARG2 ->

                          ;   PRODH:PRODL

 

EXAMPLE 8-2:

8 x 8 SIGNED MULTIPLY 

ROUTINE

 

     MOVFP    ARG1, WREG

     MULWF    ARG2        ; ARG1 * ARG2 ->

                          ;   PRODH:PRODL

     BTFSC    ARG2, SB    ; Test Sign Bit

     SUBWF    PRODH, F    ; PRODH = PRODH

                          ;         - ARG1

     MOVFP    ARG2, WREG

     BTFSC    ARG1, SB    ; Test Sign Bit

     SUBWF    PRODH, F    ; PRODH = PRODH

                          ;         - ARG2

 

TABLE 8-1:

PERFORMANCE COMPARISON     

 

Routine

Device

Program Memory

(Words)

Cycles (Max)

Time

@ 25 MHz

@ 33 MHz

 

8 x 8 unsigned

PIC17C42

13

69

11.04 

 

µ

 

s

N/A

All other PIC17CXX devices

1

1

160 ns

121 ns

8 x 8 signed

PIC17C42

N/A

All other PIC17CXX devices

6

6

960 ns

727 ns

16 x 16 unsigned

PIC17C42

21

242

38.72 

 

µ

 

s

N/A

All other PIC17CXX devices

24

24

3.84 

 

µ

 

s

2.91 

 

µ

 

s

16 x 16 signed

PIC17C42

52

254

40.64 

 

µ

 

s

N/A

All other PIC17CXX devices

36

36

5.76 

 

µ

 

s

4.36 

 

µ

 

s

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 50

 

©

 

 1996 Microchip Technology Inc.

 

Example 8-3 shows the sequence to do a 16 x 16

unsigned multiply. Equation 8-1 shows the algorithm

that is used. The 32-bit result is stored in 4 registers

RES3:RES0.

 

EQUATION 8-1:

16 x 16 UNSIGNED 

MULTIPLICATION 

ALGORITHM

 

RES3:RES0

=

ARG1H:ARG1L * ARG2H:ARG2L

=

(ARG1H * ARG2H * 2

 

16

 

) +

(ARG1H * ARG2L * 2

 

8

 

)

+

(ARG1L * ARG2H * 2

 

8

 

)

+

(ARG1L * ARG2L)

 

EXAMPLE 8-3:

16 x 16 MULTIPLY ROUTINE

 

   MOVFP    ARG1L, WREG

   MULWF    ARG2L       ; ARG1L * ARG2L ->

                        ;   PRODH:PRODL

   MOVPF    PRODH, RES1 ;

   MOVPF    PRODL, RES0 ;

;

   MOVFP    ARG1H, WREG

   MULWF    ARG2H       ; ARG1H * ARG2H ->

                        ;   PRODH:PRODL

   MOVPF    PRODH, RES3 ;

   MOVPF    PRODL, RES2 ;

;

   MOVFP    ARG1L, WREG

   MULWF    ARG2H       ; ARG1L * ARG2H ->

                        ;   PRODH:PRODL

   MOVFP    PRODL, WREG ;

   ADDWF    RES1, F     ; Add cross

   MOVFP    PRODH, WREG ;    products

   ADDWFC   RES2, F     ;

   CLRF     WREG, F     ;

   ADDWFC   RES3, F     ;

;

   MOVFP    ARG1H, WREG ;

   MULWF    ARG2L       ; ARG1H * ARG2L ->

                        ;   PRODH:PRODL

   MOVFP    PRODL, WREG ;

   ADDWF    RES1, F     ; Add cross

   MOVFP    PRODH, WREG ;    products

   ADDWFC   RES2, F     ;

   CLRF     WREG, F     ;

   ADDWFC   RES3, F     ;

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 51

 

PIC17C4X

 

Example 8-4 shows the sequence to do an 16 x 16

signed multiply. Equation 8-2 shows the algorithm that

used. The 32-bit result is stored in four registers

RES3:RES0. To account for the sign bits of the argu-

ments, each argument pairs most significant bit (MSb)

is tested and the appropriate subtractions are done.

 

EQUATION 8-2:

16 x 16 SIGNED 

MULTIPLICATION 

ALGORITHM

 

RES3:RES0

= ARG1H:ARG1L * ARG2H:ARG2L

= (ARG1H * ARG2H * 2

 

16

 

)

+

(ARG1H * ARG2L * 2

 

8

 

)

+

(ARG1L * ARG2H * 2

 

8

 

)

+

(ARG1L * ARG2L)

+

(-1 * ARG2H<7> * ARG1H:ARG1L * 2

 

16

 

) +

(-1 * ARG1H<7> * ARG2H:ARG2L * 2

 

16

 

)

 

EXAMPLE 8-4:

16 x 16 SIGNED MULTIPLY 

ROUTINE

 

   MOVFP    ARG1L, WREG

   MULWF    ARG2L       ; ARG1L * ARG2L ->

                        ;   PRODH:PRODL

   MOVPF    PRODH, RES1 ;

   MOVPF    PRODL, RES0 ;

;

   MOVFP    ARG1H, WREG

   MULWF    ARG2H       ; ARG1H * ARG2H ->

                        ;   PRODH:PRODL

   MOVPF    PRODH, RES3 ;

   MOVPF    PRODL, RES2 ;

;

   MOVFP    ARG1L, WREG

   MULWF    ARG2H       ; ARG1L * ARG2H ->

                        ;   PRODH:PRODL

   MOVFP    PRODL, WREG ;

   ADDWF    RES1, F     ; Add cross

   MOVFP    PRODH, WREG ;    products

   ADDWFC   RES2, F     ;

   CLRF     WREG, F     ;

   ADDWFC   RES3, F     ;

;

   MOVFP    ARG1H, WREG ;

   MULWF    ARG2L       ; ARG1H * ARG2L ->

                        ;   PRODH:PRODL

   MOVFP    PRODL, WREG ;

   ADDWF    RES1, F     ; Add cross

   MOVFP    PRODH, WREG ;    products

   ADDWFC   RES2, F     ;

   CLRF     WREG, F     ;

   ADDWFC   RES3, F     ;

;

   BTFSS    ARG2H, 7    ; ARG2H:ARG2L neg?

   GOTO     SIGN_ARG1   ; no, check ARG1

   MOVFP    ARG1L, WREG ;

   SUBWF    RES2        ;

   MOVFP    ARG1H, WREG ;

   SUBWFB   RES3

;

SIGN_ARG1

   BTFSS    ARG1H, 7    ; ARG1H:ARG1L neg?

   GOTO     CONT_CODE   ; no, done

   MOVFP    ARG2L, WREG ;

   SUBWF    RES2        ;

   MOVFP    ARG2H, WREG ;

   SUBWFB   RES3

;

CONT_CODE

     :

background image

 

PIC17C4X

 

DS30412C-page 52

 

©

 

 1996 Microchip Technology Inc.

 

NOTES:

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 53

 

PIC17C4X

 

9.0

I/O PORTS

 

The PIC17C4X devices have five I/O ports, PORTA

through PORTE. PORTB through PORTE have a corre-

sponding Data Direction Register (DDR), which is used

to configure the port pins as inputs or outputs. These

five ports are made up of 33 I/O pins. Some of these

ports pins are multiplexed with alternate functions. 

PORTC, PORTD, and PORTE are multiplexed with the

system bus. These pins are configured as the system

bus when the device’s configuration bits are selected to

Microprocessor or Extended Microcontroller modes. In

the two other microcontroller modes, these pins are

general purpose I/O.

PORTA and PORTB are multiplexed with the peripheral

features of the device. These peripheral features are:

• Timer modules

• Capture module

• PWM module

• USART/SCI module

• External Interrupt pin

When some of these peripheral modules are turned on,

the port pin will automatically configure to the alternate

function. The modules that do this are:

• PWM module

• USART/SCI module

When a pin is automatically configured as an output by

a peripheral module, the pins data direction (DDR) bit

is unknown. After disabling the peripheral module, the

user should re-initialize the DDR bit to the desired con-

figuration.

The other peripheral modules (which require an input)

must have their data direction bit configured appropri-

ately.     

 

Note:

 

A pin that is a peripheral input, can be con-

figured as an output (DDRx<y> is cleared).

The peripheral events will be determined

by the action output on the port pin.

 

9.1

PORTA Register

 

PORTA is a 6-bit wide latch. PORTA does not have a

corresponding Data Direction Register (DDR). 

Reading PORTA reads the status of the pins.

The RA1 pin is multiplexed with TMR0 clock input, and

RA4 and RA5 are multiplexed with the USART func-

tions. The control of RA4 and RA5 as outputs is auto-

matically configured by the USART module.

9.1.1

USING RA2, RA3 AS OUTPUTS

The RA2 and RA3 pins are open drain outputs. To use

the RA2 or the RA3 pin(s) as output(s), simply write to

the PORTA register the desired value. A '0' will cause

the pin to drive low, while a '1' will cause the pin to float

(hi-impedance). An external pull-up resistor should be

used to pull the pin high. Writes to PORTA will not affect

the other pins.    

 

FIGURE 9-1:

RA0 AND RA1 BLOCK 

DIAGRAM   

 

Note:

 

When using the RA2 or RA3 pin(s) as out-

put(s), read-modify-write instructions (such

as 

 

BCF

 

 

BSF

 

 

BTG

 

) on PORTA are not rec-

ommended.

Such operations read the port pins, do the

desired operation, and then write this value

to the data latch. This may inadvertently

cause the RA2 or RA3 pins to switch from

input to output (or vice-versa). 

It is recommended to use a shadow regis-

ter for PORTA. Do the bit operations on this

shadow register and then move it to

PORTA.

Note: I/O pins have protection diodes to V

DD

 and V

SS

.

DATA BUS

RD_PORTA

(Q2)

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 54

 

©

 

 1996 Microchip Technology Inc.

 

FIGURE 9-2:

RA2 AND RA3 BLOCK 

DIAGRAM   

Note: I/O pins have protection diodes to V

SS

.

Data Bus

WR_PORTA

(Q4)

Q

D

Q

CK

RD_PORTA

(Q2)

 

FIGURE 9-3:

RA4 AND RA5 BLOCK 

DIAGRAM   

Note: I/O pins have protection diodes to V

DD

 and V

SS

.

Data Bus

RD_PORTA

(Q2)

Serial port output signals

Serial port input signal

OE = SPEN,SYNC,TXEN, CREN, SREN for RA4

OE = SPEN (SYNC+SYNC,CSRC) for RA5

 

TABLE 9-1:

PORTA FUNCTIONS

TABLE 9-2:

REGISTERS/BITS ASSOCIATED WITH PORTA  

 

   

 

 

 

Name

Bit0

Buffer Type

Function

 

RA0/INT

bit0

ST

Input or external interrupt input.

RA1/T0CKI

bit1

ST

Input or clock input to the TMR0 timer/counter, and/or an external interrupt input.

RA2

bit2

ST

Input/Output. Output is open drain type.

RA3

bit3

ST

Input/Output. Output is open drain type.

RA4/RX/DT

bit4

ST

Input or USART Asynchronous Receive or USART Synchronous Data.

RA5/TX/CK

bit5

ST

Input or USART Asynchronous Transmit or USART Synchronous Clock.

RBPU

bit7

Control bit for PORTB weak pull-ups.

Legend: ST = Schmitt Trigger input.

 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on 

Power-on 

Reset

Value on all 

other resets 

(Note1)

 

10h, Bank 0

PORTA

RBPU

RA5

RA4

RA3

RA2

RA1/T0CKI

RA0/INT

 

0-xx xxxx

0-uu uuuu

 

05h, Unbanked

T0STA

INTEDG

T0SE

T0CS

PS3

PS2

PS1

PS0

 

0000 000-

0000 000-

 

13h, Bank 0

RCSTA

SPEN

RC9

SREN

CREN

FERR

OERR

RC9D

 

0000 -00x

0000 -00u

 

15h, Bank 0

TXSTA

CSRC

TX9

TXEN

SYNC

TRMT

TX9D

 

0000 --1x

0000 --1u

 

Legend:

 

x

 

 = unknown, 

 

u

 

 = unchanged, 

 

-

 

 = unimplemented reads as '0'. Shaded cells are not used by PORTA.

Note 1:

Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 55

 

PIC17C4X

 

9.2

PORTB and DDRB Registers

 

PORTB is an 8-bit wide bi-directional port. The corre-

sponding data direction register is DDRB. A '1' in DDRB

configures the corresponding port pin as an input. A '0'

in the DDRB register configures the corresponding port

pin as an output. Reading PORTB reads the status of

the pins, whereas writing to it will write to the port latch.

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

done by clearing the RBPU (PORTA<7>) bit. The weak

pull-up is automatically turned off when the port pin is

configured as an output. The pull-ups are enabled on

any reset.

PORTB also has an interrupt on change feature. Only

pins configured as inputs can cause this interrupt to

occur (i.e. any RB7:RB0 pin configured as an output is

excluded from the interrupt on change comparison).

The input pins (of RB7:RB0) are compared with the

value in the PORTB data latch. The “mismatch” outputs

of RB7:RB0 are OR’ed together to generate the

PORTB Interrupt Flag RBIF (PIR<7>). 

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the inter-

rupt by:

a)

Read-Write PORTB (such as; 

 

MOVPF PORTB,

PORTB

 

). This will end mismatch condition. 

b)

Then, clear the RBIF bit.

A mismatch condition will continue to set the RBIF bit.

Reading then writing PORTB will end the mismatch

condition, and allow the RBIF bit to be cleared.

This interrupt on mismatch feature, together with soft-

ware configurable pull-ups on this port, allows easy

interface to a key pad and make it possible for wake-up

on key-depression. For an example, refer to AN552 in

the 

 

Embedded Control Handbook

 

The interrupt on change feature is recommended for

wake-up on operations where PORTB is only used for

the interrupt on change feature and key depression

operation.

 

FIGURE 9-4:

BLOCK DIAGRAM OF RB<7:4> AND RB<1:0> PORT PINS      

Note: I/O pins have protection diodes to V

DD

 and V

SS

.

Data Bus

Q

D

CK

Q

D

CK

Weak

Pull-Up

Port

Input Latch

Port

Data

OE

WR_PORTB (Q4)

WR_DDRB (Q4)

RD_PORTB (Q2)

RD_DDRB (Q2)

RBIF

RBPU

Match Signal

from other

port pins

(PORTA<7>)

Peripheral Data in

background image

 

PIC17C4X

 

DS30412C-page 56

 

©

 

 1996 Microchip Technology Inc.

 

FIGURE 9-5:

BLOCK DIAGRAM OF RB3 AND RB2 PORT PINS       

Note: I/O pins have protection diodes to V

DD

 and Vss.

Data Bus

Q

D

CK

Q

D

CK

R

Weak

Pull-Up

Port

Input Latch

Port

Data

OE

PWM_select

PWM_output

WR_PORTB (Q4)

WR_DDRB (Q4)

RD_PORTB (Q2)

RD_DDRB (Q2)

RBIF

RBPU

Match Signal

from other

port pins

(PORTA<7>)

Peripheral Data in

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 57

 

PIC17C4X

 

Example 9-1 shows the instruction sequence to initial-

ize PORTB. The Bank Select Register (BSR) must be

selected to Bank 0 for the port to be initialized.

 

EXAMPLE 9-1:

INITIALIZING PORTB     

 

MOVLB 0

; Select Bank 0

CLRF

PORTB

; Initialize PORTB by clearing 

;  output data latches

MOVLW 0xCF

; Value used to initialize

;  data direction

MOVWF DDRB

;  Set RB<3:0> as inputs

;   RB<5:4> as outputs

;   RB<7:6> as inputs

 

TABLE 9-3:

PORTB FUNCTIONS   

TABLE 9-4:

REGISTERS/BITS ASSOCIATED WITH PORTB  

 

   

 

 

 

Name

Bit

Buffer Type

Function

 

RB0/CAP1

bit0

ST

Input/Output or the RB0/CAP1 input pin. Software programmable weak pull-

up and interrupt on change features.

RB1/CAP2

bit1

ST

Input/Output or the RB1/CAP2 input pin. Software programmable weak pull-

up and interrupt on change features.

RB2/PWM1

bit2

ST

Input/Output or the RB2/PWM1 output pin. Software programmable weak 

pull-up and interrupt on change features.

RB3/PWM2

bit3

ST

Input/Output or the RB3/PWM2 output pin. Software programmable weak 

pull-up and interrupt on change features.

RB4/TCLK12

bit4

ST

Input/Output or the external clock input to Timer1 and Timer2. Software pro-

grammable weak pull-up and interrupt on change features.

RB5/TCLK3

bit5

ST

Input/Output or the external clock input to Timer3. Software programmable 

weak pull-up and interrupt on change features.

RB6

bit6

ST

Input/Output pin. Software programmable weak pull-up and interrupt on 

change features.

RB7

bit7

ST

Input/Output pin. Software programmable weak pull-up and interrupt on 

change features.

Legend: ST = Schmitt Trigger input.

 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on 

Power-on 

Reset

Value on all 

other 

resets 

(Note1)

 

12h, Bank 0

PORTB

PORTB data latch

 

xxxx xxxx

uuuu uuuu

 

11h, Bank 0

DDRB

Data direction register for PORTB

 

1111 1111

1111 1111

 

10h, Bank 0

PORTA

RBPU

RA5

RA4

RA3

RA2

RA1/T0CKI

RA0/INT

 

0-xx xxxx

0-uu uuuu

 

06h, Unbanked

CPUSTA

STKAV

GLINTD

TO

PD

 

--11 11--

--11 qq--

 

07h, Unbanked

INTSTA

PEIF

T0CKIF

T0IF

INTF

PEIE

T0CKIE

T0IE

INTE

 

0000 0000

0000 0000

 

16h, Bank 1

PIR

RBIF

TMR3IF

TMR2IF

TMR1IF

CA2IF

CA1IF

TXIF

RCIF

 

0000 0010

0000 0010

 

17h, Bank 1

PIE

RBIE

TMR3IE

TMR2IE

TMR1IE

CA2IE

CA1IE

TXIE

RCIE

 

0000 0000

0000 0000

 

16h, Bank 3

TCON1

CA2ED1

CA2ED0

CA1ED1

CA1ED0

T16

TMR3CS

TMR2CS

TMR1CS

 

0000 0000

0000 0000

 

17h, Bank 3

TCON2

CA2OVF CA1OVF

PWM2ON

PWM1ON

CA1/PR3

TMR3ON

TMR2ON

TMR1ON

 

0000 0000

0000 0000

 

Legend:

 

x

 

 = unknown, 

 

u

 

 = unchanged, 

 

 

= unimplemented read as '0', q = Value depends on condition. 

Shaded cells are not used by PORTB.

Note 1:

Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

background image

 

PIC17C4X

 

DS30412C-page 58

 

©

 

 1996 Microchip Technology Inc.

 

9.3

PORTC and DDRC Registers

 

PORTC is an 8-bit bi-directional port. The correspond-

ing data direction register is DDRC. A '1' in DDRC con-

figures the corresponding port pin as an input. A '0' in

the DDRC register configures the corresponding port

pin as an output. Reading PORTC reads the status of

the pins, whereas writing to it will write to the port latch.

PORTC is multiplexed with the system bus. When

operating as the system bus, PORTC is the low order

byte of the address/data bus (AD7:AD0). The timing for

the system bus is shown in the Electrical Characteris-

tics section.      

 

Note:

 

This port is configured as the system bus

when the device’s configuration bits are

selected to Microprocessor or Extended

Microcontroller modes. In the two other

microcontroller modes, this port is a gen-

eral purpose I/O.

Example 9-2 shows the instruction sequence to initial-

ize PORTC. The Bank Select Register (BSR) must be

selected to Bank 1 for the port to be initialized.

 

EXAMPLE 9-2:

INITIALIZING PORTC   

 

MOVLB

1

;  Select Bank 1

CLRF

PORTC

;  Initialize PORTC data

;

latches before setting

;

the data direction

;

register

MOVLW

0xCF

;  Value used to initialize

;   data direction

MOVWF

DDRC

;  Set RC<3:0> as inputs

;

RC<5:4> as outputs

 

;

 

RC<7:6> as inputs

 

FIGURE 9-6:

BLOCK DIAGRAM OF RC<7:0> PORT PINS   

Note: I/O pins have protection diodes to V

DD

 and Vss.

Q

D

CK

TTL

0

1

Q

D

CK

R

S

Input

Buffer

Port

Data

to D_Bus 

 IR

INSTRUCTION READ

Data Bus

RD_PORTC

WR_PORTC

RD_DDRC

WR_DDRC

EX_EN

DATA/ADDR_OUT

DRV_SYS

SYS BUS

Control

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 59

 

PIC17C4X

 

TABLE 9-5:

PORTC FUNCTIONS   

TABLE 9-6:

REGISTERS/BITS ASSOCIATED WITH PORTC  

 

   

 

 

 

Name

Bit

Buffer Type

Function

 

RC0/AD0

bit0

TTL

Input/Output or system bus address/data pin.

RC1/AD1

bit1

TTL

Input/Output or system bus address/data pin.

RC2/AD2

bit2

TTL

Input/Output or system bus address/data pin.

RC3/AD3

bit3

TTL

Input/Output or system bus address/data pin.

RC4/AD4

bit4

TTL

Input/Output or system bus address/data pin.

RC5/AD5

bit5

TTL

Input/Output or system bus address/data pin.

RC6/AD6

bit6

TTL

Input/Output or system bus address/data pin.

RC7/AD7

bit7

TTL

Input/Output or system bus address/data pin.

Legend:  TTL = TTL input.

 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on 

Power-on 

Reset

Value on all 

other resets 

(Note1)

 

11h, Bank 1

PORTC

RC7/

AD7

RC6/

AD6

RC5/

AD5

RC4/

AD4

RC3/

AD3

RC2/

AD2

RC1/

AD1

RC0/

AD0

 

xxxx xxxx

uuuu uuuu

 

10h, Bank 1

DDRC

Data direction register for PORTC

 

1111 1111

1111 1111

 

Legend:

 

x

 

 = unknown, 

 

u

 

 = unchanged.

Note 1:

Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

background image

 

PIC17C4X

 

DS30412C-page 60

 

©

 

 1996 Microchip Technology Inc.

 

9.4

PORTD and DDRD Registers

 

PORTD is an 8-bit bi-directional port. The correspond-

ing data direction register is DDRD. A '1' in DDRD con-

figures the corresponding port pin as an input. A '0' in

the DDRC register configures the corresponding port

pin as an output. Reading PORTD reads the status of

the pins, whereas writing to it will write to the port latch.

PORTD is multiplexed with the system bus. When

operating as the system bus, PORTD is the high order

byte of the address/data bus (AD15:AD8). The timing

for the system bus is shown in the Electrical Character-

istics section.      

 

Note:

 

This port is configured as the system bus

when the device’s configuration bits are

selected to Microprocessor or Extended

Microcontroller modes. In the two other

microcontroller modes, this port is a gen-

eral purpose I/O.

Example 9-3 shows the instruction sequence to initial-

ize PORTD. The Bank Select Register (BSR) must be

selected to Bank 1 for the port to be initialized.

 

EXAMPLE 9-3:

INITIALIZING PORTD   

 

MOVLB

1

;  Select Bank 1

CLRF

PORTD

;  Initialize PORTD data

;

latches before setting

;

the data direction

;

register

MOVLW

0xCF

;  Value used to initialize

;   data direction

MOVWF

DDRD

;  Set RD<3:0> as inputs

;

RD<5:4> as outputs

 

;

 

RD<7:6> as inputs

 

FIGURE 9-7:

PORTD BLOCK DIAGRAM (IN I/O PORT MODE)  

Note: I/O pins have protection diodes to V

DD

 and Vss.

Q

D

CK

TTL

0

1

Q

D

CK

R

S

Input

Buffer

Port

Data

to D_Bus 

 IR

INSTRUCTION READ

Data Bus

RD_PORTD

WR_PORTD

RD_DDRD

WR_DDRD

EX_EN

DATA/ADDR_OUT

DRV_SYS

SYS BUS

Control

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 61

 

PIC17C4X

 

TABLE 9-7:

PORTD FUNCTIONS   

TABLE 9-8:

REGISTERS/BITS ASSOCIATED WITH PORTD  

 

   

 

 

 

Name

Bit

Buffer Type

Function

 

RD0/AD8

bit0

TTL

Input/Output or system bus address/data pin.

RD1/AD9

bit1

TTL

Input/Output or system bus address/data pin.

RD2/AD10

bit2

TTL

Input/Output or system bus address/data pin.

RD3/AD11

bit3

TTL

Input/Output or system bus address/data pin.

RD4/AD12

bit4

TTL

Input/Output or system bus address/data pin.

RD5/AD13

bit5

TTL

Input/Output or system bus address/data pin.

RD6/AD14

bit6

TTL

Input/Output or system bus address/data pin.

RD7/AD15

bit7

TTL

Input/Output or system bus address/data pin.

Legend:  TTL = TTL input.

 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on 

Power-on 

Reset

Value on all 

other resets 

(Note1)

 

13h, Bank 1

PORTD

RD7/

AD15

RD6/

AD14

RD5/

AD13

RD4/

AD12

RD3/

AD11

RD2/

AD10

RD1/

AD9

RD0/

AD8

 

xxxx xxxx

uuuu uuuu

 

12h, Bank 1

DDRD

Data direction register for PORTD

 

1111 1111

1111 1111

 

Legend:

 

x

 

 = unknown, 

 

u

 

 = unchanged.

Note 1:

Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

background image

 

PIC17C4X

 

DS30412C-page 62

 

©

 

 1996 Microchip Technology Inc.

 

9.4.1

PORTE AND DDRE REGISTER

PORTE is a 3-bit bi-directional port. The corresponding

data direction register is DDRE. A '1' in DDRE config-

ures the corresponding port pin as an input. A '0' in the

DDRE register configures the corresponding port pin

as an output. Reading PORTE reads the status of the

pins, whereas writing to it will write to the port latch.

PORTE is multiplexed with the system bus. When

operating as the system bus, PORTE contains the con-

trol signals for the address/data bus (AD15:AD0).

These control signals are Address Latch Enable (ALE),

Output Enable (OE), and Write (WR). The control sig-

nals OE and WR are active low signals. The timing for

the system bus is shown in the Electrical Characteris-

tics section.        

 

Note:

 

This port is configured as the system bus

when the device’s configuration bits are

selected to Microprocessor or Extended

Microcontroller modes. In the two other

microcontroller modes, this port is a gen-

eral purpose I/O.

Example 9-4 shows the instruction sequence to initial-

ize PORTE. The Bank Select Register (BSR) must be

selected to Bank 1 for the port to be initialized.

 

EXAMPLE 9-4:

INITIALIZING PORTE    

 

MOVLB

1

;  Select Bank 1

CLRF

PORTE

;  Initialize PORTE data

;

latches before setting

;

the data direction

;

register

MOVLW

0x03

;  Value used to initialize

;   data direction

MOVWF

DDRE

;  Set RE<1:0> as inputs

;

RE<2> as outputs

 

;

 

RE<7:3> are always

 

;

 

read as '0'

FIGURE 9-8:

PORTE BLOCK DIAGRAM (IN I/O PORT MODE)     

Note: I/O pins have protection diodes to V

DD

 and Vss.

Q

D

CK

TTL

0

1

Q

D

CK

R

S

Input

Buffer

Port

Data

Data Bus

RD_PORTE

WR_PORTE

RD_DDRE

WR_DDRE

EX_EN

CNTL

DRV_SYS

SYS BUS

Control

background image

©

 1996 Microchip Technology Inc.

DS30412C-page 63

PIC17C4X

TABLE 9-9:

PORTE FUNCTIONS   

TABLE 9-10:

REGISTERS/BITS ASSOCIATED WITH PORTE  

   

 

Name

Bit

Buffer Type

Function

RE0/ALE

bit0

TTL

Input/Output or system bus Address Latch Enable (ALE) control pin.

RE1/OE

bit1

TTL

Input/Output or system bus Output Enable (OE) control pin.

RE2/WR 

bit2

TTL

Input/Output or system bus Write (WR) control pin.

Legend:  TTL = TTL input.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on 

Power-on 

Reset

Value on all 

other resets 

(Note1)

15h, Bank 1

PORTE

RE2/WR RE1/OE RE0/ALE

---- -xxx

---- -uuu

14h, Bank 1

DDRE

Data direction register for PORTE

---- -111

---- -111

Legend:

x

 = unknown, 

u

 = unchanged, 

= unimplemented read as '0'. Shaded cells are not used by PORTE.

Note 1:

Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

background image

PIC17C4X

DS30412C-page 64

©

 1996 Microchip Technology Inc.

9.5

I/O Programming Considerations

9.5.1

BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a

read followed by a write operation. For example, the

BCF

 and 

BSF

 instructions read the register into the

CPU, execute the bit operation, and write the result

back to the register. Caution must be used when these

instructions are applied to a port with both inputs and

outputs defined. For example, a 

BSF

 operation on bit5

of PORTB will cause all eight bits of PORTB to be read

into the CPU. Then the 

BSF

 operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bi-directional I/O pin

(e.g. bit0) and it is defined as an input at this time, the

input signal present on the pin itself would be read into

the CPU and re-written to the data latch of this particu-

lar pin, overwriting the previous content. As long as the

pin stays in the input mode, no problem occurs. How-

ever, if bit0 is switched into output mode later on, the

content of the data latch may now be unknown.

Reading a port reads the values of the port pins. Writing

to the port register writes the value to the port latch.

When using read-modify-write instructions (

BCF, BSF

,

BTG

, etc.) on a port, the value of the port pins is read,

the desired operation is performed with this value, and

the value is then written to the port latch. 

Example 

9-5 shows the effect of two sequential

read-modify-write instructions on an I/O port.

 

EXAMPLE 9-5:

READ MODIFY WRITE 

INSTRUCTIONS ON AN

I/O PORT 

  

; Initial PORT settings: PORTB<7:4> Inputs

;                        PORTB<3:0> Outputs

; PORTB<7:6> have pull-ups and are

; not connected to other circuitry

;

;                       PORT latch  PORT pins

;                       ----------  ---------

;

   BCF   PORTB, 7       01pp pppp   11pp pppp

   BCF   PORTB, 6       10pp pppp   11pp pppp

;

   BCF   DDRB, 7        10pp pppp   11pp pppp

   BCF   DDRB, 6        10pp pppp   10pp pppp

;

; Note that the user may have expected the

; pin values to be 00pp pppp. The 2nd BCF

; caused RB7 to be latched as the pin value

; (High). 

   

9.5.2

SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle (Figure 9-

9). Therefore, care must be exercised if a write followed

by a read operation is carried out on the same I/O port.

The sequence of instructions should be such to allow

the pin voltage to stabilize (load dependent) before

executing the instruction that reads the values on that

I/O port. Otherwise, the previous state of that pin may

be read into the CPU rather than the “new” state. When

in doubt, it is better to separate these instructions with

NOP

 or another instruction not accessing this I/O port.

Note:

A pin actively outputting a Low or High

should not be driven from external devices

in order to change the level on this pin (i.e.

“wired-or”, “wired-and”). The resulting high

output currents may damage the device.

FIGURE 9-9:

SUCCESSIVE I/O OPERATION     

Note:

This example shows a write to PORTB

followed by a read from PORTB.

Note that:

data setup time = (0.25 T

CY

 - T

PD

)

where T

CY

 = instruction cycle.

Therefore, at higher clock 

frequencies, a write followed by a 

read may be problematic.

           T

PD

 = propagation delay

PC

PC + 1

PC + 2

PC + 3

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Instruction

fetched

RB7:RB0

MOVWF PORTB

write to

PORTB

NOP

Port pin

sampled here

NOP

MOVF PORTB,W

Instruction

executed

MOVWF PORTB

write to

PORTB

NOP

MOVF PORTB,W

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 65

 

PIC17C4X

 

10.0

OVERVIEW OF TIMER 

RESOURCES

 

The PIC17C4X has four timer modules. Each module

can generate an interrupt to indicate that an event has

occurred. These timers are called:

• Timer0 - 16-bit timer with programmable 8-bit 

prescaler

• Timer1 - 8-bit timer

• Timer2 - 8-bit timer

• Timer3 - 16-bit timer

For enhanced time-base functionality, two input Cap-

tures and two Pulse Width Modulation (PWM) outputs

are possible. The PWMs use the TMR1 and TMR2

resources and the input Captures use the TMR3

resource.

 

10.1

Timer0 Overview

 

The Timer0 module is a simple 16-bit overflow counter.

The clock source can be either the internal system

clock (Fosc/4) or an external clock. 

The Timer0 module also has a programmable pres-

caler option. The PS3:PS0 bits (T0STA<4:1>) deter-

mine the prescaler value. TMR0 can increment at the

following rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64,

1:128, 1:256.

When TImer0’s clock source is an external clock, the

Timer0 module can be selected to increment on either

the rising or falling edge. 

Synchronization of the external clock occurs after the

prescaler. When the prescaler is used, the external

clock frequency may be higher then the device’s fre-

quency. The maximum frequency is 50 MHz, given the

high and low time requirements of the clock.

 

10.2

Timer1 Overview

 

The TImer0 module is an 8-bit timer/counter with an 8-

bit period register (PR1). When the TMR1 value rolls

over from the period match value to 0h, the TMR1IF

flag is set, and an interrupt will be generated when

enabled. In counter mode, the clock comes from the

RB4/TCLK12 pin, which can also be selected to be the

clock for the Timer2 module.

TMR1 can be concatenated to TMR2 to form a 16-bit

timer. The TMR1 register is the LSB and TMR2 is the

MSB. When in the 16-bit timer mode, there is a corre-

sponding 16-bit period register (PR2:PR1). When the

TMR2:TMR1 value rolls over from the period match

value to 0h, the TMR1IF flag is set, and an interrupt

will be generated when enabled.

 

10.3

Timer2 Overview

 

The TMR2 module is an 8-bit timer/counter with an 8-

bit period register (PR2). When the TMR2 value rolls

over from the period match value to 0h, the TMR2IF

flag is set, and an interrupt will be generated when

enabled. In counter mode, the clock comes from the

RB4/TCLK12 pin, which can also be selected to be the

clock for the TMR1 module.

TMR1 can be concatenated to TMR2 to form a 16-bit

timer. The TMR2 register is the MSB and TMR1 is the

LSB. When in the 16-bit timer mode, there is a corre-

sponding 16-bit period register (PR2:PR1). When the

TMR2:TMR1 value rolls over from the period match

value to 0h, the TMR1IF flag is set, and an interrupt

will be generated when enabled.

 

10.4

Timer3 Overview

 

The TImer3 module is a 16-bit timer/counter with a 16-

bit period register. When the TMR3H:TMR3L value

rolls over to 0h, the TMR3IF bit is set and an interrupt

will be generated when enabled. In counter mode, the

clock comes from the RB5/TCLK3 pin.

When operating in the dual capture mode, the period

registers become the second 16-bit capture register.

 

10.5

Role of the Timer/Counters

 

The timer modules are general purpose, but have ded-

icated resources associated with them. TImer1 and

Timer2 are the time-bases for the two Pulse Width

Modulation (PWM) outputs, while Timer3 is the time-

base for the two input captures.

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 66

 

©

 

 1996 Microchip Technology Inc.

 

NOTES:

 

 

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 67

 

PIC17C4X

 

11.0

TIMER0

 

The Timer0 module consists of a 16-bit timer/counter,

TMR0. The high byte is TMR0H and the low byte is

TMR0L. A software programmable 8-bit prescaler

makes an effective 24-bit overflow timer. The clock

source is also software programmable as either the

internal instruction clock or the RA1/T0CKI pin. The

control bits for this module are in register T0STA

(Figure 11-1).

 

FIGURE 11-1: T0STA REGISTER

 

 (ADDRESS: 05h, UNBANKED)

 

  

 

 

 

   

 

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

U - 0

INTEDG

T0SE

T0CS

PS3

PS2

PS1

PS0

 

R = Readable bit

W = Writable bit

U = Unimplemented, 

       Read as '0'

-n = Value at POR reset

 

bit7

bit0

bit 7:

 

INTEDG

 

: RA0/INT Pin Interrupt Edge Select bit

This bit selects the edge upon which the interrupt is detected

1 = Rising edge of RA0/INT pin generates interrupt

0 = Falling edge of RA0/INT pin generates interrupt

bit 6:

 

T0SE

 

: Timer0 Clock Input Edge Select bit

This bit selects the edge upon which TMR0 will increment

When T0CS = 0  

1 = Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt

0 = Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt

When T0CS = 1   

Don’t care

bit 5:

 

T0CS

 

: Timer0 Clock Source Select bit

This bit selects the clock source for TMR0.

1 = Internal instruction clock cycle (T

 

CY

 

)

0 = T0CKI pin

bit 4-1:

 

PS3:PS0

 

: Timer0 Prescale Selection bits

These bits select the prescale value for TMR0.      

bit  0:

 

Unimplemented

 

: Read as '0'

PS3:PS0

Prescale Value

0000

0001

0010

0011

0100

0101

0110

0111

1xxx

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

1:256

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 68

 

©

 

 1996 Microchip Technology Inc.

 

11.1

Timer0 Operation

 

When the T0CS (T0STA<5>) bit is set, TMR0 incre-

ments on the internal clock. When T0CS is clear, TMR0

increments on the external clock (RA1/T0CKI pin). The

external clock edge can be configured in software.

When the T0SE (T0STA<6>) bit is set, the timer will

increment on the rising edge of the RA1/T0CKI pin.

When T0SE is clear, the timer will increment on the fall-

ing edge of the RA1/T0CKI pin. The prescaler can be

programmed to introduce a prescale of 1:1 to 1:256.

The timer increments from 0000h to FFFFh and rolls

over to 0000h. On overflow, the TMR0 Interrupt Flag bit

(T0IF) is set. The TMR0 interrupt can be masked by

clearing the corresponding TMR0 Interrupt Enable bit

(T0IE). The TMR0 Interrupt Flag bit (T0IF) is automati-

cally cleared when vectoring to the TMR0 interrupt vec-

tor.

 

11.2

Using Timer0 with External Clock

 

When the external clock input is used for Timer0, it is

synchronized with the internal phase clocks.

Figure 11-3 shows the synchronization of the external

clock. This synchronization is done after the prescaler.

The output of the prescaler (PSOUT) is sampled twice

in every instruction cycle to detect a rising or a falling

edge. The timing requirements for the external clock

are detailed in the electrical specification section for the

desired device.

11.2.1

DELAY FROM EXTERNAL CLOCK EDGE

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time TMR0 is actually

incremented. Figure 11-3 shows that this delay is

between 3T

 

OSC

 

 and 7T

 

OSC

 

. Thus, for example, mea-

suring the interval between two edges (e.g. period) will

be accurate within 

 

±

 

4T

 

OSC

 

 (

 

±

 

121 ns @ 33 MHz).

 

FIGURE 11-2: TIMER0 MODULE BLOCK DIAGRAM   

FIGURE 11-3: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)    

RA1/T0CKI

Synchronization

Prescaler

(8 stage

async ripple

counter)

T0SE

(T0STA<6>)

Fosc/4

T0CS

(T0STA<5>)

PS3:PS0

(T0STA<4:1>)

Q2

Q4

0

1

TMR0H<8> TMR0L<8>

Interrupt on overflow

sets T0IF

(INTSTA<5>)

4

PSOUT

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Prescaler

output

(PSOUT)

Sampled

Prescaler

output

Increment

TMR0

TMR0

T0

T0 + 1

T0 + 2

(note 3)

(note 2)

Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.

 2: 

 = PSOUT is sampled here.

3: The PSOUT high time is too short and is missed by the sampling circuit.

(note 1)

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 69

 

PIC17C4X

 

11.3

Read/Write Consideration for TMR0

 

Although TMR0 is a 16-bit timer/counter, only 8-bits at

a time can be read or written during a single instruction

cycle. Care must be taken during any read or write.

11.3.1

READING 16-BIT VALUE

The problem in reading the entire 16-bit value is that

after reading the low (or high) byte, its value may

change from FFh to 00h.

Example 11-1 shows a 16-bit read. To ensure a proper

read, interrupts must be disabled during this routine.

 

EXAMPLE 11-1: 16-BIT READ

 

MOVPF   TMR0L, TMPLO    ;read low tmr0

MOVPF   TMR0H, TMPHI    ;read high tmr0

MOVFP   TMPLO, WREG     ;tmplo 

 

−>

 

 wreg

CPFSLT  TMR0L           ;tmr0l < wreg?

RETURN                  ;no then return

MOVPF   TMR0L, TMPLO    ;read low tmr0

MOVPF   TMR0H, TMPHI    ;read high tmr0

RETURN                  ;return

 

11.3.2

WRITING A 16-BIT VALUE TO TMR0

Since writing to either TMR0L or TMR0H will effectively

inhibit increment of that half of the TMR0 in the next

cycle (following write), but not inhibit increment of the

other half, the user must write to TMR0L first and

TMR0H next in two consecutive instructions, as shown

in Example 11-2. The interrupt must be disabled. Any

write to either TMR0L or TMR0H clears the prescaler. 

 

EXAMPLE 11-2: 16-BIT WRITE

 

BSF   CPUSTA, GLINTD ; Disable interrupt

MOVFP RAM_L, TMR0L   ;

MOVFP RAM_H, TMR0H   ;

BCF   CPUSTA, GLINTD ; Done, enable interrupt

 

11.4

Prescaler Assignments

 

Timer0 has an 8-bit prescaler. The prescaler assign-

ment is fully under software control; i.e., it can be

changed “on the fly” during program execution. When

changing the prescaler assignment, clearing the pres-

caler is recommended before changing assignment.

The value of the prescaler is “unknown,” and assigning

a value that is less then the present value makes it dif-

ficult to take this unknown time into account.

 

FIGURE 11-4: TMR0 TIMING: WRITE HIGH OR LOW BYTE   

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

AD15:AD0

ALE

TMR0L

TMR0H

MOVFP W,TMR0L

Write to TMR0L

MOVFP TMR0L,W

Read TMR0L

(Value = NT0)

MOVFP TMR0L,W

Read TMR0L

(Value = NT0)

MOVFP TMR0L,W

Read TMR0L

(Value = NT0 +1)

T0

T0+1

New T0   (NT0)

New T0+1

PC

PC+1

PC+2

PC+3

PC+4

Fetch

Instruction

executed

background image

 

PIC17C4X

 

DS30412C-page 70

 

©

 

 1996 Microchip Technology Inc.

 

FIGURE 11-5: TMR0 READ/WRITE IN TIMER MODE   

TABLE 11-1:

REGISTERS/BITS ASSOCIATED WITH TIMER0   

 

   

 

 

 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on 

Power-on 

Reset

Value on all 

other resets 

(Note1)

 

05h, Unbanked

T0STA

INTEDG

T0SE

T0CS

PS3

PS2

PS1

PS0

 

0000 000-

0000 000-

 

06h, Unbanked

CPUSTA

STKAV

GLINTD

TO

PD

 

--11 11--

--11 qq--

 

07h, Unbanked

INTSTA

PEIF

T0CKIF

T0IF

INTF

PEIE

T0CKIE

T0IE

INTE

 

0000 0000

0000 0000

 

0Bh, Unbanked

TMR0L

TMR0 register; low byte 

 

xxxx xxxx

uuuu uuuu

 

0Ch, Unbanked

TMR0H

TMR0 register; high byte 

 

xxxx xxxx

uuuu uuuu

 

Legend:

 

x

 

 = unknown, 

 

u

 

 = unchanged, 

 

-

 

 = unimplemented read as a '0', 

 

q

 

 - value depends on condition, Shaded cells are not used by Timer0.

Note  1:

Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

Instruction

executed

MOVFP

DATAL,TMR0L

Write TMR0L

MOVFP

DATAH,TMR0H

Write TMR0H

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

AD15:AD0

ALE

WR_TRM0L

WR_TMR0H

RD_TMR0L

TMR0H

TMR0L

12

12

13

AB

FE

FF

56

57

58

In this example, old TMR0 value is 12FEh, new value of AB56h is written.

Instruction

fetched

MOVFP

DATAL,TMR0L

Write TMR0L

MOVFP

DATAH,TMR0H

Write TMR0H

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

Previously

Fetched

Instruction

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 71

 

PIC17C4X

 

12.0

TIMER1, TIMER2, TIMER3, 

PWMS AND CAPTURES

 

The PIC17C4X has a wealth of timers and time-based

functions to ease the implementation of control applica-

tions. These time-base functions include two PWM out-

puts and two Capture inputs. 

Timer1 and Timer2 are two 8-bit incrementing timers,

each with a period register (PR1 and PR2 respectively)

and separate overflow interrupt flags. Timer1 and

Timer2 can operate either as timers (increment on

internal Fosc/4 clock) or as counters (increment on fall-

ing edge of external clock on pin RB4/TCLK12). They

are also software configurable to operate as a single

16-bit timer. These timers are also used as the

time-base for the PWM (pulse width modulation) mod-

ule.

Timer3 is a 16-bit timer/counter consisting of the

TMR3H and TMR3L registers. This timer has four other

associated registers. Two registers are used as a 16-bit

period register or a 16-bit Capture1 register

(PR3H/CA1H:PR3L/CA1L). The other two registers are

strictly the Capture2 registers (CA2H:CA2L). Timer3 is

the time-base for the two 16-bit captures.

TMR3 can be software configured to increment from

the internal system clock or from an external signal on

the RB5/TCLK3 pin.

Figure 12-1 and Figure 12-2 are the control registers

for the operation of Timer1, Timer2, and Timer3, as well

as PWM1, PWM2, Capture1, and Capture2.

 

FIGURE 12-1: TCON1 REGISTER (ADDRESS: 16h, BANK 3)   

 

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

CA2ED1 CA2ED0 CA1ED1 CA1ED0

T16

TMR3CS TMR2CS TMR1CS

 

R = Readable bit

W = Writable bit

-n = Value at POR reset

 

bit7

bit0

bit 7-6:

 

CA2ED1:CA2ED0

 

:  Capture2 Mode Select bits

00 = Capture on every falling edge

01 = Capture on every rising edge

10 = Capture on every 4th rising edge

11 = Capture on every 16th rising edge

bit 5-4:

 

CA1ED1:CA1ED0

 

: Capture1 Mode Select bits

00 = Capture on every falling edge

01 = Capture on every rising edge

10 = Capture on every 4th rising edge

11 = Capture on every 16th rising edge

bit 3:

 

T16

 

: Timer1:Timer2 Mode Select bit

1 = Timer1 and Timer2 form a 16-bit timer

0 = Timer1 and Timer2 are two 8-bit timers

bit 2:

 

TMR3CS

 

: Timer3 Clock Source Select bit

1 = TMR3 increments off the falling edge of the RB5/TCLK3 pin

0 = TMR3 increments off the internal clock

bit 1:

 

TMR2CS

 

: Timer2 Clock Source Select bit

1 = TMR2 increments off the falling edge of the RB4/TCLK12 pin

0 = TMR2 increments off the internal clock

bit 0:

 

TMR1CS

 

: Timer1 Clock Source Select bit

1 = TMR1 increments off the falling edge of the RB4/TCLK12 pin

0 = TMR1 increments off the internal clock

 

This document was created with FrameMaker 4 0 4

background image

 

PIC17C4X

 

DS30412C-page 72

 

©

 

 1996 Microchip Technology Inc.

 

FIGURE 12-2: TCON2 REGISTER (ADDRESS: 17h, BANK 3)   

 

R - 0

R - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

R/W - 0

CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON

 

R = Readable bit

W = Writable bit

-n = Value at POR reset

 

bit7

bit0

bit 7:

 

CA2OVF

 

:  Capture2 Overflow Status bit

This bit indicates that the capture value had not been read from the capture register pair (CA2H:CA2L)

before the next capture event occurred. The capture register retains the oldest unread capture value (last

capture before overflow). Subsequent capture events will not update the capture register with the Timer3

value until the capture register has been read (both bytes).

1 = Overflow occurred on Capture2 register

0 = No overflow occurred on Capture2 register

bit 6:

 

CA1OVF

 

: Capture1 Overflow Status bit

This bit indicates that the capture value had not been read from the capture register pair

(PR3H/CA2H:PR3L/CA2L) before the next capture event occurred. The capture register retains the old-

est unread capture value (last capture before overflow). Subsequent capture events will not update the

capture register with the TMR3 value until the capture register has been read (both bytes).

1 = Overflow occurred on Capture1 register

0 = No overflow occurred on Capture1 register

bit 5:

 

PWM2ON

 

: PWM2 On bit

1 = PWM2 is enabled (The RB3/PWM2 pin ignores the state of the DDRB<3> bit)

0 = PWM2 is disabled (The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction)

bit 4:

 

PWM1ON

 

: PWM1 On bit

1 = PWM1 is enabled (The RB2/PWM1 pin ignores the state of the DDRB<2> bit)

0 = PWM1 is disabled (The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction)

bit 3:

 

CA1/PR3

 

: CA1/PR3 Register Mode Select bit

1 = Enables Capture1 (PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without 

a period register)

0 = Enables the Period register (PR3H/CA1H:PR3L/CA1L is the Period register for Timer3)

bit 2:

 

TMR3ON

 

: Timer3 On bit

1 = Starts Timer3

0 = Stops Timer3

bit 1:

 

TMR2ON

 

: Timer2 On bit

This bit controls the incrementing of the Timer2 register.  When Timer2:Timer1 form the 16-bit timer (T16

is set), TMR2ON must be set.  This allows the MSB of the timer to increment.

1 = Starts Timer2 (Must be enabled if the T16 bit (TCON1<3>) is set)

0 = Stops Timer2

bit 0:

 

TMR1ON

 

: Timer1 On bit

When T16 is set (in 16-bit Timer Mode)   

1 = Starts 16-bit Timer2:Timer1

0 = Stops 16-bit Timer2:Timer1

When T16 is clear (in 8-bit Timer Mode)   

1 = Starts 8-bit Timer1

0 = Stops 8-bit Timer1

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 73

 

PIC17C4X

 

12.1

Timer1 and Timer2

 

12.1.1

TIMER1, TIMER2 IN 8-BIT MODE

Both Timer1 and Timer2 will operate in 8-bit mode

when the T16 bit is clear. These two timers can be inde-

pendently configured to increment from the internal

instruction cycle clock or from an external clock source

on the RB4/TCLK12 pin. The timer clock source is con-

figured by the TMRxCS bit (x = 1 for Timer1 or = 2 for

Timer2). When TMRxCS is clear, the clock source is

internal and increments once every instruction cycle

(Fosc/4). When TMRxCS is set, the clock source is the

RB4/TCLK12 pin, and the timer will increment on every

falling edge of the RB4/TCLK12 pin.

The timer increments from 00h until it equals the Period

register (PRx). It then resets to 00h at the next incre-

ment cycle. The timer interrupt flag is set when the timer

is reset. TMR1 and TMR2 have individual interrupt flag

bits. The TMR1 interrupt flag bit is latched into TMR1IF,

and the TMR2 interrupt flag bit is latched into TMR2IF.

Each timer also has a corresponding interrupt enable

bit (TMRxIE). The timer interrupt can be enabled by set-

ting this bit and disabled by clearing this bit. For periph-

eral interrupts to be enabled, the Peripheral Interrupt

Enable bit must be enabled (PEIE is set) and global

interrupts must be enabled (GLINTD is cleared).

The timers can be turned on and off under software

control. When the Timerx On control bit (TMRxON) is

set, the timer increments from the clock source. When

TMRxON is cleared, the timer is turned off and cannot

cause the timer interrupt flag to be set.

12.1.1.1

EXTERNAL CLOCK INPUT FOR TIMER1 

OR TIMER2

When TMRxCS is set, the clock source is the

RB4/TCLK12 pin, and the timer will increment on every

falling edge on the RB4/TCLK12 pin. The TCLK12 input

is synchronized with internal phase clocks. This causes

a delay from the time a falling edge appears on TCLK12

to the time TMR1 or TMR2 is actually incremented. For

the external clock input timing requirements, see the

Electrical Specification section.

 

FIGURE 12-3: TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE   

Fosc/4

RB4/TCLK12

TMR1ON

(TCON2<0>)

TMR1CS

(TCON1<0>)

TMR1

PR1

Reset

Equal

Set TMR1IF

(PIR<4>)

0

1

Comparator<8>

Comparator x8

Fosc/4

TMR2ON

(TCON2<1>)

TMR2CS

(TCON1<1>)

TMR2

PR2

Reset

Equal

Set TMR2IF

(PIR<5>)

1

0

Comparator<8>

Comparator x8

background image

 

PIC17C4X

 

DS30412C-page 74

 

©

 

 1996 Microchip Technology Inc.

 

12.1.2

TIMER1 & TIMER2 IN 16-BIT MODE

To select 16-bit mode, the T16 bit must be set. In this

mode TMR1 and TMR2 are concatenated to form a

16-bit timer (TMR2:TMR1). The 16-bit timer incre-

ments until it matches the 16-bit period register

(PR2:PR1). On the following timer clock, the timer

value is reset to 0h, and the TMR1IF bit is set.

When selecting the clock source for the16-bit timer, the

TMR1CS bit controls the entire 16-bit timer and

TMR2CS is a “don’t care.” When TMR1CS is clear, the

timer increments once every instruction cycle (Fosc/4).

When TMR1CS is set, the timer increments on every

falling edge of the RB4/TCLK12 pin. For the 16-bit timer

to increment, both TMR1ON and TMR2ON bits must be

set (Table 12-1).

12.1.2.1

EXTERNAL CLOCK INPUT FOR 

TMR1:TMR2

When TMR1CS is set, the 16-bit TMR2:TMR1 incre-

ments on the falling edge of clock input TCLK12. The

input on the RB4/TCLK12 pin is sampled and synchro-

nized by the internal phase clocks twice every instruc-

tion cycle. This causes a delay from the time a falling

edge appears on RB4/TCLK12 to the time

TMR2:TMR1 is actually incremented. For the external

clock input timing requirements, see the Electrical

Specification section.

 

TABLE 12-1:

TURNING ON 16-BIT TIMER   

 

TMR2ON

TMR1ON

Result

 

1

1

 

16-bit timer 

(TMR2:TMR1) ON

 

0

1

 

Only TMR1 increments

 

x

0

 

16-bit timer OFF

 

FIGURE 12-4: TMR1 AND TMR2 IN 16-BIT TIMER/COUNTER MODE   

TABLE 12-2:

SUMMARY OF TIMER1 AND TIMER2 REGISTERS    

 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on 

Power-on 

Reset

Value on all 

other resets 

(Note1)

 

16h, Bank 3

TCON1

CA2ED1

CA2ED0

CA1ED1

CA1ED0

T16

TMR3CS TMR2CS TMR1CS

 

0000 0000

0000 0000

 

17h, Bank 3

TCON2

CA2OVF

CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON

 

0000 0000

0000 0000

 

10h, Bank 2

TMR1

Timer1 register

 

xxxx xxxx

uuuu uuuu

 

11h, Bank 2

TMR2

Timer2 register

 

xxxx xxxx

uuuu uuuu

 

16h, Bank 1

PIR

RBIF

TMR3IF

TMR2IF

TMR1IF

CA2IF

CA1IF

TXIF

RCIF

 

0000 0010

0000 0010

 

17h, Bank 1

PIE

RBIE

TMR3IE

TMR2IE

TMR1IE

CA2IE

CA1IE

TXIE

RCIE

 

0000 0000

0000 0000

 

07h, Unbanked

INTSTA

PEIF

T0CKIF

T0IF

INTF

PEIE

T0CKIE

T0IE

INTE

 

0000 0000

0000 0000

 

06h, Unbanked

CPUSTA

STKAV

GLINTD

TO

PD

 

--11 11--

--11 qq--

 

14h, Bank 2

PR1

Timer1 period register

 

xxxx xxxx

uuuu uuuu

 

15h, Bank 2

PR2

Timer2 period register

 

xxxx xxxx

uuuu uuuu

 

10h, Bank 3

PW1DCL

DC1

DC0

 

xx-- ----

uu-- ----

 

11h, Bank 3

PW2DCL

DC1

DC0

TM2PW2

 

xx0- ----

uu0- ----

 

12h, Bank 3

PW1DCH

DC9

DC8

DC7

DC6

DC5

DC4

DC3

DC2

 

xxxx xxxx

uuuu uuuu

 

13h, Bank 3

PW2DCH

DC9

DC8

DC7

DC6

DC5

DC4

DC3

DC2

 

xxxx xxxx

uuuu uuuu

 

Legend:

 

x

 

 = unknown, 

 

u

 

 = unchanged, 

 

-

 

 = unimplemented read as a '0', q - value depends on condition,

shaded cells are not used by Timer1 or Timer2.

Note  1:

Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.

RB4/TCLK12

Fosc/4

TMR1ON

(TCON2<0>)

TMR1CS

(TCON1<0>)

TMR1 x 8

PR1 x 8

Reset

Equal

Set Interrupt TMR1IF

(PIR<4>)

1

0

Comparator<8>

Comparator x16

TMR2 x 8

PR2 x 8

background image

 

©

 

 1996 Microchip Technology Inc.

DS30412C-page 75

 

PIC17C4X

 

12.1.3

USING PULSE WIDTH MODULATION 

(PWM) OUTPUTS WITH TMR1 AND TMR2

Two high speed pulse width modulation (PWM) outputs

are provided. The PWM1 output uses Timer1 as its

time-base, while PWM2 may be software configured to

use either Timer1 or Timer2 as the time-base. The

PWM outputs are on the RB2/PWM1 and RB3/PWM2

pins.

Each PWM output has a maximum resolution of

10-bits. At 10-bit resolution, the PWM output frequency

is 24.4 kHz (@ 25 MHz clock) and at 8-bit resolution the

PWM output frequency is 97.7 kHz. The duty cycle of

the output can vary from 0% to 100%.

Figure 12-5 shows a simplified block diagram of the

PWM module. The duty cycle register is double buff-

ered for glitch free operation. Figure 12-6 shows how a

glitch could occur if the duty cycle registers were not

double buffered.

The user needs to set the PWM1ON bit (TCON2<4>)

to enable the PWM1 output. When the PWM1ON bit is

set, the RB2/PWM1 pin is configured as PWM1 output

and forced as an output irrespective of the data direc-

tion bit (DDRB<2>). When the PWM1ON bit is clear,

the pin behaves as a port pin and its direction is con-

trolled by its data direction bit (DDRB<2>). Similarly,

the PWM2ON (TCON2<5>) bit controls the configura-

tion of the RB3/PWM2 pin.

 

FIGURE 12-5: SIMPLIFIED PWM BLOCK 

DIAGRAM   

PWxDCH

Duty Cycle registers

PWxDCL<7:6>

Clear Timer,

PWMx pin and 

Latch D.C.

(Slave)

Comparator

TMR2

Comparator

PRy

(Note 1)

R

S

Q

PWMxON

RCy/PWMx

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

Read

Write

 

FIGURE 12-6: PWM OUTPUT   

0

10

20

30

40

0

PWM

output

Timer

interrupt

Write new

PWM value

Timer interrupt

new PWM value

transferred to slave

Note     The dotted line shows PWM output if duty cycle registers were not double buffered.

If the new duty cycle is written after the timer has passed that value, then the PWM does

not reset at all during the current cycle causing a “glitch”.

    In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10.

background image

 

PIC17C4X

 

DS30412C-page 76

 

©

 

 1996 Microchip Technology Inc.

 

12.1.3.1

PWM PERIODS

The period of the PWM1 output is determined by

Timer1 and its period register (PR1). The period of the

PWM2 output can be software configured to use either

Timer1 or Timer2 as the time-base. When TM2PW2 bit

(PW2DCL<5>) is clear, the time-base is determined by

TMR1 and PR1. When TM2PW2 is set, the time-base

is determined by Timer2 and PR2.

Running two different PWM outputs on two different

timers allows different PWM periods. Running both

PWMs from Timer1 allows the best use of resources by

freeing Timer2 to operate as an 8-bit timer. Timer1 and

Timer2 can not be used as a 16-bit timer if either PWM

is being used.

The PWM periods can be calculated as follows:

period of PWM1 =[(PR1) + 1] x 4T

 

OSC

 

period of PWM2 =[(PR1) + 1] x 4T

 

OSC

 

   or

[(PR2) + 1] x 4T

 

OSC

 

The duty cycle of PWMx is determined by the 10-bit

value DCx<9:0>. The upper 8-bits are from register

PWxDCH and the lower 2-bits are from PWxDCL<7:6>

(PWxDCH:PWxDCL<7:6>). Table 

12-3 shows the

maximum PWM frequency (F

 

PWM

 

) given the value in

the period register. 

The number of bits of resolution that the PWM can

achieve depends on the operation frequency of the

device as well as the PWM frequency (F

 

PWM

 

).