background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  1

 

Devices included in this data sheet:

 

• PIC16C641

• PIC16C642

• PIC16C661

• PIC16C662

 

High Performance RISC CPU:

 

• Only 35 instructions to learn

• All single-cycle instructions (200 ns), except for 

program branches which are two-cycle

• Operating speed:

- DC - 20 MHz clock input

- DC - 200 ns instruction cycle

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative addressing modes

 

Peripheral Features:

 

• Up to 33 I/O pins with individual direction control

• High current sink/source for direct LED drive

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference 

(V

 

REF

 

) module

- Programmable input multiplexing from device 

inputs and internal voltage reference

- Comparator outputs can be output signals

• Timer0: 8-bit timer/counter with 8-bit 

programmable prescaler

 

Special Microcontroller Features:

 

• Power-on Reset (POR)

• Power-up Timer (PWRT) and 

Oscillator Start-up Timer (OST)

• Brown-out Reset

• Watchdog Timer (WDT) with its own on-chip RC 

oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• Serial in-circuit programming (via two pins)

 

Device

Program 

Memory x14

Data 

Memory x8

 

PIC16C641

2K

128

PIC16C642

4K

176

PIC16C661

2K

128

PIC16C662

4K

176

 

Pin Diagrams

PDIP, SOIC, Windowed CERDIP

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RC7

RC6

RC5

RC4

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PIC16C64X

MCLR/V

PP

RA0/AN0

RA1/AN1

RA2/AN2/V

REF

RA3/AN3

RA4/T0CKI

RA5

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0

RC1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

RC2

RC3

PDIP, Windowed CERDIP

PIC16C66X

10

11

2

3

4

5

6

1

8

7

9

12

13

14

15

16

17

18

19

20

29

30

31

32

33

34

35

36

37

38

39

23

24

25

26

27

28

22

21

40

MCLR/V

PP

RA0/AN0

RA1/AN1

RA2/AN2/V

REF

RA3/AN3

RA4/T0CKI

RA5

RE0/RD

OSC1/CLKIN

OSC2/CLKOUT

RE1/WR

RE2/CS

V

DD

V

SS

RD0/PSP0

RD1/PSP1

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RD7/PSP7

RD6/PSP6

RD4/PSP4

RC7

RC6

RC5

RC4

RD3/PSP3

RD2/PSP2

RD5/PSP5

RC0

RC1

RC2

RC3

 

• Four user programmable ID locations

• Program Memory Parity Error checking circuitry 

with Parity Error Reset (PER)

 

CMOS Technology:

 

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• Wide operating voltage range: 3.0V to 6.0V

• Commercial, Industrial and Automotive 

temperature ranges

• Low power consumption

- < 2.0 mA @ 5.0V, 4.0 MHz

- 15 

 

µ

 

A typical @ 3.0V, 32 kHz

- < 1.0 

 

µ

 

A typical standby current @ 3.0V

 

8-Bit EPROM Microcontrollers with Analog Comparators

 

PIC16C64X & PIC16C66X

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  2

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

Pin Diagrams (Cont.’d) 

10

11

12

13

14

15

16

17

18 19 20 21 2223 24 2526

44

8

7

6 5 4 3 2 1

27 28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

9

PIC16C66X

RA4/T0CKI

RA5

RE0/RD

OSC1/CLKIN

OSC2/CLKOUT

RC0

NC

RE1/WR

RE2/CS

V

DD

V

SS

RB3

RB2

RB1

RB0/INT

V

DD

V

SS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7

RA3/AN3

RA2/AN2/V

REF

RA1/AN1

RA0/AN0

MCLR

/V

PP

NC

RB7

RB6

RB5

RB4 NC

NC

RC6

RC5

RC4

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3

RC2

RC1

10

11

2

3

4

5

6

1

18 19 20 21 22

12 1314 15

38

8

7

44 43 42 41 40 39

16 17

29

30

31

32

33

23

24

25

26

27

28

36

34

35

9

PIC16C66X

37

RA3/AN3

RA2/AN2/V

REF

RA1/AN1

RA0/AN0

MCLR

/V

PP

NC

RB7

RB6

RB5

RB4

NC

RC6

RC5

RC4

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3

RC2

RC1

NC

NC

RC0

OSC2/CLKOUT

OSC1/CLKIN

V

SS

V

DD

RE2/CS

RE1/WR

RE0/RD

RA5

RA4/T0CKI

RC7

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

V

SS

V

DD

RB0/INT

RB1

RB2

RB3

TQFP

PLCC

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  3

 

PIC16C64X & PIC16C66X

 

Table of Contents

 

1.0

General Description .......................................................................................................................................... 5

2.0

PIC16C64X & PIC16C66X Device Varieties .................................................................................................... 7

3.0

Architectural Overview...................................................................................................................................... 9

4.0

Memory Organization ..................................................................................................................................... 17

5.0

I/O Ports.......................................................................................................................................................... 29

6.0

Timer0 Module................................................................................................................................................ 41

7.0

Comparator Module ........................................................................................................................................ 47

8.0

Voltage Reference Module ............................................................................................................................. 53

9.0

Special Features of the CPU .......................................................................................................................... 55

10.0

Instruction Set Summary ................................................................................................................................ 73

11.0

Development Support ..................................................................................................................................... 87

12.0

Electrical Specifications .................................................................................................................................. 91

13.0

Device Characterization Information............................................................................................................. 103

14.0

Packaging Information .................................................................................................................................. 105

Appendix A:  Enhancements...................................................................................................................................... 115

Appendix B:  Compatibility ......................................................................................................................................... 115

Appendix C:  What’s New .......................................................................................................................................... 116

Appendix D:  What’s Changed ................................................................................................................................... 116

Appendix E: PIC16/17 Microcontrollers ..................................................................................................................... 117

Pin Compatibility ......................................................................................................................................................... 125

Index ........................................................................................................................................................................... 127

List of Examples.......................................................................................................................................................... 129

List of Figures.............................................................................................................................................................. 129

List of Tables............................................................................................................................................................... 130

On-Line Support.......................................................................................................................................................... 131

Reader Response ....................................................................................................................................................... 132

PIC16C64X & PIC16C66X Product Identification System .......................................................................................... 135

 

To Our Valued Customers

 

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional

amount of time to ensure that these documents are correct. However, we realize that we may have missed a few

things. If you find any information that is missing or appears in error, please use the reader response form in the

back of this data sheet to inform us. We appreciate your assistance in making this a better document.

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  4

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

NOTES:

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  5

 

PIC16C64X & PIC16C66X

 

1.0

GENERAL DESCRIPTION

 

PIC16C64X & PIC16C66X devices are 28-pin and

40-pin EPROM-based members of the versatile

PIC16CXXX family of low-cost, high-performance,

CMOS, fully-static, 8-bit microcontrollers.

All PIC16/17 microcontrollers employ an advanced

RISC architecture. The PIC16CXXX family has

enhanced core features, eight-level deep stack, and

multiple internal and external interrupt sources. The

separate instruction and data buses of the Harvard

architecture allow a 14-bit wide instruction word with

the separate 8-bit wide data. The two-stage instruction

pipeline allows all instructions to execute in a sin-

gle-cycle, except for program branches (which require

two cycles). A total of 35 instructions (reduced instruc-

tion set) are available. Additionally, a large register set

gives some of the architectural innovations used to

achieve a very high performance. 

PIC16CXXX microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in its class.

The PIC16C641 has 128 bytes of RAM and the

PIC16C642 has 176 bytes of RAM. Both devices have

22 I/O pins, and an 8-bit timer/counter with an 8-bit pro-

grammable prescaler. In addition, they have two analog

comparators with a programmable on-chip voltage ref-

erence module. Program Memory has internal parity

error detection circuitry with a Parity Error Reset. The

comparator module is ideally suited for applications

requiring a low-cost analog interface (e.g., battery

chargers, threshold detectors, white goods

controllers, etc.).

The PIC16C661 has 128 bytes of RAM and the

PIC16C662 has 176 bytes of RAM. Both devices have

33 I/O pins, and an 8-bit timer/counter with an 8-bit pro-

grammable prescaler. They also have an 8-bit Parallel

Slave Port. In addition, the devices have two analog

comparators with a programmable on-chip voltage ref-

erence module. Program Memory has internal parity

error detection circuitry with a Parity Error Reset. The

comparator module is ideally suited for applications

requiring a low-cost analog interface (e.g., battery

chargers, threshold detectors, white goods

controllers, etc.).

PIC16CXXX devices have special features to reduce

external components, thus reducing cost, enhancing

system reliability and reducing power consumption.

There are four oscillator options, of which the single pin

RC oscillator provides a low-cost solution, the LP

oscillator minimizes power consumption, XT is a

standard crystal, and the HS is for High Speed crystals.

The SLEEP (power-down) mode offers power saving.

The user can wake-up the chip from SLEEP through

several external and internal interrupts and resets. 

A highly reliable Watchdog Timer (WDT) with its own

on-chip RC oscillator provides protection against soft-

ware lock-up. 

A UV-erasable CERDIP-packaged version is ideal for

code development while the cost-effective One-Time

Programmable (OTP) version is suitable for production

in any volume. 

The PIC16CXXX series fit perfectly in applications

ranging from battery chargers to low-power remote

sensors. The EPROM technology makes

customization of application programs (detection

levels, pulse generation, timers, etc.) extremely fast

and convenient. The small footprint packages make

this microcontroller series perfect for all applications

with space limitations. Low-cost, low-power,

high-performance, ease of use, and I/O flexibility make

the PIC16C64X & PIC16C66X very versatile.

 

1.1

Family and Upward Compatibility

 

Those users familiar with the PIC16C5X family of

microcontrollers will realize that this is an enhanced

version of the PIC16C5X architecture. Please refer to

Appendix A for a detailed list of enhancements. Code

written for PIC16C5X can be easily ported to the

PIC16C64X & PIC16C66X (Appendix B).

 

1.2

Development Support

 

PIC16C64X & PIC16C66X devices are supported by

the complete line of Microchip Development tools,

including:

• MPLAB Integrated Development Environment 

including MPLAB-Simulator.

• MPASM Universal Assembler and MPLAB-C Uni-

versal C compiler.

• PRO MATE II and PICSTART Plus device pro-

grammers.

• PICMASTER In-circuit Emulator System

 

fuzzy

 

TECH-MP Fuzzy Logic Development Tools

• DriveWay Visual Programming Tool

Please refer to Section 11.0 for more details about

these and other Microchip development tools.

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  6

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

TABLE 1-1:

PIC16C64X & PIC16C66X DEVICE FEATURES

PIC16C641

20

2K

128

TMR0

2

Yes

-

4

22

3.0-6.0

Yes

28-pin PDIP, SOIC, Windowed CDIP

PIC16C642

20

4K

176

TMR0

2

Yes

-

4

22

3.0-6.0

Yes

28-pin PDIP, SOIC, Windowed CDIP

PIC16C661

20

2K

128

TMR0

2

Yes

Yes

5

3

3

3.0-6.0

Yes

40-pin PDIP, Windowed CDIP; 

44-pin PLCC, TQFP

PIC16C662

20

4K

176

TMR0

2

Yes

Yes

5

3

3

3.0-6.0

Yes

40-pin PDIP, Windowed CDIP; 

44-pin PLCC, TQFP

All PIC16/17 Family devices have Power-on Reset, selectable W

atchdog 

T

imer

, selectable code protect, and high I/O current 

capability

.

All PIC16CXXX Family devices use serial programming with clock pin RB6 and data pin RB7.

Maximum Frequency of Operation (MHz)

EPROM

Data Memory (bytes)

Timer Module(s)

Comparator(s)

Internal Reference Voltage

Interrupt Sources

I/O Pins

Voltage Range (Volts)

Brown-out Reset

Packages

Program Memory

Clock

Memory

Peripherals

Features

Parallel Slave Port

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  7

 

PIC16C64X & PIC16C66X

 

2.0

PIC16C64X & PIC16C66X 

DEVICE VARIETIES

 

A variety of frequency ranges and packaging options

are available. Depending on application and production

requirements the proper device option can be selected

using the information in the Product Identification Sys-

tem page at the end of this data sheet. When placing

orders, please use that page of the data sheet to spec-

ify the correct part number.

 

2.1

UV Erasable Devices

 

The UV erasable version, offered in CERDIP package

is optimal for prototype development and pilot

programs. This version can be erased and

reprogrammed to any of the oscillator modes.

Microchip's PICSTART

 

®

 

 Plus and PRO 

MATE

 

® 

 

II

programmers both support programming of the

PIC16C64X & PIC16C66X.

 

2.2

One-Time-Programmable (OTP) 

Devices

 

The availability of OTP devices is especially useful for

customers who need flexibility for frequent code

updates and small volume applications. In addition to

the program memory, the configuration bits must also

be programmed.

 

2.3

Quick-Turnaround-Production (QTP) 

Devices

 

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code pat-

terns have stabilized. The devices are identical to the

OTP devices but with all EPROM locations and config-

uration options already programmed by the factory.

Certain code and prototype verification procedures

apply before production shipments are available.

Please contact your Microchip Technology sales office

for more details.

 

2.4

Serialized Quick-Turnaround-

Production (SQTP

 

SM

 

) Devices

 

Microchip offers a unique programming service where

a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  8

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

NOTES:

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  9

 

PIC16C64X & PIC16C66X

 

3.0

ARCHITECTURAL OVERVIEW

 

The high performance of the PIC16C64X &

PIC16C66X devices can be attributed to a number of

architectural features commonly found in RISC micro-

processors. To begin with, the PIC16C64X &

PIC16C66X use a Harvard architecture in which pro-

gram and data are accessed from separate memories

using separate buses. This improves bandwidth over

traditional von Neumann architecture where program

and data are fetched from the same memory. Separat-

ing program and data memory further allows instruc-

tions to be sized differently than an 8-bit wide data

word. Instruction opcodes are 14-bits wide making it

possible to have all single word instructions. A 14-bit

wide program memory access bus fetches a 14-bit

instruction in a single cycle. A two-stage pipeline over-

laps fetch and execution of instructions. Consequently,

all instructions (35) execute in a single cycle (200 ns @

20 MHz) except for program branches, which require

two cycles. 

The PIC16C641 and PIC16C661 both address 2K x 14

on-chip program memory while the PIC16C642 and

PIC16C662 address 4K x 14. All program memory is

internal.

PIC16C64X & PIC16C66X devices can directly or indi-

rectly address their register files or data memory. All

special function registers including the program

counter are mapped in the data memory. These

devices have an orthogonal (symmetrical) instruction

set that makes it possible to carry out any operation on

any register using any addressing mode. This symmet-

rical nature and lack of ‘special optimal situations’

make programming with the PIC16C64X & PIC16C66X

simple yet efficient. In addition, the learning curve is

reduced significantly.

PIC16C64X & PIC16C66X devices contain an 8-bit

ALU and working register. The ALU is a general pur-

pose arithmetic unit. It performs arithmetic and Bool-

ean functions between data in the working register and

any register file.

The ALU is 8-bits wide and capable of addition,

subtraction, shift, and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the working register

(W register). The other operand is a file register or an

immediate constant. In single operand instructions, the

operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a Borrow and Digit Borrow out bit,

respectively, bit in subtraction. See the 

 

SUBLW

 

 and

 

SUBWF

 

 instructions for examples.

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  10

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

FIGURE 3-1:

PIC16C641/642 BLOCK DIAGRAM

EPROM

Program

Memory

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

7

RAM Bank

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR

V

DD

, V

SS

Voltage

Brown-out

Reset

8

3

Timer0

PORTA

Comparator

RA3/AN3

RA2/AN2/V

REF

RA1/AN1

RA0/AN0

Reference

RA4/T0CKI

+

-

+

-

PORTB

RB0/INT

Select

RB1

RB2

RB3

RB4

RB5

RB6

RB7

PORTC

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

RA5

Parity Error

Reset

PIC16C641 has 2K x 14 Program Memory and 128 x 8 RAM

PIC16C642 has 4K x 14 Program Memory and 176 x 8 RAM

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  11

 

PIC16C64X & PIC16C66X

 

FIGURE 3-2:

PIC16C661/662 BLOCK DIAGRAM 

EPROM

Program

Memory

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

7

RAM Bank

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

Voltage

8

3

Timer0

PORTA

Comparator

RA3/AN3

RA2/AN2/V

REF

RA1/AN1

RA0/AN0

Reference

RA4/T0CKI

+

-

+

-

PORTB

RB0/INT

Select

RB1

RB2

RB3

RB4

RB5

RB6

RB7

PORTC

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

PORTD

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

PORTE

RE0/RD

RE1/WR

RE2/CS

Parallel

Slave

Port

RA5

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR

V

DD

, V

SS

Brown-out

Reset

Parity Error

Reset

PIC16C661 has 2K x 14 Program Memory and 128 x 8 RAM

PIC16C662 has 4K x 14 Program Memory and 176 x 8 RAM

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  12

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

TABLE 3-1:

PIC16C641/642 PINOUT DESCRIPTION 

 

Name

Pin #

I/O/P

Type

Buffer

Type

Description

 

OSC1/CLKIN

9

I

ST/CMOS Oscillator crystal input or external clock source input.

OSC2/CLKOUT

10

O

Oscillator crystal output. Connects to crystal or resonator in crystal 

oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 

1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR/V

 

PP

 

1

I/P

ST

Master clear (reset) input or programming voltage input. This pin is 

an active low reset to the device. 

PORTA is a bi-directional I/O port.

RA0/AN0

2

I/O

ST

Analog comparator input.

RA1/AN1

3

I/O

ST

Analog comparator input. 

RA2/AN2/V

 

REF

 

4

I/O

ST

Analog comparator input or V

 

REF

 

 output.

RA3/AN3

5

I/O

ST

Analog comparator input or comparator output.

RA4/T0CKI

6

I/O

ST

Can be selected to be the clock input to the Timer0 timer/counter

or a comparator output. Output is open drain type.

RA5

7

I/O

ST

PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-ups on all inputs. 

RB0/INT

21

I/O

TTL/ST

 

(1)

 

RB0 can also be selected as an external interrupt pin.

RB1

22

I/O

TTL

RB2

23

I/O

TTL

RB3

24

I/O

TTL

RB4

25

I/O

TTL

Interrupt on change pin.

RB5

26

I/O

TTL

Interrupt on change pin.

RB6

27

I/O

TTL/ST

 

(2)

 

Interrupt on change pin. Serial programming clock.

RB7

28

I/O

TTL/ST

 

(2)

 

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0

11

I/O

ST

RC1

12

I/O

ST

RC2

13

I/O

ST

RC3

14

I/O

ST

RC4

15

I/O

ST

RC5

16

I/O

ST

RC6

17

I/O

ST

RC7

18

I/O

ST

V

 

SS

 

8,19

P

Ground reference for logic and I/O pins.

V

 

DD

 

20

P

Positive supply for logic and I/O pins.

Legend:

O = output

I/O = input/output

P = power

I = input

— = not used

ST = Schmitt Trigger input

TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  13

 

PIC16C64X & PIC16C66X

 

TABLE 3-2:

   PIC16C661/662 PINOUT DESCRIPTION

 

Name

DIP 

Pin #

QFP 

Pin # 

PLCC

 Pin #

I/O/P

Type

Buffer

Type

Description

 

OSC1/CLKIN

13

30

14

I

ST/CMOS Oscillator crystal input or external clock source 

input.

OSC2/CLKOUT

14

31

15

O

Oscillator crystal output. Connects to crystal or reso-

nator in crystal oscillator mode. In RC mode, OSC2 

pin outputs CLKOUT which has 1/4 the frequency of 

OSC1, and denotes the instruction cycle rate.

MCLR/V

 

PP

 

1

18

2

I/P

ST

Master clear (reset) input or programming voltage 

input. This pin is an active low reset to the device. 

PORTA is a bi-directional I/O port.

RA0/AN0

2

19

3

I/O

ST

Analog comparator input.

RA1/AN1

3

20

4

I/O

ST

Analog comparator input.

RA2/AN2/V

 

REF

 

4

21

5

I/O

ST

Analog comparator input or V

 

REF

 

 output.

RA3/AN3

5

22

6

I/O

ST

Analog comparator input or comparator output.

RA4/T0CKI

6

23

7

I/O

ST

Can be selected to be the clock input to the

Timer0 timer/counter or a comparator output.

Output is open drain type.

RA5

7

24

8

I/O

ST

PORTB is a bi-directional I/O port. PORTB can be 

software programmed for internal weak pull-ups on 

all inputs. 

RB0/INT

33

8

36

I/O

TTL/ST

 

(1)

 

RB0 can also be selected as an external

interrupt pin.

RB1

34

9

37

I/O

TTL

RB2

35

10

38

I/O

TTL

RB3

36

11

39

I/O

TTL

RB4

37

14

41

I/O

TTL

Interrupt on change pin.

RB5

38

15

42

I/O

TTL

Interrupt on change pin.

RB6

39

16

43

I/O

TTL/ST

 

(2)

 

Interrupt on change pin. Serial programming

clock.

RB7

40

17

44

I/O

TTL/ST

 

(2)

 

Interrupt on change pin. Serial programming

data.

PORTC is a bi-directional I/O port.

RC0

15

32

16

I/O

ST

RC1

16

35

18

I/O

ST

RC2

17

36

19

I/O

ST

RC3

18

37

20

I/O

ST

RC4

23

42

25

I/O

ST

RC5

24

43

26

I/O

ST

RC6

25

44

27

I/O

ST

RC7

26

1

29

I/O

ST

Legend:

O = output

I/O = input/output

P = power

I = input

— = not used

ST = Schmitt Trigger input

TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used 

in the Parallel Slave Port Mode (for interfacing to a microprocessor port).

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  14

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

PORTD can be a bi-directional I/O port or parallel 

slave port for interfacing to a microprocessor bus.

RD0/PSP0

19

38

21

I/O

ST/TTL

 

(3)

 

RD1/PSP1

20

39

22

I/O

ST/TTL

 

(3)

 

RD2/PSP2

21

40

23

I/O

ST/TTL

 

(3)

 

RD3/PSP3

22

41

24

I/O

ST/TTL

 

(3)

 

RD4/PSP4

27

2

30

I/O

ST/TTL

 

(3)

 

RD5/PSP5

28

3

31

I/O

ST/TTL

 

(3)

 

RD6/PSP6

29

4

32

I/O

ST/TTL

 

(3)

 

RD7/PSP7

30

5

33

I/O

ST/TTL

 

(3)

 

PORTE is a bi-directional I/O port.

RE0/RD

8

25

9

I/O

ST/TTL

 

(3)

 

RE0/RD read control for parallel slave port.

RE1/WR

9

26

10

I/O

ST/TTL

 

(3)

 

RE1/WR write control for parallel slave port.

RE2/CS

10

27

11

I/O

ST/TTL

 

(3)

 

RE2/CS select control for parallel slave port.

V

 

SS

 

12,31

6,29

13,34

P

Ground reference for logic and I/O pins.

V

 

DD

 

11,32

7,28

12,35

P

Positive supply for logic and I/O pins.

NC

12,13,

33,34

1,17 

28,40

Not Connected.

 

Name

DIP 

Pin #

QFP 

Pin # 

PLCC

 Pin #

I/O/P

Type

Buffer

Type

Description

 

Legend:

O = output

I/O = input/output

P = power

I = input

— = not used

ST = Schmitt Trigger input

TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when configured as a general purpose I/O and a TTL input when used 

in the Parallel Slave Port Mode (for interfacing to a microprocessor port).

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  15

 

PIC16C64X & PIC16C66X

 

3.1

Clocking Scheme/Instruction Cycle

 

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3, and Q4. Internally, the

program counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The

instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution flow is shown in Figure 3-3.

 

3.2

Instruction Flow/Pipelining

 

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3, and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., 

 

GOTO

 

)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register (IR)” in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

 

FIGURE 3-3:

CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW 

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

OSC1

Q1

Q2

Q3

Q4

PC

OSC2/CLKOUT

(RC mode)

PC

PC+1

PC+2

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 

Tcy0

Tcy1

Tcy2

Tcy3

Tcy4

Tcy5

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. CALL SUB_1

Fetch 3

Execute 3

4. BSF   PORTA, BIT3 (Forced NOP)

Fetch 4

Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  16

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

NOTES:

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  17

 

PIC16C64X & PIC16C66X

 

4.0

MEMORY ORGANIZATION

 

4.1

Program Memory Organization

 

The PIC16C64X & PIC16C66X have a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. For the PIC16C641 and PIC16C661

only the first 2K x 14 (0000h - 07FFh) is physically

implemented. For the PIC16C642 and PIC16C662 only

the first 4K x 14 (0000h - 0FFh) is physically imple-

mented. Accessing a location above the 2K or 4K

boundary will cause a wrap-around. The reset vector is

at 0000h and the interrupt vector is at 0004h (Figure 4-

1 and Figure 4-2). See Section 4.4 for Program Mem-

ory paging.

 

FIGURE 4-1:

PIC16C641/661 PROGRAM 

MEMORY MAP AND STACK   

PC<12:0>

13

0000h

0004h

0005h

07FFh

0800h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory 

CALL, RETURN

RETFIE, RETLW

Stack Level 2

2000h

2007h

3FFFh

TEST

Configuration Word

TEST

User Memory Space

 

FIGURE 4-2:

PIC16C642/662 PROGRAM 

MEMORY MAP AND STACK 

PC<12:0>

13

0000h

0004h

0005h

0FFFh

1000h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

2000h

2007h

3FFFh

TEST

Configuration Word

TEST

User Memory Space

Page0 

On-chip Program

Memory

Page1 

07FFh

0800h

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  18

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

4.2

Data Memory Organization

 

The data memory (Figure 4-4) is partitioned into two

banks which contain the general purpose registers and

the special function registers. Bank 0 is selected when

bit RP0 (STATUS<5>) is cleared. Bank 1 is selected

when the RP0 bit is set. The Special Function Regis-

ters are located in the first 32 locations of each Bank.

Register locations A0h-EFh (Bank 1) are general pur-

pose registers implemented as static RAM. Some spe-

cial function registers are mapped in Bank 1.

4.2.1

GENERAL PURPOSE REGISTER FILE

The register file is organized as 176 x 8 for the

PIC16C642/662, and 128 x8 for the PIC16C641/661.

Each is accessed either directly, or indirectly through

the File Select Register FSR (Section 4.5).

 

FIGURE 4-3:

PIC16C641/661 DATA 

MEMORY MAP 

INDF

(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PIR1

CMCON

INDF

(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

TRISC

PIE1

PCON

VRCON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h

A0h

General

Purpose

Register

General

Purpose

Register

7Fh

FFh

Bank 0

Bank 1

File

Address

BFh

C0h

  Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

2: Not implemented on the PIC16C641.

File

Address

PORTD

(2)

TRISD

(2)

TRISE

(2)

PCLATH

INTCON

PORTE

(2)

PCLATH

INTCON

Mapped

in Page 0

EFh

F0h

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  19

 

PIC16C64X & PIC16C66X

 

FIGURE 4-4:

PIC16C642/662 DATA 

MEMORY MAP   

INDF

(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

PIR1

CMCON

INDF

(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PIE1

PCON

VRCON

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h

A0h

General

Purpose

Register

7Fh

FFh

Bank 0

Bank 1

File

Address

      Unimplemented data memory loca-

tions, read as '0'.

Note 1: Not a physical register.

2: Not implemented on the PIC16C642.

File

Address

PORTC

TRISC

PORTD

(2)

TRISD

(2)

PORTE

(2)

TRISE

(2)

General

Purpose

Register

Mapped

in Bank 0

EFh

F0h

 

4.2.2

SPECIAL FUNCTION REGISTERS

The special function registers are registers used by the

CPU and Peripheral Modules for controlling the desired

operation of the device (Table 4-1). These registers are

static RAM.

The special function registers can be classified into two

sets (core and peripheral). The special function regis-

ters associated with the “core” functions are described

in this section. Those related to the operation of the

peripheral features are described in the section of that

peripheral feature. 

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  20

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

TABLE 4-1:

SPECIAL FUNCTION REGISTERS   

 

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2 

Bit 1

Bit 0

Value on

POR,

BOR,

PER

Value on

all other

 resets

 

(1)

 

Bank 0

 

00h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

 

xxxx xxxx

xxxx xxxx

 

01h

TMR0

Timer0 Module’s Register

 

xxxx xxxx

uuuu uuuu

 

02h

PCL

Program Counter's (PC) Least Significant Byte

 

0000 0000

0000 0000

 

03h

STATUS

IRP

 

(2)

 

RP1

 

(2)

 

RP0

TO

PD

Z

DC

C

 

0001 1xxx

000q quuu

 

04h

FSR

Indirect data memory address pointer

 

xxxx xxxx

uuuu uuuu

 

05h

PORTA

PORTA Data Latch when written: PORTA pins when read

 

--xx 0000

--xu 0000

 

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

 

xxxx xxxx

uuuu uuuu

 

06h

PORTC

PORTC Data Latch when written: PORTC pins when read

 

xxxx xxxx

uuuu uuuu

 

06h

PORTD

 

(3)

 

PORTD Data Latch when written: PORTD pins when read

 

xxxx xxxx

uuuu uuuu

 

06h

PORTE

 

(3)

 

RE2

RE1

RE0

 

---- -xxx

---- -uuu

 

0Ah

PCLATH

Write buffer for upper 5 bits of program counter

 

---0 0000

---0 0000

 

0Bh

INTCON

GIE PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

 

0000 000x

0000 000u

 

0Ch

PIR1

PSPIF

 

(4)

 

CMIF

 

00-- ----

00-- ----

 

0Dh-1Eh Unimplemented

 

 

1Fh

CMCON

C2OUT

C1OUT

CIS

CM2

CM1

CM0

 

00-- 0000

00-- 0000

 

Bank 1

 

80h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

 

xxxx xxxx

xxxx xxxx

 

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

 

1111 1111

1111 1111

 

82h

PCL

Program Counter's (PC) Least Significant Byte

 

0000 0000

0000 0000

 

83h

STATUS

IRP

 

(2)

 

RP1

 

(2)

 

RP0

TO

PD

Z

DC

C

 

0001 1xxx

000q quuu

 

84h

FSR

Indirect data memory address pointer

 

xxxx xxxx

uuuu uuuu

 

85h

TRISA

PORTA Data Direction Register

 

--11 1111

--11 1111

 

86h

TRISB

PORTB Data Direction Register

 

1111 1111

1111 1111

 

86h

TRISC

PORTC Data Direction Register

 

1111 1111

1111 1111

 

86h

TRISD

 

(3)

 

PORTD Data Direction Register

 

1111 1111

1111 1111

 

86h

TRISE

 

(3)

 

IBF

OBF

IBOV

PSPMODE

TRISE2

TRISE1

TRISE0

 

0000 -111

0000 -111

 

8Ah

PCLATH

Write buffer for upper 5 bits of program counter

 

---0 0000

---0 0000

 

8Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

 

0000 000x

0000 000x

 

8Ch

PIE1

PSPIE

 

(4)

 

CMIE

 

00-- ----

00-- ----

 

8Dh

Unimplemented

 

 

8Eh

PCON

MPEEN

PER

POR

BOR

 

u--- -qqq

u--- -uuu

 

8Fh-9Eh

Unimplemented

 

 

9Fh

VRCON

VREN

VROE

VRR

VR3

VR2

VR1

VR0

 

000- 0000

000- 0000

 

Legend:  

 

-

 

 = unimplemented locations read as ‘0’, 

 

u

 

 = unchanged, 

 

x

 

 = unknown, 

 

q

 

 = value depends on condition, shaded = unimplemented

Note

1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: The IRP and RP1 bits are reserved, always maintain these bits clear.

3: The PORTD, PORTE, TRISD, and TRISE registers are not implemented on the PIC16C641/642.

4: Bits PSPIE and PSPIF are reserved on the PIC16C641/642, always maintain these bits clear.

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  21

 

PIC16C64X & PIC16C66X

 

4.2.2.1

STATUS REGISTER

The STATUS register, shown in Figure 4-5, contains

the arithmetic status of the ALU, the RESET status, and

the bank select bits for data memory.

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended. 

For example, 

 

CLRF STATUS

 

 will clear the upper-three

bits and set the Z bit. This leaves the STATUS register

as 

 

000uu1uu

 

 (where 

 

u

 

 = unchanged).

It is recommended, therefore, that only 

 

BCF, BSF,

SWAPF,

 

 and 

 

MOVWF

 

 instructions are used to alter the

STATUS register because these instructions do not

affect any status bit. For other instructions, not affecting

any status bits, see the “Instruction Set Summary.” 

 

Note 1:

 

The IRP and RP1 bits (STATUS<7:6>) are

reserved on the PIC16C64X &

PIC16C66X and should be maintained

clear. Use of these bits as general pur-

pose R/W bits is NOT recommended,

since this may affect upward compatibility

with future products.

 

Note 2:

 

The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the 

 

SUBLW

 

 and 

 

SUBWF

 

instructions for examples.

 

FIGURE 4-5:

STATUS REGISTER (ADDRESS 03h, 83h)

 

R/W-0

R/W-0

R/W-0

R-1

R-1

R/W-x

R/W-x

R/W-x

IRP

RP1

RP0

TO

PD

Z

DC

C

R = Readable bit

W = Writable bit

U = Unimplemented bit, 

       read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

 

IRP: 

 

Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

Bit IRP is reserved on the PIC16C64X & PIC16C66X, always maintain this bit clear. 

bit  6-5:

 

RP1:RP0

 

: Register Bank Select bits (used for direct addressing)

 

11

 

 = Bank 3 (180h - 1FFh)

 

10

 

 = Bank 2 (100h - 17Fh)

 

01

 

 = Bank 1 (80h - FFh)

 

00

 

 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. Bit RP1 is reserved on the PIC16C64X & PIC16C66X, always maintain this bit

clear.

bit  4:

 

TO

 

: Time-out bit

1 = After power-up, 

 

CLRWDT

 

 instruction, or 

 

SLEEP

 

 instruction

0 = A WDT time-out occurred

bit  3:

 

PD

 

: Power-down bit

1 = After power-up or by the 

CLRWDT

 instruction

0 = By execution of the 

SLEEP

 instruction

bit  2:

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit  1:

DC: Digit carry/borrow bit (

ADDWF

ADDLW,SUBLW,SUBWF

 instructions) (for borrow the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit  0:

C: Carry/borrow bit (

ADDWF

ADDLW,SUBLW,SUBWF 

instructions)

1 = A carry-out from the most significant bit of the result occurred

0 = No carry-out from the most significant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (

RRF

RLF

) instructions, this bit is loaded with either the high or low order bit of

the source register.

background image

PIC16C64X & PIC16C66X

DS30559A-page  22

Preliminary

©

 1996 Microchip Technology Inc.

4.2.2.2

OPTION REGISTER

The OPTION register is a readable and writable

register which contains various control bits to configure

the TMR0/WDT prescaler, the external RB0/INT

interrupt, TMR0, and the weak pull-ups on PORTB.

Note:

To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT.

FIGURE 4-6:

OPTION REGISTER (ADDRESS 81h)

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

R= Readable bit

W= Writable bit

U= Unimplemented bit, 

read as ‘0’

- n= Value at POR reset

bit7

bit0

bit 7:

RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit  6:

INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit  5:

T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit  4:

T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit  3:

PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit  2-0: PS2:PS0: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value

TMR0 Rate

WDT Rate

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  23

PIC16C64X & PIC16C66X

4.2.2.3

INTCON REGISTER

The INTCON register is a readable and writable

register which contains the various enable and flag bits

for all non-peripheral interrupt sources.

 

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

FIGURE 4-7:

INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-x

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

R= Readable bit

W= Writable bit

U= Unimplemented bit, 

read as ‘0’

- n= Value at POR reset

bit7

bit0

bit 7:

GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit  6:

PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

bit  5:

T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit  4:

INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit  3:

RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit  2:

T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit  1:

INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit  0:

RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (See Section 5.2 to clear interrupt)

0 = None of the RB7:RB4 pins have changed state

background image

PIC16C64X & PIC16C66X

DS30559A-page  24

Preliminary

©

 1996 Microchip Technology Inc.

4.2.2.4

PIE1 REGISTER

This register contains the individual enable bits for the

comparator and Parallel Slave Port interrupts.

FIGURE 4-8:

PIE1 REGISTER (ADDRESS 8Ch)

 

R/W-0

R/W-0

U-0

U-0

U-0

U-0

U-0

U-0

PSPIE

(1)

CMIE

R= Readable bit

W= Writable bit

U= Unimplemented bit, 

read as ‘0’

- n= Value at POR reset

bit7

bit0

bit 7:

PSPIE

(1)

Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

bit  6:

CMIE: Comparator Interrupt Enable bit

1 = Enables the Comparator interrupt

0 = Disables the Comparator interrupt

bit  5-0: Unimplemented: Read as '0'

Note 1: Bit PSPIE is reserved on the PIC16C641/642, always maintain this bit clear.

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  25

PIC16C64X & PIC16C66X

4.2.2.5

PIR1 REGISTER

This register contains the individual flag bits for the

comparator and Parallel Slave Port interrupts.

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

FIGURE 4-9:

PIR1 REGISTER (ADDRESS 0Ch)

R/W-0

R/W-0

U-0

U-0

U-0

U-0

U-0

U-0

PSPIF

(1)

CMIF

R= Readable bit

W= Writable bit

U= Unimplemented bit, 

read as ‘0’

- n= Value at POR reset

bit7

bit0

bit 7:

PSPIF

(1)

Parallel Slave Port Interrupt Flag bit

1 = A read or write operation has taken place (must be cleared in software)

0 = No read or write operation has taken place

bit  6:

CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

bit  5-0: Unimplemented: Read as '0'

Note 1: Bit PSPIF is reserved on the PIC16C641/642, always maintain this bit clear.

background image

PIC16C64X & PIC16C66X

DS30559A-page  26

Preliminary

©

 1996 Microchip Technology Inc.

4.2.2.6

PCON REGISTER

The PCON register contains flag bits to differentiate

between a Power-on Reset (POR), an external MCLR

reset, WDT reset, Brown-out Reset (BOR), and Parity

Error Reset (PER). The PCON register also contains a

status bit, MPEEN, which reflects the value of the

MPEEN bit in Configuration Word. See Table 9-4 for

status of these bits on various resets.

 

Note:

BOR is unknown on Power-on Reset. It

must then be set by the user and checked

on subsequent resets to see if BOR is

cleared, indicating a brown-out has

occurred. The BOR status bit is a “don't

care” and is not necessarily predictable if

the brown-out circuit is disabled (by

programming the BODEN bit in the

Configuration word).

FIGURE 4-10: PCON REGISTER (ADDRESS 8Eh)

R-U

U-0

U-0

U-0

U-0

R/W-1

R/W-0

R/W-u

MPEEN

PER

POR

BOR

R= Readable bit

W= Writable bit

U= Unimplemented bit, 

read as ‘0’

- n= Value at POR reset

bit7

bit0

bit 7:

MPEEN: Memory Parity Error Circuitry Status bit

Reflects the value of Configuration Word bit, MPEEN

bit 6-3:

Unimplemented: Read as '0'

bit 2:

PER: Memory Parity Error Reset Status bit

1 = No error occurred

0 = Program memory fetch parity error occurred 

(must be set in software after a Parity Error Reset occurs)

bit  1:

POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit  0:

BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  27

PIC16C64X & PIC16C66X

4.3

PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte

comes from the PCL register, which is readable and

writable. The high byte (PC<12:8>) is not directly read-

able or writable and comes from PCLATH. On any

reset, the PC is cleared. Figure 4-11 shows the two

situations for the loading of the PC. The upper example

in the figure shows how the PC is loaded on a write to

PCL (PCLATH<4:0> 

 PCH). The lower example in

the figure shows how the PC is loaded during a 

CALL

or 

GOTO

 instruction (PCLATH<4:3> 

 PCH).

FIGURE 4-11: LOADING OF PC IN 

DIFFERENT SITUATIONS

4.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an

offset to the program counter (

ADDWF PCL

). When

doing a table read using a computed GOTO method,

care should be exercised if the table location crosses a

PCL memory boundary (each 256 byte block). Refer to

the application note 

“Implementing a Table Read”

(AN556).

PC

12

8

7

0

5

PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode <10:0>

8

PC

12

11 10

0

11

PCLATH<4:3>

PCH

PCL

8

7

2

PCLATH

PCH

PCL

PCL as 

Destination

4.3.2

STACK

PIC16C64X & PIC16C66X devices have an 8 level

deep x 13-bit wide hardware stack (Figure 4-2). The

stack space is not part of either program or data space

and the stack pointer is not readable or writable. The

PC is PUSHed onto the stack when a 

CALL

 instruction

is executed or an interrupt causes a branch. The stack

is POPed in the event of a 

RETURN, RETLW

 or a 

RETFIE

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on). 

4.4

Program Memory Paging

PIC16C642 and PIC16C662 devices have 4K of pro-

gram memory, but the 

CALL

 and 

GOTO

 instructions only

have an 11-bit address range. This 11-bit address

range allows a branch within a 2K program memory

page size. To allow 

CALL

 and 

GOTO

 instructions to

address the entire 4K program memory address range,

there must be another bit to specify the program mem-

ory page. This paging bit comes from the PCLATH<3>

bit (Figure 4-11). When doing a 

CALL

 or 

GOTO

 instruc-

tion, the user must ensure that this page select bit

(PCLATH<3>) is programmed so that the desired pro-

gram memory page is addressed. If a return from a

CALL

 instruction (or interrupt) is executed, the entire

13-bit PC is pushed onto the stack. Therefore, manipu-

lation of the PCLATH<3> bit is not required for the

return instructions (which POPs the address from the

stack).

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions. 

Note 2: There are no instructions mnemonics

called PUSH or POP. These are actions

that occur from the execution of the 

CALL,

RETURN, RETLW,

 and 

RETFIE

 instruc-

tions, or the vectoring to an interrupt

address.

Note:

The PIC16C64X & PIC16C66X ignore the

PCLATH<4> bit, which is used for program

memory pages 2 and 3 (1000h - 1FFFh).

The use of PCLATH<4> as a general pur-

pose read/write bit is not recommended

since this may affect upward compatibility

with future products.

background image

PIC16C64X & PIC16C66X

DS30559A-page  28

Preliminary

©

 1996 Microchip Technology Inc.

4.5

Indirect Addressing, INDF, and FSR 

Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing. 

Indirect addressing is possible by using the INDF reg-

ister. Any instruction using the INDF register actually

accesses data pointed to by the file select register

(FSR). Reading INDF itself indirectly will produce 00h.

Writing to the INDF register indirectly results in a no-

operation (although status bits may be affected). An

effective 9-bit address is obtained by concatenating the

8-bit FSR register and the IRP bit (STATUS<7>), as

shown in Figure 4-12. However, bit IRP is not used in

the PIC16C64X & PIC16C66X.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 4-1.

EXAMPLE 4-1:

INDIRECT ADDRESSING

          movlw 0x20  ;initialize pointer

          movwf FSR   ;to RAM

NEXT      clrf  INDF  ;clear INDF register

          incf  FSR   ;inc pointer

          btfss FSR,4 ;all done? 

          goto  NEXT  ;no goto next

                      ;yes continue

CONTINUE:

FIGURE 4-12: DIRECT/INDIRECT ADDRESSING   

For memory map detail see Figure 4-3 and Figure 4-4.

Note 1: Bits RP1 and IRP are reserved, always maintain these bits clear.

Data

Memory

Indirect Addressing

Direct Addressing

bank select

location select

(1)

RP1 RP0

6

0

from opcode

IRP

(1)

FSR register

7

0

bank select

location select

00

01

10

11

00h

7Fh

00h

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

not used

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  29

 

PIC16C64X & PIC16C66X

 

5.0

I/O PORTS

 

The  PIC16C641  and  PIC16C642  have three ports,

PORTA, PORTB, and PORTC. PIC16C661 and

PIC16C662 devices have five ports, PORTA through

PORTE. Some pins for these I/O ports are multiplexed

with alternate functions for the peripheral features on

the device. In general, when a peripheral is enabled,

that pin may not be used as a general purpose I/O pin.

 

5.1

PORTA and TRISA Registers

 

PORTA is a 6-bit wide latch. RA4 is a Schmitt Trigger

input and an open drain output. Pin RA4 is multiplexed

with the T0CKI clock input. All other RA port pins have

Schmitt Trigger input levels and full CMOS output driv-

ers. All pins have data direction bits (TRIS registers)

which can configure these pins as input or output.

Setting a bit in the TRISA register puts the correspond-

ing output driver in a hi-impedance mode. Clearing a bit

in the TRISA register puts the contents of the output

latch on the selected pin.

Reading the PORTA register reads the status of the

pins, whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore, a write to a port implies that the port pins are

read, this value is modified, and then written to the port

data latch.

The PORTA pins are multiplexed with comparator and

voltage reference functions. The operation of these

pins are selected by control bits in the CMCON

(comparator control register) register and the VRCON

(voltage reference control) register. When selected as

comparator inputs, these pins will read as '0's.

 

FIGURE 5-1:

BLOCK DIAGRAM OF 

RA1:RA0 PINS 

 

TRISA controls the direction of the RA pins, even when

they are being used as comparator inputs. The user

must make sure to keep the pins configured as inputs

when using them as comparator inputs.

The RA2 pin will also function as the output for the

voltage reference. When in this mode, the V

 

REF

 

 pin is

a very hi-impedance output. The user must set the

TRISA<2> bit and use hi-impedance loads.

In one of the comparator modes defined by the

CMCON register, pins RA3 and RA4 become outputs

of the comparators. The TRISA<4:3> bits must be

cleared to enable outputs to use this function.

 

EXAMPLE 5-1:

INITIALIZING PORTA

 

CLRF   PORTA        ;Initialize PORTA by

                    ;clearing output latches

MOVLW  0x07         ;Turn comparators off,

MOVWF  CMCON        ;enable pins for I/O

BSF    STATUS, RP0  ;Select bank1

MOVLW  0x1F         ;Value to initialize

                    ;data direction

MOVWF  TRISA        ;Set RA<4:0> as inputs

                    ;TRISA<7:5> are clear

 

Note:

 

On reset, the TRISA register is set to all

inputs. The digital inputs are disabled and

the comparator inputs are forced to ground

to reduce excess current consumption.

Note: I/O pins have protection diodes to V

DD

 and V

SS

.

Data

bus

Q

D

Q

CK

P

N

WR

Port

WR

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

Analog

V

SS

V

DD

I/O Pin

Q

D

Q

CK

Input Mode

D

Q

EN

To Comparator

Schmitt Trigger

Input Buffer

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  30

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

FIGURE 5-2:

BLOCK DIAGRAM OF RA2 PIN

Note: I/O pin has protection diodes to V

DD

 and V

SS

.

Data

bus

Q

D

Q

CK

P

N

WR

Port

WR

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

Analog

V

SS

V

DD

RA2 Pin

Q

D

Q

CK

Input Mode

D

Q

EN

To Comparator

Schmitt Trigger

Input Buffer

VROE

V

REF

 

FIGURE 5-3:

BLOCK DIAGRAM OF RA3 PIN

Data

bus

Q

D

Q

CK

P

N

WR

Port

WR

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

Analog

V

SS

V

DD

RA3 Pin

Q

D

Q

CK

D

Q

EN

To Comparator

Schmitt Trigger

Input Buffer

Input Mode

Comparator Output

Comparator Mode = 110

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  31

 

PIC16C64X & PIC16C66X

 

FIGURE 5-4:

BLOCK DIAGRAM OF RA4 PIN

TABLE 5-1:

PORTA FUNCTIONS

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA 

 

Name

Bit #

Buffer 

Type

Function

 

RA0/AN0

bit0

ST

Input/output or comparator input.

RA1/AN1

bit1

ST

Input/output or comparator input.

RA2/AN2/V

 

REF

 

bit2

ST

Input/output or comparator input or V

 

REF

 

 output.

RA3/AN3

bit3

ST

Input/output or comparator input/output.

RA4/T0CKI

bit4

ST

Input/output or external clock input for TMR0 or comparator output. Out-

put is open drain type.

RA5

bit5

ST

Input/output.

Legend: ST = Schmitt Trigger input

 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on 

all other

resets

 

05h

PORTA

RA5

RA4

RA3

RA2

RA1

RA0

 

--xx 0000

--uu 0000

 

85h

TRISA

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

 

--11 1111

--11 1111

 

1Fh

CMCON

C2OUT

C1OUT

CIS

CM2

CM1

CM0

 

00-- 0000

00-- 0000

 

9Fh

VRCON

VREN

VROE

VRR

VR3

VR2

VR1

VR0

 

000- 0000

000- 0000

 

Legend:  

 

x

 

 = unknown, 

 

u

 

 = unchanged, 

 

-

 

 = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Data

bus

Q

D

Q

CK

N

WR

Port

WR

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

V

SS

RA4 Pin

Q

D

Q

CK

D

Q

EN

TMR0 Clock Input

Schmitt Trigger

Input Buffer

Comparator Output

Comparator Mode = 110

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  32

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

5.2

PORTB and TRISB Registers

 

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. Setting

a bit in the TRISB register puts the corresponding out-

put driver in a hi-impedance mode. Clearing a bit in the

TRISB register puts the contents of the output latch on

the selected pin(s).

Reading PORTB register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. There-

fore, a write to a port implies that the port pins are read,

this value is modified, and then written to the port data

latch.

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

done by clearing the RBPU (OPTION<7>) bit. The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are dis-

abled on a Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt

on change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RBIF interrupt (flag

latched in (INTCON<0>)). 

 

FIGURE 5-5:

BLOCK DIAGRAM OF 

RB7:RB4 PINS 

Data Latch

From other

RBPU

(2)

P

V

DD

I/O

Q

D

CK

Q

D

CK

Q

D

EN

Q

D

EN

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak

pull-up

RD Port

Latch

TTL

Input

Buffer

pin

(1)

Note 1: I/O pins have diode protection to V

DD

 and V

SS

.

 2: TRISB = '1' enables weak pull-up if RBPU = '0'

(OPTION<7>).

ST

Buffer

RB7:RB6 in serial programming mode

 

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

a)

Any read or write of PORTB. This will end the

mismatch condition.

b)

Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with

software configurable pull-ups on these four pins allow

easy interface to a keypad and make it possible for

wake-up on key-depression. (See AN552 in the

Microchip 

 

Embedded Control Handbook

 

.)

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

 

FIGURE 5-6:

BLOCK DIAGRAM OF 

RB3:RB0 PINS 

Data Latch

RBPU

(2)

P

V

DD

Q

D

CK

Q

D

CK

Q

D

EN

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak

pull-up

RD Port

RB0/INT

I/O

pin

(1)

TTL

Input

Buffer

Note 1: I/O pins have diode protection to V

DD

 and V

SS

.

     2: TRISB = '1' enables weak pull-up if RBPU = '0'

(OPTION<7>).

ST

Buffer

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  33

 

PIC16C64X & PIC16C66X

 

EXAMPLE 5-2:

INITIALIZING PORTB

 

CLRF   PORTB        ; Initialize PORTB by

                    ; clearing output

                    ; data latches

BSF    STATUS, RP0  ; Select Bank 1

MOVLW  0xCF         ; Value used to 

                    ; initialize data 

                    ; direction

MOVWF  TRISB        ; Set RB<3:0> as inputs

                    ; RB<5:4> as outputs

                    ; RB<7:6> as inputs

 

TABLE 5-3:

PORTB FUNCTIONS

TABLE 5-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

 

Name

Bit #

Buffer Type

Function

 

RB0/INT

bit0

TTL/ST

 

(1)

 

Input/output or external interrupt input. Internal software programmable 

weak pull-up.

RB1

bit1

TTL

Input/output pin. Internal software programmable weak pull-up.

RB2

bit2

TTL

Input/output pin. Internal software programmable weak pull-up.

RB3

bit3

TTL

Input/output pin. Internal software programmable weak pull-up.

RB4

bit4

TTL

Input/output pin (with interrupt on change). Internal software programmable 

weak pull-up.

RB5

bit5

TTL

Input/output pin (with interrupt on change). Internal software programmable 

weak pull-up.

RB6

bit6

TTL/ST

 

(2)

 

Input/output pin (with interrupt on change). Internal software programmable 

weak pull-up. Serial programming clock pin.

RB7

bit7

TTL/ST

 

(2)

 

Input/output pin (with interrupt on change). Internal software programmable 

weak pull-up. Serial programming data pin.

Legend:  ST = Schmitt Trigger input, TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

 

06h

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

 

xxxx xxxx

uuuu uuuu

 

86h

TRISB

TRISB7

TRISB6

TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

 

1111 1111

1111 1111

 

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

 

1111 1111

1111 1111

 

Legend:

 

x

 

 = unknown, 

 

u

 

 = unchanged, shaded cells are not used by PORTB.

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  34

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

5.3

PORTC and TRISC Registers

 

PORTC is an 8-bit bi-directional port. Each pin is indi-

vidually configurable as an input or output through the

TRISC register. PORTC pins have Schmitt Trigger

input buffers.

 

EXAMPLE 5-3:

INITIALIZING PORTC

 

CLRF   PORTC        ; Initialize PORTC by

                    ; clearing output

                    ; data latches

BSF    STATUS, RP0  ; Select Bank 1

MOVLW  0xCF         ; Value used to 

                    ; initialize data 

                    ; direction

MOVWF  TRISC        ; Set RC<3:0> as inputs

                    ; RC<5:4> as outputs

                    ; RC<7:6> as inputs

 

FIGURE 5-7:

PORTC BLOCK DIAGRAM (IN 

I/O PORT MODE)

Data

bus

WR

PORT

WR

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

input

buffer

I/O pin

(1)

Note 1: I/O pins have protection diodes to V

DD

 and V

SS

.

Q

D

CK

Q

D

CK

EN

Q

D

EN

 

TABLE 5-5:

PORTC FUNCTIONS 

TABLE 5-6:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

 

Name

Bit#

Buffer Type

Function

 

RC0

bit0

ST

Input/output

RC1

bit1

ST

Input/output

RC2

bit2

ST

Input/output

RC3

bit3

ST

Input/output

RC4

bit4

ST

Input/output

RC5

bit5

ST

Input/output

RC6

bit6

ST

Input/output

RC7

bit7

ST

Input/output

Legend: ST = Schmitt Trigger input

 

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: 

POR,

BOR

Value on all 

other resets

 

07h

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

 

xxxx xxxx

uuuu uuuu

 

87h

TRISC

TRISC7

TRISC6

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

 

1111 1111

1111 1111

 

Legend:

 

x

 

 = unknown, 

 

u

 

 = unchanged.

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  35

 

PIC16C64X & PIC16C66X

 

5.4

PORTD and TRISD Registers 

(PIC16C661 and PIC16C662 only)

 

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configurable as an input or

output.

PORTD can be configured as an 8-bit wide micropro-

cessor port (parallel slave port) by setting control bit

PSPMODE (TRISE<4>). In this mode, the input buffers

are TTL.

 

FIGURE 5-8:

PORTD BLOCK DIAGRAM (IN 

I/O PORT MODE)

Data

bus

WR

PORT

WR

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

input

buffer

I/O pin

(1)

Note 1: I/O pins have protection diodes to V

DD

 and V

SS

.

Q

D

CK

Q

D

CK

EN

Q

D

EN

 

TABLE 5-7:

PORTD FUNCTIONS

TABLE 5-8:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

 

Name

Bit#

Buffer Type

Function

 

RD0/PSP0

bit0

ST/TTL

 

(1)

 

Input/output port pin or parallel slave port bit0

RD1/PSP1

bit1

ST/TTL

 

(1)

 

Input/output port pin or parallel slave port bit1

RD2/PSP2

bit2

ST/TTL

 

(1)

 

Input/output port pin or parallel slave port bit2

RD3/PSP3

bit3

ST/TTL

 

(1)

 

Input/output port pin or parallel slave port bit3

RD4/PSP4

bit4

ST/TTL

 

(1)

 

Input/output port pin or parallel slave port bit4

RD5/PSP5

bit5

ST/TTL

 

(1)

 

Input/output port pin or parallel slave port bit5

RD6/PSP6

bit6

ST/TTL

 

(1)

 

Input/output port pin or parallel slave port bit6

RD7/PSP7

bit7

ST/TTL

 

(1)

 

Input/output port pin or parallel slave port bit7

Legend:  ST = Schmitt Trigger input, TTL = TTL input 

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.

 

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: 

POR,

BOR

Value on all 

other resets

 

08h

PORTD

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

 

xxxx xxxx

uuuu uuuu

 

88h

TRISD

TRISD7 TRISD6 TRISD5

TRISD4

TRISD3 TRISD2 TRISD1 TRISD0

 

1111 1111

1111 1111

 

89h

TRISE

IBF

OBF

IBOV

PSPMODE

TRISE2 TRISE1 TRISE0

 

0000 -111

0000 -111

 

Legend:

 

x

 

 = unknown, 

 

u

 

 = unchanged, 

 

-

 

 = unimplemented read as '0'. Shaded cells are not used by PORTD.

background image

 

PIC16C64X & PIC16C66X

DS30559A-page  36

Preliminary

©

 1996 Microchip Technology Inc.

5.5

PORTE and TRISE Register 

(PIC16C661 and PIC16C662 only)

PORTE has three pins RE0/RD, RE1/WR, and RE2/

CS, which are individually configurable as inputs or

outputs. These pins have Schmitt Trigger input buffers.

I/O PORTE becomes control inputs for the micropro-

cessor port when bit PSPMODE (TRISE<4>) is set. In

this mode, the user must make sure that the

TRISE<2:0> bits are set (pins are configured as digital

inputs). In this mode the input buffers are TTL.

Figure 5-9 shows the TRISE register, which also con-

trols the parallel slave port operation. 

FIGURE 5-9:

TRISE REGISTER (ADDRESS 89h)

R-0

R-0

R/W-0

R/W-0

U-0

R/W-1

R/W-1

R/W-1

IBF

OBF

IBOV

PSPMODE

TRISE2

TRISE1

TRISE0

R

= Readable bit

W = Writable bit

U

= Unimplemented bit, 

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

IBF: Input Buffer Full Status bit

1 = A word has been received and waiting to be read by the CPU

0 = No word has been received

bit  6:

OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word

0 = The output buffer has been read

bit  5:

IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in software)

0 = No overflow occurred

bit  4:

PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel slave port mode

0 = General purpose I/O mode

bit  3:

Unimplemented: Read as '0'

bit  2:

TRISE2: Direction control bit for pin RE2/CS

1 = Input

0 = Output

bit  1:

TRISE1: Direction control bit for pin RE1/WR

1 = Input

0 = Output

bit  0:

TRISE0: Direction control bit for pin RE0/RD

1 = Input

0 = Output

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  37

PIC16C64X & PIC16C66X

FIGURE 5-10: PORTE BLOCK DIAGRAM (IN I/O PORT MODE)

TABLE 5-9:

PORTE FUNCTIONS

TABLE 5-10:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name

Bit#

Buffer Type

Function

RE0/RD

bit0

ST/TTL

(1)

Input/output port pin or read control input in parallel slave port mode:

RD

1 =  Not a read operation

0 =  Read operation. Reads PORTD register (if chip selected)

RE1/WR

bit1

ST/TTL

(1)

Input/output port pin or write control input in parallel slave port mode:

WR

1 = Not a write operation

0 = Write operation. Writes PORTD register (if chip selected)

RE2/CS

bit2

ST/TTL

(1)

Input/output port pin or chip select control input in parallel slave port 

mode:

CS

1 = Device is not selected

0 = Device is selected

Legend:  ST = Schmitt Trigger input, TTL = TTL input 

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: 

POR,

BOR

Value on all 

other resets

09h

PORTE

RE2

RE1

RE0

---- -xxx

---- -uuu

89h

TRISE

IBF

OBF

IBOV

PSPMODE

TRISE2

TRISE1

TRISE0

0000 -111

0000 -111

Legend:

x

 = unknown, 

u

 = unchanged, 

-

 = unimplemented read as '0'. Shaded cells are not used by PORTE.

Data Bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

Schmitt

Trigger

input

buffer

Q

D

Q

CK

Q

D

Q

CK

EN

Q

D

EN

I/O pin

RD TRIS

Note: I/O pins have protection diodes to V

DD

 and V

SS

.

background image

PIC16C64X & PIC16C66X

DS30559A-page  38

Preliminary

©

 1996 Microchip Technology Inc.

5.6

I/O Programming Considerations

5.6.1

BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a

read followed by a write operation. The 

BCF

 and 

BSF

instructions, for example, read the register into the

CPU, execute the bit operation and write the result

back to the register. Caution must be used when these

instructions are applied to a port with both inputs and

outputs defined. For example, a 

BSF

 operation on bit5

of PORTB will cause all eight bits of PORTB to be read

into the CPU. Then the 

BSF

 operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bi-directional I/O pin

(e.g., bit0) and it is defined as an input at this time, the

input signal present on the pin itself would be read into

the CPU and rewritten to the data latch of this particular

pin, overwriting the previous content. As long as the pin

stays in the input mode, no problem occurs. However,

if bit0 is switched into output mode later on, the content

of the data latch may now be unknown.

Reading the port register reads the values of the port

pins. Writing to the port register writes the value to the

port latch. When using read-modify-write instructions

(e.g., 

BCF, BSF

, etc.) on a port, the value of the port

pins is read, the desired operation is done to this value,

and this value is then written to the port latch. 

Example 

5-4 shows the effect of two sequential

read-modify-write instructions on an I/O port.

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-and”).

The resulting high output currents may damage

the chip.

EXAMPLE 5-4:

READ-MODIFY-WRITE 

INSTRUCTIONS ON AN I/O 

PORT

;Initial PORT settings: PORTB<7:4> Inputs

;                       PORTB<3:0> Outputs

;PORTB<7:6> have external pull-ups and are

;not connected to other circuitry

;

;                    PORT latch  PORT pins

;                    ----------  ---------

  BCF PORTB, 7    ; 01pp pppp    11pp pppp

  BCF PORTB, 6    ; 10pp pppp    11pp pppp

  BCF STATUS, RP1 ;

  BSF STATUS, RP0 ; 

  BCF TRISB, 7    ; 10pp pppp    11pp pppp

  BCF TRISB, 6    ; 10pp pppp    10pp pppp

;

;Note that the user may have expected the 

;pin values to be 00pp ppp. The 2nd BCF

;caused RB7 to be latched as the pin value

;(high).

5.6.2

SUCCESSIVE OPERATIONS ON I/O 

PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle

(Figure 5-11). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should be

such to allow the pin voltage to stabilize (load

dependent) before the next instruction which causes

that file to be read into the CPU is executed. Otherwise,

the previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with an NOP or another

instruction not accessing this I/O port.

FIGURE 5-11: SUCCESSIVE I/O OPERATION

PC

PC + 1

PC + 2

PC + 3

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Instruction

fetched

RB7:RB0

MOVWF PORTB

write to

PORTB

NOP

Port pin

sampled here

NOP

MOVF PORTB,W

Instruction

executed

MOVWF PORTB

write to

PORTB

NOP

MOVF PORTB,W

PC

T

PD

Note:

This example shows a write to PORTB

followed by a read from PORTB.

Note that:

data setup time = (0.25T

CY

 - T

PD

)

where T

CY

 = instruction cycle

T

PD

 = propagation delay

Therefore, at higher clock frequencies,

a write followed by a read may be

problematic.

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  39

PIC16C64X & PIC16C66X

5.7

Parallel Slave Port 

(PIC16C661 and PIC16C662 only)

PORTD operates as an 8-bit wide parallel slave port, or

as a microprocessor port when control bit PSPMODE

(TRISE<4>) is set. In slave mode it is asynchronously

readable and writable by the external world through

RD control input pin (RE0/RD) and WR control input pin

(RE1/WR).

It can directly interface to an 8-bit microprocessor data

bus. The external microprocessor can read or write the

PORTD latch as an 8-bit latch. Setting PSPMODE

enables port pin RE0/RD to be the RD input, RE1/WR

to be the WR input and RE2/CS to be the CS (chip

select) input. For this functionality, the corresponding

data direction bits of the TRISE register (TRISE<2:0>)

must be configured as inputs (set). 

There are actually two 8-bit latches, one for data-out

(from the PIC16/17) and one for data input. The user

writes 8-bit data to PORTD data latch and reads data

from the port pin latch (note that they have the same

address). In this mode, the TRISD register is ignored

since the microprocessor is controlling the direction of

data flow.

Input Buffer Full Status Flag bit IBF (TRISE<7>) is set

if a received word is waiting to be read by the CPU.

Once the PORTD input latch is read, bit IBF is cleared.

IBF is a read only status bit. Output Buffer Full Status

Flag bit OBF (TRISE<6>) is set if a word written to

PORTD latch is waiting to be read by the external bus.

Once the PORTD output latch is read by the micropro-

cessor, bit OBF is cleared. Input Buffer Overflow Status

flag bit IBOV (TRISE<5>) is set if a second write to the

microprocessor port is attempted when the previous

word has not been read by the CPU (the first word is

retained in the buffer).

When not in Parallel Slave Port mode, bits IBF and

OBF are held clear. However, if flag bit IBOV was pre-

viously set, it must be cleared in software.

An interrupt is generated and latched into flag bit

PSPIF (PIR1<7>) when a read or a write operation is

completed. Flag bit PSPIF must be cleared by user

software. The interrupt can be disabled by clearing the

interrupt enable bit PSPIE (PIE1<7>). 

FIGURE 5-12: PORTD AND PORTE AS A 

PARALLEL SLAVE PORT

Data bus

WR

PORT

RD

RDx

Q

D

CK

EN

Q

D

EN

PORT

pin

One bit of PORTD

Set interrupt flag

PSPIF (PIR1<7>)

Read

Chip Select

Write

RD

CS

WR

Note: I/O pins have protection diodes to V

DD

 and V

SS

.

TTL

TTL

TTL

TTL

TABLE 5-11:

REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: 

POR,

BOR

Value on all 

other resets

08h

PORTD

PSP7

PSP6

PSP5

PSP4

PSP3

PSP2

PSP1

PSP0

xxxx xxxx

uuuu uuuu

09h

PORTE

RE2

RE1

RE0

---- -xxx

---- -uuu

89h

TRISE

IBF

OBF

IBOV

PSPMODE

TRISE2

TRISE1

TRISE0

0000 -111

0000 -111

0Ch

PIR1

PSPIF

(1)

CMIF

00-- ----

00-- ----

8Ch

PIE1

PSPIE

(1)

CMIE

00-- ----

00-- ----

Legend:

x

 = unknown, 

u

 = unchanged, 

-

 = unimplemented locations read as '0'. Shaded cells are not used by the PSP.

Note 1:

These bits are reserved on the PIC16C641/642, always maintain these bits clear.

background image

PIC16C64X & PIC16C66X

DS30559A-page  40

Preliminary

©

 1996 Microchip Technology Inc.

NOTES:

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  41

 

PIC16C64X & PIC16C66X

 

6.0

TIMER0 MODULE 

 

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Read and write capability

- Interrupt on overflow from FFh to 00h

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing bit T0CS

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two instruction cycles (Figure 6-2 and

Figure 6-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS. In this

mode, Timer0 will increment either on every rising or

falling edge of pin RA4/T0CKI. The incrementing edge

is determined by the source edge select bit T0SE

(OPTION<4>). Clearing bit T0SE selects the rising

edge. Restrictions on the external clock input are dis-

cussed in detail in Section 6.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. The pres-

caler assignment is controlled in software by control bit

PSA (OPTION<3>). Clearing bit PSA will assign the

prescaler to the Timer0 module. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4, …,

1:256 are selectable. Section 6.3 details the operation

of the prescaler.

 

6.1

Timer0 Interrupt

 

The TMR0 interrupt is generated when the register

(TMR0) overflows from FFh to 00h. This overflow sets

interrupt flag bit T0IF (INTCON<2>). The interrupt can

be masked by clearing enable bit T0IE (INTCON<5>).

Flag bit T0IF must be cleared in software by the Timer0

interrupt service routine before re-enabling this inter-

rupt. The TMR0 interrupt cannot wake the processor

from SLEEP since the timer is shut off during SLEEP.

Figure 6-4 displays the Timer0 interrupt timing.

 

FIGURE 6-1:

TIMER0 BLOCK DIAGRAM    

FIGURE 6-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER    

Note 1:

 Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION<5:0).

2:

The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed diagram).

RA4/T0CKI

T0SE

0

1

1

0

pin

T0CS

F

OSC

/4

Programmable

Prescaler

Sync with

Internal

clocks

TMR0 reg

PSout

(2 cycle delay)

PSout

Data bus

8

Set bit T0IF

on overflow

PSA

PS2, PS1, PS0

3

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

Instruction

Fetch

TMR0

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

T0

T0+1

T0+2

NT0

NT0

NT0

NT0+1

NT0+2

MOVWF TMR0

MOVF TMR0,W

MOVF TMR0,W MOVF TMR0,W

MOVF TMR0,W

MOVF TMR0,W

Write TMR0

executed

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0 + 2

Instruction

Executed

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  42

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

FIGURE 6-3:

TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2    

FIGURE 6-4:

TIMER0 INTERRUPT TIMING    

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

Instruction

Fetch

TMR0

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

T0

NT0+1

MOVWF TMR0

MOVF TMR0,W

MOVF TMR0,W

MOVF TMR0,W

MOVF TMR0,W

MOVF TMR0,W

Write TMR0

executed

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

T0+1

NT0

Instruction

Execute

T0

Q2

Q1

Q3

Q4

Q2

Q1

Q3

Q4

Q2

Q1

Q3

Q4

Q2

Q1

Q3

Q4

Q2

Q1

Q3

Q4

1

1

OSC1

CLKOUT(3)

Timer0

T0IF bit

(INTCON<2>)

FEh

GIE bit

(INTCON<7>)

INSTRUCTION

PC

Instruction

fetched

PC

PC +1

PC +1

0004h

0005h

Instruction

executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Dummy cycle

Dummy cycle

FFh

00h

01h

02h

Note 1: Interrupt flag bit T0IF is sampled here (every Q1).

2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.

3: CLKOUT is available only in RC oscillator mode.

FLOW

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  43

 

PIC16C64X & PIC16C66X

 

6.2

Using Timer0 with External Clock

 

When an external clock input is used for Timer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (T

 

OSC

 

). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.2.1

EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 6-5).

Therefore, it is necessary for T0CKI to be high for at

least 2Tosc (and a small RC delay of 20 ns) and low for

at least 2Tosc (and a small RC delay of 20 ns). Refer to

the electrical specification of the desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type pres-

caler so that the prescaler output is symmetrical. For

the external clock to meet the sampling requirement,

the ripple-counter must be taken into account. There-

fore, it is necessary for T0CKI to have a period of at

least 4Tosc (and a small RC delay of 40 ns) divided by

the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the mini-

mum pulse width requirement of 10 ns. Refer to param-

eters 40, 41, and 42 in the electrical specification of the

desired device.

6.2.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0 mod-

ule is actually incremented. Figure 6-5 shows the delay

from the external clock edge to the timer incrementing.

 

FIGURE 6-5:

TIMER0 TIMING WITH EXTERNAL CLOCK     

Q1

Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4

External Clock Input or

Prescaler output 

(2)

External Clock/Prescaler

Output after sampling

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = 

±

4Tosc max.

2: External clock if no prescaler selected, prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

(3)

(1)

Small pulse

misses sampling

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  44

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

6.3

Prescaler

 

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (Figure 6-6). For simplicity,

this counter is being referred to as “prescaler” through-

out this data sheet. Note that the prescaler may be

used by either the Timer0 module or the Watchdog

Timer, but not both. Thus, a prescaler assignment for

the Timer0 module means that there is no prescaler for

the Watchdog Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., 

 

CLRF 1, MOVWF 1,

BSF 1,x

 

) will clear the prescaler count. When

assigned to Watchdog Timer, a 

 

CLRWDT

 

 instruction will

clear the prescaler count along with the Watchdog

Timer. The prescaler is not readable or writable. 

 

FIGURE 6-6:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER     

RA4/T0CKI

T0SE

pin

M

U

X

CLKOUT (=Fosc/4)

SYNC

2

Cycles

TMR0 reg

8-bit Prescaler

8 - to  - 1MUX

M

U

X

M U X

Watchdog

Timer

PSA

0

1

0

1

WDT

Time-out

PS2:PS0

8

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

PSA

WDT Enable bit

M

U

X

0

1

0

1

Data Bus

Set flag bit T0IF

on Overflow

8

PSA

T0CS

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  45

 

PIC16C64X & PIC16C66X

 

6.3.1

SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the fly” during program

execution. 

 

EXAMPLE 6-1:

CHANGING PRESCALER 

(TIMER0

 

 

WDT)

 

  BCF    STATUS, RP0  ;Bank 0

  CLRF   TMR0         ;Clear TMR0 & Prescaler

  BSF    STATUS, RP0  ;Bank 1

  CLRWDT              ;Clears WDT

  MOVLW  b'xxxx1xxx'  ;Select new prescale

  MOVWF  OPTION_REG   ;value & WDT

  BCF    STATUS, RP0  ;Bank 0 

 

Note:

 

To avoid an unintended device RESET, the

following instruction sequence (shown in

Example 

6-1) must be executed when

changing the prescaler assignment from

Timer0 to the WDT. This precaution must

be followed even if the WDT is disabled.

To change prescaler from the WDT to the Timer0 mod-

ule, use the sequence shown in Example 6-2.

 

EXAMPLE 6-2:

CHANGING PRESCALER 

(WDT

 

 

TIMER0)

 

  CLRWDT               ;Clear WDT and 

                       ;prescaler

  BSF      STATUS, RP0 ;Bank 1

  MOVLW    b'xxxx0xxx' ;Select TMR0, new

                       ;prescale value and

  MOVWF    OPTION_REG  ;clock source

  BCF      STATUS, RP0 ;Bank 0

 

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER0    

 

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on: 

POR,

BOR

Value on all 

other resets

 

01h

TMR0

Timer0 module’s register

 

xxxx xxxx

uuuu uuuu

 

0Bh/8Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

 

0000 000x

0000 000u

 

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

 

1111 1111

1111 1111

 

85h

TRISA

TRISA5

TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

 

--11 1111

--11 1111

 

Legend:

 

x

 

 = unknown, 

 

u

 

 = unchanged, 

 

-

 

 = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  46

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

NOTES:

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  47

 

PIC16C64X & PIC16C66X

 

7.0

COMPARATOR MODULE

 

The comparator module contains two analog

comparators. The inputs to the comparators are

multiplexed with pins RA0 through RA4. The on-chip

Voltage Reference (Section 8.0) can also be an input to

the comparators. 

The CMCON register, shown in Figure 7-1, controls the

comparator input and output multiplexers. A block

diagram of the comparator is shown in Figure 7-2.

 

FIGURE 7-1:

 CMCON REGISTER

 

 

 

(ADDRESS 1Fh)

 

R-0

R-0

U-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

C2OUT

C1OUT

CIS

CM2

CM1

CM0

R =Readable bit

W =Writable bit

U =Unimplemented bit, read 

as ‘0’

- n =Value at POR reset

bit7

bit0

bit  7:

 

C2OUT

 

: Comparator 2 output

1 = C2 V

 

IN

 

+ > C2 V

 

IN

 

0 = C2 V

 

IN

 

+ < C2 V

 

IN

 

bit  6:

 

C1OUT

 

: Comparator 1 output

1 = C1 V

 

IN

 

+ > C1 V

 

IN

 

0 = C1 V

 

IN

 

+ < C1 V

 

IN

 

bit 5-4:

 

Unimplemented: 

 

Read as '0'

bit  3:

 

CIS

 

: Comparator Input Switch

When CM2:CM0: = 

 

001

 

:

Then:

1 = C1 V

 

IN

 

– connects to RA3

0 = C1 V

 

IN

 

– connects to RA0

When CM2:CM0 = 

 

010

 

:

Then:

1 = C1 V

 

IN

 

– connects to RA3

      C2 V

 

IN

 

– connects to RA2

0 = C1 V

 

IN

 

– connects to RA0

      C2 V

 

IN

 

– connects to RA1

bit 2-0:

 

CM2:CM0

 

: Comparator mode

Figure 7-2 shows the comparator modes and CM2:CM0 bit settings.

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  48

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

7.1

Comparator Configuration

 

There are eight modes of operation for the

comparators. The CMCON register is used to select

the mode. Figure 7-2 shows the eight possible modes.

The TRISA register controls the data direction of the

comparator pins for each mode. If the comparator

mode is changed, the comparator output level may not

be valid for the specified mode change delay shown

in Table 12-2. 

 

Note:

 

Comparator interrupts should be disabled

during a comparator mode change other-

wise a false interrupt may occur.

 

FIGURE 7-2:

COMPARATOR I/O OPERATING MODES

C1

RA0/AN0

V

IN

-

V

IN

+

RA3/AN3

Off 

(Read as '0')

Comparators Reset   (POR Default Value)

A

A

CM2:CM0 = 

000

C2

RA1/AN1

V

IN

-

V

IN

+

RA2/AN2

Off 

(Read as '0')

A

A

C1

RA0/AN0

V

IN

-

V

IN

+

RA3/AN3

C1OUT

Two Independent Comparators

A

A

CM2:CM0 = 

100

C2

RA1/AN1

V

IN

-

V

IN

+

RA2/AN2

C2OUT

A

A

C1

RA0/AN0

V

IN

-

V

IN

+

RA3/AN3

C1OUT

Two Common Reference Comparators

A

D

CM2:CM0 = 

011

C2

RA1/AN1

V

IN

-

V

IN

+

RA2/AN2

C2OUT

A

A

C1

RA0/AN0

V

IN

-

V

IN

+

RA3/AN3

Off 

(Read as '0')

One Independent Comparator

D

D

CM2:CM0 = 

101

C2

RA1/AN1

V

IN

-

V

IN

+

RA2/AN2

C2OUT

A

A

C1

RA0/AN0

V

IN

-

V

IN

+

RA3/AN3

Off 

(Read as '0')

Comparators Off

D

D

CM2:CM0 = 

111

C2

RA1/AN1

V

IN

-

V

IN

+

RA2/AN2

Off 

(Read as '0')

D

D

C1

RA0/AN0

V

IN

-

V

IN

+

RA3/AN3

C1OUT

Four Inputs Multiplexed to Two Comparators

A

A

CM2:CM0 = 

010

C2

RA1/AN1

V

IN

-

V

IN

+

RA2/AN2

C2OUT

A

A

From V

REF

 Module

CIS = 0

CIS = 1

CIS = 0

CIS = 1

C1

RA0/AN0

V

IN

-

V

IN

+

RA3/AN3

C1OUT

Two Common Reference Comparators with Outputs

A

D

CM2:CM0 = 

110

C2

RA1/AN1

V

IN

-

V

IN

+

RA2/AN2

C2OUT

A

A

RA4 

Open Drain

C1

RA0/AN0

V

IN

-

V

IN

+

RA3/AN3

C1OUT

Three Inputs Multiplexed to Two Comparators

A

A

CM2:CM0 = 

001

C2

RA1/AN1

V

IN

-

V

IN

+

RA2/AN2

C2OUT

A

A

CIS = 0

CIS = 1

A = Analog Input, port reads zeros always.

D = Digital Input.

CIS (CMCON<3>) is the Comparator Input Switch.

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  49

 

PIC16C64X & PIC16C66X

 

The code example in Example 7-1 depicts the steps

required to configure the comparator module. RA3 and

RA4 are configured as digital outputs. RA0 and RA1

are configured as the V- inputs and RA2 as the V+ input

to both comparators.

 

EXAMPLE 7-1:

INITIALIZING THE 

COMPARATOR MODULE

 

FLAG_REG  EQU 0x20

CLRF      FLAG_REG     ;Init Flag Register

CLRF      PORTA        ;Init PORTA

ANDLW     0xC0         ;Mask Comp bits

IORWF     FLAG_REG,F   ;Bits to Flag_Reg

MOVLW     0x03         ;Init Comp Mode

MOVWF     CMCON        ;CM2:CM0 = 011

BSF       STATUS,RP0   ;Select Bank 1

MOVLW     0x07         ;Init Data direction

MOVWF     TRISA        ;RA<2:0> to inputs

                       ;RA<4:3> to outputs

                       ;TRISA<7:5> read '0'

BCF       STATUS,RP0   ;Select Bank 0

CALL      DELAY_10

 

µ

 

s   ;10 

 

µ

 

s delay

MOVF      CMCON,F      ;Read CMCON to end

                       ;change condition

BCF       PIR1,CMIF    ;Clear Pending Ints

BSF       STATUS,RP0   ;Select Bank 1

BSF       PIE1,CMIE    ;Enable Comp Ints

BCF       STATUS,RP0   ;Select Bank 0

BSF       INTCON,PEIE  ;Enable Periph Ints

BSF       INTCON,GIE   ;Global Int enable

 

7.2

Comparator Operation

 

A single comparator is shown in Figure 7-3 along with

the relationship between the analog input levels and

the digital output. When the analog input at V

 

IN

 

+ is less

than the analog input V

 

IN

 

–, the output of the comparator

is a digital low level. When the analog input at V

 

IN

 

+ is

greater than the analog input V

 

IN

 

–, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 7-3 represents

the uncertainty due to input offsets and response time.

 

7.3

Comparator Reference

 

An external or internal reference signal may be used

depending on the comparator operating mode. The

analog signal that is present at V

 

IN

 

– is compared to the

signal at V

 

IN

 

+, and the digital output of the comparator

is adjusted accordingly (Figure 7-3).

 

FIGURE 7-3:

SINGLE COMPARATOR

 

7.3.1

 EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the

comparator module can be configured to have the com-

parators operate from the same or different reference

sources. However, threshold detector applications may

require the same reference. The reference signal must

be between V

 

SS

 

 and V

 

DD

 

, and can be applied to either

pin of the comparator(s).

7.3.2

 INTERNAL REFERENCE SIGNAL

The comparator module also allows the selection of an

internally generated voltage reference for the

comparators. Section 8.0, contains a detailed descrip-

tion of the Voltage Reference Module that provides this

signal. The internal reference signal is used when the

comparators are in mode CM2:CM0 

 

010

 

(Figure 7-2). In this mode, the internal voltage refer-

ence is applied to the V

 

IN

 

+ pin of both comparators.

V

IN

-

V

IN

+

Output

V

IN

-

V

IN

+

Output

background image

PIC16C64X & PIC16C66X

DS30559A-page  50

Preliminary

©

 1996 Microchip Technology Inc.

7.4

Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is guaranteed to have a valid level.

If the internal reference is changed, the maximum delay

of the internal voltage reference must be considered

when using the comparator outputs. Otherwise, the

maximum delay of the comparators should be used

(Table 12-2 and Table 12-3).

7.5

Comparator Outputs

The comparator outputs are read through the CMCON

register. These bits are read only. The comparator

outputs may also be directly output to the RA3 and RA4

I/O pins. When CM2:CM0 = 

110

, multiplexors in the

output path of the RA3 and RA4 pins will switch and the

output of each pin will be the unsynchronized output of

the comparator. The uncertainty of each of the

comparators is related to the input offset voltage and

the response time given in the specifications.

Figure 7-4 shows the comparator output block diagram.

The TRISA bits will still function as an output enable/

disable for the RA3 and RA4 pins while in this mode.

Note 1: When reading the PORTA register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert an analog input according to the

Schmitt Trigger input specification.

Note 2: Analog levels on any pin that is defined as

a digital input may cause the input buffer

to consume more current than is speci-

fied.

FIGURE 7-4:

COMPARATOR OUTPUT BLOCK DIAGRAM

D

Q

EN

To RA3 or RA4 pin

RD CMCON

Set CMIF bit

MULTIPLEX

D

Q

EN

CL

Port Pins

RD CMCON

NRESET

From other Comparator

To Data Bus

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  51

PIC16C64X & PIC16C66X

7.6

Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator. User

software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that has occurred. The

CMIF bit (PIR1<6>), is the comparator interrupt flag

and must be cleared in user software. 

To enable the Comparator interrupt the following bits

must be set:

• CMIE (PIE1<6>)

• PEIE (INTCON<6>)

• GIE (INTCON<7>)

The user, in the interrupt service routine, can clear the

interrupt in the following manner:

a)

Any read or write of CMCON. This will end the

mismatch condition.

b)

Clear flag bit CMIF.

A mismatch condition will continue to set flag bit CMIF.

Reading CMCON will end the mismatch condition, and

allow flag bit CMIF to be cleared.

7.7

Comparator Operation During SLEEP

When a comparator is active and the device is placed

in SLEEP mode, the comparator remains active and

the interrupt is functional if enabled. This interrupt will

wake up the device from SLEEP mode when enabled.

While the comparator is powered up, higher sleep

currents than shown in the power-down current

specification will occur. Each comparator that is

operational will consume additional current as shown in

the comparator specifications. To minimize power

consumption while in SLEEP mode, turn off the

comparators, CM2:CM0 = 

111

, before entering sleep.

If the device wakes up from sleep, the contents of the

CMCON register are not affected.

7.8

Effects of a RESET

A device reset forces the CMCON register to its reset

state. This forces the comparator module to be in the

comparator reset mode, CM2:CM0 

000

. This

ensures that all potential inputs are analog inputs.

Device current is minimized when analog inputs are

present at reset time. The comparators will be powered

down during the reset interval. 

7.9

Analog Input Connection 

Considerations

A simplified circuit for an analog input is shown in

Figure 7-5. Since the analog pins are connected to a

digital output, they have reverse biased diodes to V

DD

and V

SS

. The analog input therefore, must be between

V

SS

 and V

DD

. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur. A

maximum source impedance of 10 

k

 is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

FIGURE 7-5:

ANALOG INPUT MODEL

V

A

R

S

A

IN

C

PIN

5 pF

V

DD

V

T

 = 0.6V

V

T

 = 0.6V

R

C

 < 10k

I

LEAKAGE

±

500 nA

V

SS

Legend C

PIN

= Input Capacitance

V

T

= Threshold Voltage

I

LEAKAGE

= Leakage Current at the pin due to various junctions

R

IC

= Interconnect Resistance

R

S

= Source Impedance

V

A

= Analog Voltage

background image

PIC16C64X & PIC16C66X

DS30559A-page  52

Preliminary

©

 1996 Microchip Technology Inc.

TABLE 7-1:

REGISTERS ASSOCIATED WITH THE COMPARATOR MODULE

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

resets

1Fh

CMCON

C2OUT

C1OUT

CIS

CM2

CM1

CM0

00-- 0000

00-- 0000

9Fh

VRCON

VREN

VROE

VRR

VR3

VR2

VR1

VR0

000- 0000

000- 0000

0Bh/8Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

PSPIF

(1)

CMIF

00-- ----

00-- ----

8Ch

PIE1

PSPIE

(1)

CMIE

00-- ----

00-- ----

85h

TRISA

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

--11 1111

--11 1111

Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  53

 

PIC16C64X & PIC16C66X

 

8.0

VOLTAGE REFERENCE 

MODULE

 

The Voltage Reference is a 16-tap resistor ladder

network that provides a selectable voltage reference.

The resistor ladder is segmented to provide two ranges

of V

 

REF

 

 values and has a power-down function to

conserve power when the reference module is not

being used.   

The VRCON register, shown in Figure 8-1, controls the

operation of the Voltage Reference Module. The block

diagram is given in Figure 8-2.

 

FIGURE 8-1:

 VRCON REGISTER (ADDRESS 9Fh)

FIGURE 8-2:

VOLTAGE REFERENCE BLOCK DIAGRAM

 

R/W-0

R/W-0

R/W-0

U-0

R/W-0

R/W-0

R/W-0

R/W-0

VREN

VROE

VRR

VR3

VR2

VR1

VR0

R =Readable bit

W =Writable bit

U =Unimplemented bit, read 

as ‘0’

- n =Value at POR reset

bit7

bit0

bit  7:

 

VREN:

 

 V

 

REF

 

 Enable

1 = V

 

REF

 

 circuit powered up 

0 = V

 

REF

 

 circuit powered down, no I

 

DD

 

 drain

bit  6:

 

VROE:

 

 V

 

REF

 

 Output Enable

1 = V

 

REF

 

 is output on RA2 pin

0 = V

 

REF

 

 is disconnected from RA2 pin

bit  5:

 

VRR:

 

 V

 

REF

 

 Range selection

1 = Low Range

0 = High Range

bit 4:

 

Unimplemented: 

 

Read as '0'

bit  3-0:

 

VR3:VR0

 

: V

 

REF

 

 value selection 0 

 

 

 VR3:VR0 

 

 

 15

When: VRR = 1

Then: V

 

REF

 

 = (VR3:VR0/ 24) • V

 

DD

 

When: VRR = 0

Then: V

 

REF

 

 = 1/4 • V

 

DD

 

 + (VR3:VR0/ 32) • V

 

DD

Note:

R is defined in Table 12-3.

VRR

8R

VR3

VR0

(From VRCON<3:0>)

16-1 Analog Mux

8R

R

R

R

R

VREN

V

REF

16 Stages

VR2

VR1

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  54

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

8.1

Configuring the Voltage Reference

 

The Voltage Reference Module can output 16 distinct

voltage levels for each range.

The equations used to calculate the output of the

Voltage Reference are as follows:

If VRR = 1

Then V

 

REF

 

 = (VR3:VR0/24) • V

 

DD

 

If VRR = 0

Then V

 

REF

 

 = (V

 

DD

 

 • 1/4) + (VR3:VR0/32) • V

 

DD

 

The settling time of the Voltage Reference must be

considered when changing the V

 

REF

 

 output

(Table 12-2). Example 8-1 shows an example of how to

configure the Voltage Reference for an output voltage

of 1.25V with V

 

DD

 

 = 5.0V.

 

EXAMPLE 8-1:

VOLTAGE REFERENCE 

CONFIGURATION 

 

MOVLW   0x02         ; 4 inputs muxed

MOVWF   CMCON        ; to 2 comparators

BSF     STATUS,RP0   ; Select Bank 1

MOVLW   0x07         ; RA3:RA0 to outputs

MOVWF   TRISA        ;

MOVLW   0xA6         ; enable Vref low

MOVWF   VRCON        ; range, VR3:VR0 = 6

BCF     STATUS,RP0   ; Select Bank 0

CALL    DELAY_10

 

µ

 

s     ; 10 

 

µ

 

s delay

 

8.2

Voltage Reference Accuracy/Error

 

The full range of V

 

SS

 

 to V

 

DD

 

 cannot be realized due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 8-2) keep V

 

REF

 

 from approaching V

 

SS

 

 or V

 

DD

 

.

The Voltage Reference is V

 

DD

 

 derived and therefore,

the V

 

REF

 

 output changes with fluctuations in V

 

DD

 

. The

absolute accuracy of the Voltage Reference can be

found in Table 12-3. 

 

8.3

Operation During Sleep

 

When the device wakes up from sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the VRCON register are not affected. To minimize

current consumption in SLEEP mode, the Voltage

Reference Module should be disabled.

 

8.4

Effects of a Reset

 

A device reset disables the Voltage Reference by clear-

ing bit VREN (VRCON<7>). This reset also

disconnects the reference from the RA2 pin by clearing

bit VROE (VRCON<6>) and selects the high voltage

range by clearing bit VRR (VRCON<5>). The V

 

REF

 

value select bits, VRCON<3:0>, are also cleared.

 

8.5

Connection Considerations

 

The Voltage Reference Module operates independently

of the comparator module. The output of the reference

generator may be connected to the RA2 pin if the

TRISA<2> bit is set and bit VROE is set. Enabling the

Voltage Reference output onto the RA2 pin with an

input signal present will increase current consumption.

Connecting RA2 as a digital output with V

 

REF

 

 enabled

will also increase current consumption.

The RA2 pin can be used as a simple D/A output with

limited drive capability. Due to the limited drive

capability, a buffer must be used in conjunction with the

Voltage Reference output for external connections to

V

 

REF

 

. Figure 

8-3 shows an example buffering

technique.

 

FIGURE 8-3:

VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 8-1:

REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

 

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value On

POR,

BOR

Value on

all other

resets

 

9Fh

VRCON

VREN

VROE

VRR

VR3

VR2

VR1

VR0

 

000- 0000

000- 0000

 

1Fh

CMCON

C2OUT

C1OUT

CIS

CM2

CM1

CM0

 

00-- 0000

00-- 0000

 

85h

TRISA

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

 

--11 1111

--11 1111

Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.

V

REF

 output

Voltage

Reference

Output

Impedance

R

(1)

Pin RA2

V

REF

Module

PIC16C662

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  55

 

PIC16C64X & PIC16C66X

 

9.0

SPECIAL FEATURES OF THE 

CPU

 

What sets apart a microcontroller from other

processors are special circuits to deal with the needs of

real-time applications. The PIC16C64X & PIC16C66X

families have a host of such features intended to max-

imize system reliability, minimize cost through elimina-

tion of external components, provide power saving

operating modes and offer code protection. 

These are:

1.

Oscillator selection

2.

Resets

Power-on Reset (POR)

Power-up Timer (PWRT)

Oscillator Start-up Timer (OST)

Brown-out Reset (BOR)

Parity Error Reset (PER)

3.

Interrupts

4.

Watchdog Timer (WDT)

5.

SLEEP

6.

Code protection

7.

ID Locations

8.

In-circuit serial programming

The PIC16C64X & PIC16C66X has a Watchdog Timer

which is enabled by a configuration bit (WDTE). It runs

off its own RC oscillator for added reliability. There are

two timers that offer necessary delays on power-up.

One is the Oscillator Start-up Timer (OST), intended to

keep the chip in reset until the crystal oscillator is sta-

ble. The other is the Power-up Timer (PWRT), which

provides a fixed delay of 72 ms (nominal) on power-up

only, designed to keep the part in reset while the power

supply stabilizes. Circuitry has been provided for

checking program memory parity with a reset when an

error is indicated. There is also circuitry to reset the

device if a brown-out occurs which provides at least a

72 ms reset. With these three functions on-chip, most

applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current

power-down mode. The user can wake-up from SLEEP

through external reset, Watchdog Timer wake-up or

through an interrupt. Several oscillator options are also

made available to allow the part to fit the application.

The RC oscillator option saves system cost while the

LP crystal option saves power. A set of configuration

bits are used to select various options.

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  56

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

9.1

Configuration Bits

 

The configuration bits can be programmed (read as '0')

or left unprogrammed (read as '1') to select various

device configurations. These bits are mapped in

program memory location 2007h.

The  user  will  note  that  address  2007h  is  beyond 

the user program memory space. In fact, it belongs

to  the  special   test/configuration   memory   space

(2000h–3FFFh), which can be accessed only during

programming.

 

FIGURE 9-1:

CONFIGURATION WORD

 

CP1

CP0

CP1

CP0

CP1

CP0

MPEEN

BODEN CP1

CP0

PWRTE

WDTE

FOSC1 FOSC0

CONFIG

Address

REGISTER:

2007h

bit13

bit0

bit 13-8

 

CP1:CP0: 

 

Code protection bits

 

(2)

 

      5-4:

 

11

 

 = Code protection off

 

10

 

 = Upper half of program memory code protected

 

01

 

 = Upper 3/4th of program memory code protected

 

00

 

 = All memory is code protected

bit  7:

 

MPEEN

 

: Memory Parity Error Enable

1 = Memory Parity Checking is enabled

0 = Memory Parity Checking is disabled

bit  6:

 

BODEN

 

: Brown-out Reset Enable bit 

 

(1)

 

1 = BOR enabled

0 = BOR disabled

bit  3:

 

PWRTE

 

: Power-up Timer Enable bit 

 

(1)

 

1 = PWRT disabled

0 = PWRT enabled

bit  2:

 

WDTE

 

: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit  1-0:

 

FOSC1:FOSC0

 

: Oscillator Selection bits

 

11

 

 = RC oscillator

 

10

 

 = HS oscillator

 

01

 

 = XT oscillator

 

00

 

 = LP oscillator

Note

1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the 

Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  57

 

PIC16C64X & PIC16C66X

 

9.2

Oscillator Configurations

 

9.2.1

 OSCILLATOR TYPES

The PIC16CXXX can be operated in four different

oscillator modes. The user can program two

configuration bits (FOSC1 and FOSC0) to select one of

these four modes:

• LP

Low Power Crystal

• XT

Crystal/Resonator

• HS

High Speed Crystal/Resonator

• RC

Resistor/Capacitor

9.2.2

CRYSTAL OSCILLATOR / CERAMIC 

RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1 and OSC2 pins to establish

oscillation (Figure 

9-2). The PIC16CXXX oscillator

design requires the use of a parallel cut crystal. Use of

a series cut crystal may give a frequency out of the

crystal manufacturers specifications. When in XT, LP or

HS modes, the device can have an external clock

source to drive the OSC1 pin (Figure 9-3).

 

FIGURE 9-2:

CRYSTAL OPERATION 

(OR CERAMIC RESONATOR) 

(HS, XT OR LP OSC 

CONFIGURATION)

FIGURE 9-3:

EXTERNAL CLOCK INPUT 

OPERATION (HS, XT OR LP 

OSC CONFIGURATION)

See Table 9-1 or Table 9-2 for recommended val-

ues of C1 and C2.

Note:

A series resistor may be required for

AT strip cut crystals.

C1

C2

XTAL

OSC2

RS

 

OSC1

RF

SLEEP

To internal logic

PIC16CXXX

see Note

clock from

ext. system

PIC16CXXX

OSC1

OSC2

Open

 

TABLE 9-1:

CAPACITOR SELECTION 

FOR CERAMIC RESONATORS 

(PRELIMINARY)

TABLE 9-2:

CAPACITOR SELECTION 

FOR CRYSTAL OSCILLATOR 

(PRELIMINARY) 

 

Ranges tested:

Mode

Freq

OSC1

 

XT

455 kHz

2.0 MHz

4.0 MHz

22 - 100 pF

15 - 68 pF

15 - 68 pF

HS

8.0 MHz

16.0 MHz

10 - 68 pF

10 - 22 pF

 

Note: Recommended values of C1 and C2 are identical

to the ranges tested table.

Higher capacitance increases the stability of the

oscillator but also increases the start-up time.

These values are for design guidance only. Since

each resonator has its own characteristics, the

user should consult the resonator manufacturer for

appropriate values of external components. 

 

Resonators used:

 

455 kHz

Panasonic EFO-A455K04B

 

±

 

0.3%

2.0 MHz

Murata Erie CSA2.00MG

 

±

 

0.5%

4.0 MHz

Murata Erie CSA4.00MG

 

±

 

0.5%

8.0 MHz

Murata Erie CSA8.00MT

 

±

 

0.5%

16.0 MHz

Murata Erie CSA16.00MX

 

±

 

0.5%

 

All resonators used did not have built-in capacitors.

 

Mode

 Freq

OSC1 

OSC2

 

LP

32 kHz

200 kHz

68 - 100 pF

15 - 30 pF

68 - 100 pF

15 - 30 pF

XT

100 kHz

2 MHz

4 MHz

68 - 150 pF

15 - 30 pF

15 - 30 pF

150 - 200 pF

15 - 30 pF

15 - 30 pF

HS

8 MHz

10 MHz

20 MHz

15 - 30 pF

15 - 30 pF

15 - 30 pF

15 - 30 pF

15 - 30 pF

15 - 30 pF

 

Higher capacitance increases the stability of the 

oscillator but also increases the start-up time. 

These values are for design guidance only. Rs may 

be required in HS mode as well as XT mode to 

avoid overdriving crystals with low drive level spec-

ification. Since each crystal has its own 

characteristics, the user should consult the crystal 

manufacturer for appropriate values of external 

components.

 

Crystals used: 

 

32.768 kHz

Epson C-001R32.768K-A

 

±

 

 20 PPM

100 kHz

Epson C-2 100.00 KC-P

 

±

 

 20 PPM

200 kHz

STD XTL 200.000 kHz

 

±

 

 20 PPM

2.0 MHz

ECS ECS-20-S-2

 

±

 

 50 PPM

4.0 MHz

ECS ECS-40-S-4

 

±

 

 50 PPM

10.0 MHz

ECS ECS-100-S-4

 

±

 

 50 PPM

20.0 MHz

ECS ECS-200-S-4

 

±

 

 50 PPM

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  58

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

9.2.3

EXTERNAL CRYSTAL OSCILLATOR 

CIRCUIT

Either a prepackaged oscillator can be used or a simple

oscillator circuit with TTL gates can be built. Prepack-

aged oscillators provide a wide operating range and

better stability. A well-designed crystal oscillator will

provide good performance with TTL gates. Two types

of crystal oscillator circuits can be used: one with series

resonance, or one with parallel resonance.

Figure 9-4 shows implementation of a parallel resonant

oscillator circuit. The circuit is designed to use the fun-

damental frequency of the crystal. The 74AS04 inverter

performs the 180-degree phase shift that a parallel

oscillator requires. The 4.7 k

 

 

 resistor provides the

negative feedback for stability. The 10 k

 

 

 potentiome-

ter biases the 74AS04 in the linear region. This could

be used for external oscillator designs.

 

FIGURE 9-4:

EXTERNAL PARALLEL 

RESONANT CRYSTAL 

OSCILLATOR CIRCUIT

 

Figure 9-5 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental fre-

quency of the crystal. The inverter performs a

180-degree phase shift in a series resonant oscillator

circuit. The 330 k

 

 

 resistors provide the negative feed-

back to bias the inverters in their linear region.

 

FIGURE 9-5:

EXTERNAL SERIES 

RESONANT CRYSTAL 

OSCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k

4.7k

10k

74AS04

XTAL

10k

74AS04

CLKIN

To Other

Devices

PIC16CXXX

330 k

74AS04

74AS04

PIC16CXXX

CLKIN

To Other

Devices

XTAL

330 k

 

74AS04

0.1 

µ

F

 

9.2.4

RC OSCILLATOR

For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the resis-

tor (Rext) and capacitor (Cext) values, and the operat-

ing temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

Cext values. The user also needs to take into account

variation due to tolerance of external R and C compo-

nents used. Figure 9-6 shows how the R/C combina-

tion is connected to the PIC16CXXX. For Rext values

below 2.2 k

 

 

, the oscillator operation may become

unstable, or stop completely. For very high Rext values

(e.g. 1 M

 

 

), the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend to keep

Rext between 3 k

 

 

 and 100 k

 

 

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or pack-

age lead frame capacitance.

See characterization data for desired device for RC fre-

quency variation from part to part due to normal pro-

cess variation. The variation is larger for larger R (since

leakage current variation will affect RC frequency more

for large R) and for smaller C (since variation of input

capacitance will affect RC frequency more).

See characterization data for desired device for varia-

tion of oscillator frequency due to V

 

DD

 

 for given Rext/

Cext values as well as frequency variation due to oper-

ating temperature for given R, C, and V

 

DD

 

 values. 

The oscillator frequency, divided by 4, is available on

the OSC2/CLKOUT pin, and can be used for test pur-

poses or to synchronize other logic (see Figure 3-3 for

waveform).

 

FIGURE 9-6:

RC OSCILLATOR MODE

OSC2/CLKOUT

Cext

V

DD

Rext

V

SS

PIC16CXXX

OSC1

Fosc/4

Internal

clock

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  59

 

PIC16C64X & PIC16C66X

 

9.3

Reset

 

The PIC16CXXX differentiates between various kinds

of reset: 

a)

Power-on reset (POR) 

b)

MCLR reset during normal operation

c)

MCLR reset during SLEEP 

d)

WDT reset (normal operation)

e)

Brown-out Reset (BOR)

f)

Parity Error Reset (PER)

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any

other reset. Most other registers are reset to a “reset

state” on Power-on reset, MCLR, WDT reset,

Brown-out Reset, Parity Error Reset, and on MCLR

reset during SLEEP. They are not affected by a WDT

wake-up, since this is viewed as the resumption of nor-

mal operation. TO and PD bits are set or cleared differ-

ently in different reset situations as indicated in

Table 9-4. These bits are used in software to determine

the nature of the reset. See Table 9-6 for a full descrip-

tion of reset states of all registers.

A simplified block diagram of the on-chip reset circuit is

shown in Figure 9-7.

The MCLR reset path has a noise filter to detect and

ignore small pulses. See Table 12-6 for pulse width

specification.

 

FIGURE 9-7:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

S

R

Q

External

Reset

MCLR/

V

DD

OSC1/

WDT

Module

V

DD

 rise

detect

OST/PWRT

On-chip

(1)

 

RC OSC 

WDT Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Enable OST

Enable PWRT

SLEEP

See Table 9-3 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

Brown-out

Reset

BODEN

CLKIN

Pin

V

PP

 Pin

10-bit Ripple-counter

Program

Memory

Parity

MPEEN

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  60

 

Preliminary

 

©

 

 1996 Microchip Technology Inc.

 

9.4

Power-on Reset (POR), Power-up 

Timer (PWRT), Oscillator Start-up 

Timer (OST), Brown-out Reset (BOR), 

and Parity Error Reset (PER)

 

9.4.1

POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when

V

 

DD

 

 rise is detected (in the range of 1.6V to 1.8V). To

take advantage of the POR, just tie the MCLR pin

directly (or through a resistor) to V

 

DD

 

. This will

eliminate external RC components usually needed to

create a Power-on Reset. A maximum rise time for V

 

DD

 

is required. See Electrical Specifications for details.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature, etc.) must be met to ensure

operation. If these conditions are not met, the device

must be held in reset until the operating conditions are

met.

For additional information, refer to Application Note

AN607 “

 

Power-up Trouble Shooting.

 

9.4.2

POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 72 ms (nominal)

delay on power-up only, from POR or BOR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in reset as long as PWRT is active. The

PWRT delay allows V

 

DD

 

 to rise to an acceptable level.

A configuration bit, PWRTE can disable (if set) or

enable (if cleared or programmed) the Power-up Timer.

The Power-up Timer should always be enabled when

Brown-out Reset is enabled.

The power-up time delay will vary from chip to chip due

to V

 

DD

 

, temperature, and process variations. See DC

parameters for details.

9.4.3

OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-Up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP, and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

9.4.4

BROWN-OUT RESET (BOR)

PIC16C64X & PIC16C66X devices have on-chip

Brown-out Reset circuitry. A configuration bit, BODEN,

can disable (if clear/programmed) or enable (if set) the

Brown-out Reset circuitry. If V

 

DD

 

 falls below 4.0V

(Parameter D005 in ES section) for greater than

parameter 35 in Table 12-6, the brown-out situation will

reset the chip. A reset is not guaranteed to occur if V

 

DD

 

falls below 4.0V for less than parameter 35. The chip

will remain in Brown-out Reset until V

 

DD

 

 rises above

BV

 

DD

 

. The Power-up Timer will now be invoked and will

keep the chip in reset an additional 72 ms. If V

 

DD

 

 drops

below BV

 

DD

 

 while the Power-up Timer is running, the

chip will go back into a Brown-out Reset and the

Power-up Timer will be initialized. Once V

 

DD

 

 rises

above BV

 

DD

 

, the Power-up Timer will execute a 72 ms

time delay. The Power-up Timer should always be

enabled when Brown-out Reset is enabled. Figure 9-8

shows typical Brown-out situations.

 

FIGURE 9-8:

BROWN-OUT SITUATIONS 

72 ms

BV

DD

 Max.

BV

DD

 Min.

V

DD

Internal

Reset

BV

DD

 Max.

BV

DD

 Min.

V

DD

Internal

Reset

72 ms

<72 ms

72 ms

BV

DD

 Max.

BV

DD

 Min.

V

DD

Internal

Reset

background image

 

©

 

 1996 Microchip Technology Inc.

 

Preliminary

 

DS30559A-page  61

 

PIC16C64X & PIC16C66X

 

9.4.5

PARITY ERROR RESET (PER)

PIC16C64X & PIC16C66X devices have on-chip parity

bits that can be used to verify the contents of program

memory. Parity bits may be useful in applications in

order to increase overall reliability of a system.

There are two parity bits for each word of Program

Memory. The parity bits are computed on alternating

bits of the program word. One computation is per-

formed using even parity, the other using odd parity. As

a program executes, the parity is verified. The even

parity bit is XOR’d with the even bits in the program

memory word. The odd parity bit is negated and XOR’d

with the odd bits in the program memory word. When

an error is detected, a reset is generated and the PER

flag bit in the PCON register is set. This indication can

allow software to act on a failure. However, there is no

indication of the program memory location of the failure

of the Program Memory. This flag can only be cleared

in software or by a POR.

The parity array is user selectable during programming.

Bit7 of the configuration word located at address 2007h

can be programmed (read as '0') to disable parity

checking. If left unprogrammed (read as '1'), parity

checking is enabled.

9.4.6

TIME-OUT SEQUENCE

On power-up, the time-out sequence is as follows: First

PWRT time-out is invoked after POR has expired. Then

the OST is activated. The total time-out will vary based

on oscillator configuration and PWRTE bit status. For

example, in RC mode with the PWRTE bit set (PWRT

disabled), there will be no time-out at all. Figure 9-9,

Figure 

9-10 and Figure 

9-11 depict time-out

sequences.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high will begin execution immediately

(Figure 9-10). This is useful for testing purposes or to

synchronize more than one device operating in parallel.

Table 9-5 shows the reset conditions for some special

registers, while Table 9-6 shows the reset conditions

for all the registers. 

9.4.7

POWER CONTROL/STATUS REGISTER 

(PCON)

The power control/status register, PCON (address

8Eh) has four bits. See Figure 4-10 for register.

Bit0 is BOR (Brown-out Reset). BOR is unknown on a

Power-on-reset. It must initially be set by the user and

checked on subsequent resets to see if BOR = '0'

indicating that a Brown-out Reset has occurred. The

BOR status bit is a “don’t care” bit and is not necessar-

ily predictable if the brown-out circuit is disabled (by

clearing the BODEN bit in the Configuration word).

Bit1 is POR (Power-on Reset). It is cleared on a

Power-on Reset and is unaffected otherwise. The user

set this bit following a Power-on Reset. On subsequent

resets if POR is ‘0’, it will indicate that a Power-on

Reset must have occurred.

Bit2 is PER (Parity Error Reset). It is cleared on a Parity

Error Reset and must be set by user software. It will

also be set on a Power-on Reset.

Bit7 is MPEEN (Memory Parity Error Enable). This bit

reflects the status of the MPEEN bit in configuration

word. It is unaffected by any reset or interrupt.

 

TABLE 9-3:

TIME-OUT IN VARIOUS SITUATIONS

 

Oscillator Configuration

Power-up

Brown-out Reset

Wake-up 

from SLEEP

PWRTE = 0

PWRTE = 1

 

XT, HS, LP

72 ms + 1024 T

 

OSC

 

1024 T

 

OSC

 

72 ms + 1024 T

 

OSC

 

1024 T

 

OSC

 

RC

72 ms

72 ms

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  62

 

Preliminary

©

 1996 Microchip Technology Inc.

TABLE 9-4:

STATUS BITS AND THEIR SIGNIFICANCE

TABLE 9-5:

INITIALIZATION CONDITION FOR SPECIAL REGISTERS

PER

POR

BOR

TO

PD

1

0

x

1

1

Power-on Reset

x

0

x

0

x

Illegal, TO is set on POR

x

0

x

x

0

Illegal, PD is set on POR

1

1

0

1

1

Brown-out Reset

1

1

1

0

1

WDT Reset

1

1

1

0

0

WDT Wake-up

1

1

1

u

u

MCLR reset during normal operation

1

1

1

1

0

MCLR reset during SLEEP

0

1

1

1

1

Parity Error Reset

0

0

x

x

x

Illegal, PER is set on POR

0

x

0

x

x

Illegal, PER is set on BOR

Condition

Program

Counter

STATUS

Register

PCON

Register

Power-on Reset

000h

0001 1xxx

u--- -10x

MCLR reset during normal operation

000h

000u uuuu

u--- -uuu

MCLR reset during SLEEP

000h

0001 0uuu

u--- -uuu

WDT reset

000h

0000 1uuu

u--- -uuu

WDT Wake-up

PC + 1

uuu0 0uuu

u--- -uuu

Brown-out Reset

000h

0001 1uuu

u--- -uu0

Parity Error Reset

000h

0001 1uuu

1--- -0uu

Interrupt Wake-up from SLEEP

PC + 1

(1)

uuu1 0uuu

u--- -uuu

Legend:

u

 = unchanged,   

x

 = unknown, 

-

 = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the inter-

rupt vector (0004h) after execution of PC+1.

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  63

PIC16C64X & PIC16C66X

TABLE 9-6:

INITIALIZATION CONDITION FOR REGISTERS

Register

Address

Power-on Reset

Brown-out Reset

Parity Error Reset

MCLR Reset during:

- normal   operation

- SLEEP or

WDT Reset

Wake up from SLEEP 

through: 

- interrupt

- WDT time-out

W

-

xxxx xxxx

uuuu uuuu

uuuu uuuu

INDF

00h

-

-

-

TMR0

01h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PCL

02h

0000 0000

0000 0000

PC + 1

(2)

STATUS

03h

0001 1xxx

000q quuu

(3)

uuuq quuu

(3)

FSR

04h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PORTA

05h

--xx 0000

--xu 0000

--uu uuuu

PORTB

06h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PORTC

07h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PORTD

(4)

08h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PORTE

(4)

09h

---- -xxx

---- -uuu

---- -uuu

CMCON

1Fh

00-- 0000

00-- 0000

uu-- uuuu

PCLATH

0Ah

---0 0000

---0 0000

---u uuuu

INTCON

0Bh

0000 000x

0000 000u

uuuu uuuu

(1)

PIR1

0Ch

00-- ----

00-- ----

uu-- ----

(1)

OPTION

81h

1111 1111

1111 1111

uuuu uuuu

TRISA

85h

--11 1111

--11 1111

--uu uuuu

TRISB

86h

1111 1111

1111 1111

uuuu uuuu

TRISC

87h

1111 1111

1111 1111

uuuu uuuu

TRISD

(4)

88h

1111 1111

1111 1111

uuuu uuuu

TRISE

(4)

89h

0000 -111

0000 -111

uuuu -uuu

PIE1

8Ch

00-- ----

00-- ----

uu-- ----

PCON

8Eh

u--- -qqq

u--- -uuu

u--- -uuu

VRCON

9Fh

000- 0000

000- 0000

uuu- uuuu

Legend: 

u

 = unchanged, 

x

 = unknown, 

-

 = unimplemented bit, reads as ‘0’,

q

 = value depends on condition.

Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt 

vector (0004h).

3: See Table 9-5 for reset value for specific condition.

4: These registers are associated with the Parallel Slave Port and are not implemented on the PIC16C641/642.

background image

PIC16C64X & PIC16C66X

DS30559A-page  64

Preliminary

©

 1996 Microchip Technology Inc.

FIGURE 9-9:

TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V

DD

): CASE 1

FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V

DD

): CASE 2

FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V

DD

)

T

PWRT

T

OST

V

DD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

V

DD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

T

PWRT

T

OST

T

PWRT

T

OST

V

DD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  65

PIC16C64X & PIC16C66X

FIGURE 9-12: EXTERNAL POWER-ON 

RESET CIRCUIT (FOR SLOW 

V

DD

 POWER-UP)

FIGURE 9-13: EXTERNAL BROWN-OUT 

PROTECTION CIRCUIT 1

Note 1: External power-on reset circuit is required 

only if V

DD

 power-up slope is too slow. 

The diode D helps discharge the capaci-

tor quickly when V

DD

 powers down.

2: R < 40 k

 is recommended to make sure 

that voltage drop across R does not vio-

late the device’s electrical specification.

3: R1 = 100

 to 1 k

 will limit any current 

flowing into MCLR from external capaci-

tor C in the event of MCLR/V

PP

 pin 

breakdown due to Electrostatic Dis-

charge (ESD) or Electrical Overstress 

(EOS).

C

R1

R

D

V

DD

MCLR

PIC16CXXX

V

DD

Note 1: This circuit will activate reset when V

DD

 

goes below (Vz + 0.7V) where 

Vz = Zener voltage.

2: Internal Brown-out Reset circuitry 

should be disabled when using this cir-

cuit.

3: Resistors should be adjusted for the 

characteristics of the transistor.

V

DD

33k

10k

40k

V

DD

MCLR

PIC16CXXX

FIGURE 9-14: EXTERNAL BROWN-OUT 

PROTECTION CIRCUIT 2

Note 1: This brown-out circuit is less expensive, 

albeit less accurate. Transistor Q1 turns 

off when V

DD

 is below a certain level 

such that:

2: Internal Brown-out Reset circuitry 

should be disabled when using this cir-

cuit.

3: Resistors should be adjusted for the 

characteristics of the transistor.

V

DD

 •

R1

R1 + R2

=  0.7 V

V

DD

R2

40k

V

DD

MCLR

PIC16CXXX

R1

Q1

background image

PIC16C64X & PIC16C66X

DS30559A-page  66

Preliminary

©

 1996 Microchip Technology Inc.

9.5

Interrupts

The PIC16C641 and PIC16C642 have four sources of

interrupt, while the PIC16C661 and PIC16C662 have

five sources: 

• External interrupt RB0/INT

• TMR0 overflow interrupt

• PORTB change interrupts (pins RB7:RB4)

• Comparator interrupt

• Parallel Slave Port interrupt (PIC16C661/662)

The interrupt control register, (INTCON), records

individual core interrupt requests in flag bits. It also has

various individual enable bits and the global interrupt

enable bit. 

The global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on reset.

The “return from interrupt” instruction, 

RETFIE

, exits

the interrupt routine as well as sets the GIE bit, which

allows any pending interrupt to execute.

Those interrupts associated with the “core” have their

flag and enable bits in the INTCON register. The core

interrupts are: RB0/INT pin interrupt, the RB port

change interrupt, and the TMR0 overflow interrupt. The

INTCON register also contains the Peripheral Interrupt

Enable bit, PEIE. Bit PEIE will enable/mask the periph-

eral interrupts (CM and PSP) from vectoring when bit

PEIE is set/cleared.

Flag bits PSPIF and CMIF are contained in special

function register PIR1. The corresponding interrupt

enable bits (PSPIE and CMIE) are contained in special

function register PIE1.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed into the stack and the PC is loaded with 0004h.

Once in the interrupt service routine the source(s) of

the interrupt can be determined by polling the interrupt

flag bits. The interrupt flag bit(s) must be cleared in

software before re-enabling interrupts to avoid recur-

sive interrupts.

For external interrupt events, such as the RB0/INT or

Port RB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs (Figure 9-16).

The latency is the same for one or two cycle

instructions. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid multiple interrupt requests. Individual interrupt

flag bits are set regardless of the status of their

corresponding mask bit or the GIE bit. 

Note 1: Individual interrupt flag bits are set regard-

less of the status of their corresponding

mask bit or the GIE bit. 

Note 2: When an instruction that clears the GIE bit

is executed, any interrupts that were

pending for execution in the next cycle are

ignored. The CPU will execute a NOP in

the cycle immediately following the

instruction which clears the GIE bit. The

interrupts which were ignored are still

pending to be serviced when the GIE bit is

set again.

FIGURE 9-15: INTERRUPT LOGIC

RBIF

RBIE

T0IF

T0IE

INTF

INTE

GIE

CMIE

Wake-up

(If in SLEEP mode)

Interrupt 

CMIF

to CPU

PSPIE

(1)

PSPIF

(1)

PEIE

Note 1: The Parallel Slave Port is implemented on the PIC16C661 and PIC16C662 only.

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  67

PIC16C64X & PIC16C66X

9.5.1

RB0/INT INTERRUPT

The external interrupt on the RB0/INT pin is edge trig-

gered: either rising if bit INTEDG (OPTION<6>) is set,

or falling, if bit INTEDG is clear. When a valid edge

appears on the RB0/INT pin, flag bit INTF

(INTCON<1>) is set. This interrupt can be enabled/dis-

abled by setting/clearing enable bit INTE

(INTCON<4>). The INTF bit must be cleared in soft-

ware in the interrupt service routine before re-enabling

this interrupt. The RB0/INT interrupt can wake-up the

processor from SLEEP, if bit INTE was set prior to

going into SLEEP. The status of the GIE bit decides

whether or not the processor branches to the interrupt

vector following wake-up. See Section 9.8 for details

on SLEEP and Figure 9-19 for timing of wake-up from

SLEEP through RB0/INT interrupt.

9.5.2

TMR0 INTERRUPT

An overflow (FFh 

 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

be enabled/disabled by setting/clearing T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 6.0. 

9.5.3

PORTB INTERRUPT

An input change on any bit of PORTB<7:4> sets flag bit

RBIF (INTCON<0>). The interrupt can be enabled/dis-

abled by setting/clearing enable bit RBIE

(INTCON<4>). For operation of PORTB (Section 5.2).

9.5.4

COMPARATOR INTERRUPT

See Section 7.6 for complete description of the com-

parator interrupt.

FIGURE 9-16: RB0/INT PIN INTERRUPT TIMING

Q2

Q1

Q3

Q4

Q2

Q1

Q3

Q4

Q2

Q1

Q3

Q4

Q2

Q1

Q3

Q4

Q2

Q1

Q3

Q4

OSC1

CLKOUT

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

Instruction

fetched

Instruction

executed

Interrupt Latency

PC

PC+1

PC+1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC+1)

Inst (PC-1)

Inst (0004h)

Dummy Cycle

Inst (PC)

1

4

5

1

Note 1: INTF flag is sampled here (every Q1).

2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in RC oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles. 

2

3

background image

PIC16C64X & PIC16C66X

DS30559A-page  68

Preliminary

©

 1996 Microchip Technology Inc.

9.6

Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key reg-

isters during an interrupt e.g. W register and STATUS

register. This will have to be implemented in software.

Example 9-1 stores and restores the STATUS and W

registers. The user register, W_TEMP, must be defined

in both banks and must be defined at the same offset

from the bank base address (i.e., W_TEMP is defined

at 0x70 - 0x7F in Bank 0). The user register,

STATUS_TEMP, must be defined in Bank 0. 

Example 9-1:

• Stores the W register regardless of current bank

• Stores the STATUS register in Bank 0

• Executes the ISR code

• Restores the STATUS (and bank select bit 

register)

• Restores the W register

EXAMPLE 9-1:

SAVING THE STATUS AND W REGISTERS IN RAM 

MOVWF   W_TEMP         ; Copy W to a Temporary Register regardless of current bank

SWAPF   STATUS,W       ; Swap STATUS nibbles and place into W register

BCF     STATUS,RP0     ; Change to Bank 0 regardless of current bank

MOVWF   STATUS_TEMP    ; Save STATUS to a Temporary register in Bank 0

    :

    : (Interrupt Service Routine)

    :

SWAPF   STATUS_TEMP,W  ; Swap original STATUS register value into W (restores original bank)

MOVWF   STATUS         ; Restore STATUS register from W register

SWAPF   W_TEMP,F       ; Swap W_Temp nibbles and return value to W_Temp

SWAPF   W_TEMP,W       ; Swap W_Temp to W to restore original W value without affecting STATUS

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  69

PIC16C64X & PIC16C66X

9.7

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator which does not require any external com-

ponents. The block diagram is shown in Figure 9-17.

This RC oscillator is separate from the RC oscillator of

the OSC1/CLKIN pin. This means that the WDT will

run, even if the clock on the OSC1 and OSC2 pins has

been stopped, for example, by execution of a 

SLEEP

instruction. During normal operation, a WDT time-out

generates a device RESET. If the device is in SLEEP

mode, a WDT time-out causes the device to wake-up

and continue with normal operation, this is known as a

WDT wake-up. The WDT can be permanently disabled

by clearing configuration bit WDTE (Section 9.1).

9.7.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out period varies with temper-

ature, V

DD

 and process variations from part to part (see

DC specs). If longer time-outs are desired, a prescaler

with a division ratio of up to 1:128 can be assigned to

the WDT, under software control, by writing to the

OPTION register. Thus, time-out periods of up to 2.3

seconds can be realized.

The 

CLRWDT

 and 

SLEEP

 instructions clear the WDT and

the postscaler (if assigned to the WDT) and prevent it

from timing out and generating a device RESET. 

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer time-out (WDT Reset and WDT

wake-up).

9.7.2

WDT PROGRAMMING CONSIDERATIONS

It should also be taken in account that under worst case

conditions (V

DD

 = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a

WDT time-out occurs.

Note:

When the prescaler is assigned to the

WDT, always execute a 

CLRWDT

 instruction

before changing the prescale value, other-

wise a WDT reset may occur.

FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM

FIGURE 9-18: SUMMARY OF WATCHDOG TIMER REGISTERS

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2007h

Config. bits

MPEEN

BODEN

(1)

CP1

CP0

PWRTE

(1)

WDTE

FOSC1

FOSC0

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Figure 9-1 for details of the operation of these bits.

From TMR0 Clock Source

(Figure 7-6)

To TMR0 (Figure 7-6)

Postscaler

WDT Timer

WDT 

Enable Bit

0

1

M

U

X

PSA

8 - to - 1 MUX

PS2:PS0

0

1

MUX

PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION register.

8

background image

PIC16C64X & PIC16C66X

DS30559A-page  70

Preliminary

©

 1996 Microchip Technology Inc.

9.8

Power-Down Mode (SLEEP)

Power-down mode is entered by executing a 

SLEEP

instruction. 

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit in the STATUS register is

cleared, the TO bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before the 

SLEEP

 instruction was executed (driving

high, low, or hi-impedance).

For lowest current consumption in this mode, all I/O

pins should be either at V

DD

, or V

SS

, with no external

circuitry drawing current from the I/O pin and the com-

parators and V

REF

 module should be disabled. I/O pins

that are hi-impedance inputs should be pulled high or

low externally to avoid switching currents caused by

floating inputs. The T0CKI input should also be at V

DD

or V

SS

 for lowest current consumption. The contribu-

tion from on chip pull-ups on PORTB should be consid-

ered.

The MCLR pin must be at a logic high level (V

IHMC

).

9.8.1

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1.

Any device reset

2.

Watchdog Timer Wake-up (if WDT was enabled)

3.

Interrupt from RB0/INT pin, RB Port change, or

the Comparator.

The first event will reset the device upon wake-up.

However the latter two events will wake the device and

then resume program execution. The TO and PD bits in

the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up is cleared when SLEEP is invoked. The TO

bit is cleared if WDT wake-up occurred.

When the 

SLEEP

 instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake-up through an interrupt event, the correspond-

ing interrupt enable bit must be set (enabled). Wake-up

is regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the 

SLEEP

 instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the 

SLEEP

 instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following 

SLEEP 

is not desirable, the

user should have an 

NOP

 after the 

SLEEP

 instruction.

9.8.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag set, one of the following events will

occur:

• If the interrupt occurs before the execution of a 

SLEEP

 instruction, the 

SLEEP

 instruction will com-

plete as an NOP. Therefore, the WDT and WDT 

postscaler will not be cleared, the TO bit will not 

be set and PD bit will not be cleared.

• If the interrupt occurs during or after the execution 

of a 

SLEEP

 instruction, the device will immediately 

wake-up from sleep. The 

SLEEP

 instruction will be 

completely executed before the wake-up. There-

fore, the WDT and WDT postscaler will be 

cleared, the TO bit will be set and the PD bit will 

be cleared.

Even if the flag bits were checked before executing a

SLEEP

 instruction, it may be possible for flag bits to

become set before the 

SLEEP

 instruction completes. To

determine whether a 

SLEEP

 instruction executed, test

the PD bit. If the PD bit is set, the 

SLEEP

 instruction

was executed as an NOP.

To ensure that the WDT is clear, a 

CLRWDT

 instruction

should be executed before a 

SLEEP

 instruction.

FIGURE 9-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1

Q2

Q3 Q4

Q1 Q2

Q3

Q4

Q1

Q1

Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q1

Q2 Q3

Q4

Q1 Q2

Q3

Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

Instruction

fetched

Instruction

executed

PC

PC+1

PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2

0004h

0005h

Dummy cycle

T

OST

(2)

PC+2

Note

1: XT, HS or LP oscillator mode assumed.

2: T

OST

 = 1024T

OSC

 (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

background image

©

 1996 Microchip Technology Inc.

Preliminary

DS30559A-page  71

PIC16C64X & PIC16C66X

9.9

Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out for verification purposes.

9.10

ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code-identification numbers. These locations are

not accessible during normal execution but are

readable and writable during program/verify. Only the

least significant 4 bits of the ID locations are used.

Note:

Microchip does not recommend code

protecting windowed devices.

9.11

In-Circuit Serial Programming

The PIC16CXX microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground, and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

The device is placed into a program/verify mode by

holding the RB6 and RB7 pins low while raising the

MCLR (V

PP

) pin from V

IL

 to V

IHH

 (see programming

specification). RB6 becomes the programming clock

and RB7 becomes the programming data. Both RB6

and RB7 are Schmitt Trigger inputs in this mode.

After reset, to place the device into programming/verify

mode, the program counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14-bits of program data

are then supplied to or from the device, depending if

the command was a load or a read. For complete

details of serial programming, please refer to the

PIC16C6X/7X Programming Specifications (Literature

#DS30228).

A typical in-circuit serial programming connection is

shown in Figure 9-20.

FIGURE 9-20: TYPICAL IN-CIRCUIT SERIAL 

PROGRAMMING 

CONNECTION

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC16CXX

V

DD

V

SS

MCLR/V

PP

RB6

RB7

+5V

0V

V

PP

CLK

Data I/O

V

DD

background image

PIC16C64X & PIC16C66X

DS30559A-page  72

Preliminary

©

 1996 Microchip Technology Inc.

NOTES:

background image

 

©

 

 1996 Microchip Technology Inc.

DS30559A-page  73

 

PIC16C64X & PIC16C66X

 

10.0

INSTRUCTION SET SUMMARY

 

Each PIC16CXX instruction is a 14-bit word divided

into an OPCODE which specifies the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC16CXX instruction

set summary in Table 10-2 lists 

 

byte-oriented

 

 

bit-ori-

ented

 

, and 

 

literal and control

 

 operations. Table 10-1

shows the opcode field descriptions.

For 

 

byte-oriented

 

 instructions, 'f' represents a file reg-

ister designator and 'd' represents a destination desig-

nator. The file register designator specifies which file

register is to be used by the instruction. 

The destination designator specifies where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register. If 'd' is one, the result is placed

in the file register specified in the instruction.

For 

 

bit-oriented

 

 instructions, 'b' represents a bit field

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

file in which the bit is located.

For 

 

literal and control

 

 operations, 'k' represents an

eight or eleven bit constant or literal value.

 

TABLE 10-1:

OPCODE FIELD 

DESCRIPTIONS  

 

The instruction set is highly orthogonal and is grouped

into three basic categories:

 

Field

Description

 

f

 

Register file address (0x00 to 0x7F)

 

W

 

Working register (accumulator)

 

b

 

Bit address within an 8-bit file register

 

k

 

Literal field, constant data or label

 

x

 

Don't care location (= 0 or 1) 

The assembler will generate code with x = 0. It is the 

recommended form of use for compatibility with all 

Microchip software tools.

 

d

 

Destination select; d = 0: store result in W,

d = 1: store result in file register f. 

Default is d = 1

 

label

 

Label name

 

TOS

 

Top of Stack

 

PC

 

Program Counter

 

PCLATH

 

Program Counter High Latch

 

GIE

 

Global Interrupt Enable bit

 

WDT

 

Watchdog Timer/Counter

 

TO

 

Time-out bit

 

PD

 

Power-down bit

 

dest

 

Destination either the W register or the specified 

register file location

[  ]

Options

 

(  )

 

Contents

 

 

Assigned to

 

< >

 

Register bit field

 

 

In the set of

 

i

 

talics

 

User defined term (font is courier)

 

 

Byte-oriented

 

 operations

 

Bit-oriented

 

 operations

 

Literal and control

 

 operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In this case, the execution takes two instruction cycles

with the second cycle executed as a NOP. One instruc-

tion cycle consists of four oscillator periods. Thus, for

an oscillator frequency of 4 MHz, the normal instruction

execution time is 1 

 

µ

 

s. If a conditional test is true or the

program counter is changed as a result of an instruc-

tion, the instruction execution time is 2 

 

µ

 

s.

Table 10-2 lists the instructions recognized by the

MPASM assembler. 

Figure 10-1 shows the three general formats that the

instructions can have.     

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signifies a hexadecimal digit. 

 

FIGURE 10-1: GENERAL FORMAT FOR 

INSTRUCTIONS    

 

Note:

 

To maintain upward compatibility with

future PIC16CXX products, do not use the

 

OPTION

 

 and 

 

TRIS

 

 instructions.

Byte-oriented file register operations

13                          8     7    6                              0

d = 0 for destination W

OPCODE            d              f (FILE #)

d = 1 for destination f

f  = 7-bit file register address

Bit-oriented file register operations

13                         10  9        7   6                       0

OPCODE          b (BIT #)        f (FILE #)

b = 3-bit bit address

f  = 7-bit file register address

Literal and control operations

13                                  8    7                             0

OPCODE                              k (literal)

k  = 8-bit immediate value

13                 11    10                                          0

OPCODE                        k (literal)

k  = 11-bit immediate value

General

CALL

 and 

GOTO

 instructions only

 

This document was created with FrameMaker 4 0 4

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  74

 

©

 

 1996 Microchip Technology Inc.

 

10.1

Special Function Registers as 

Source/Destination

 

The PIC16C64X & PIC16C66X’s orthogonal instruction

set allows read and write of all file registers, including

special function registers. There are some special situ-

ations the user should be aware of:

10.1.1

STATUS AS DESTINATION 

If an instruction writes to STATUS, the Z, C, and DC bits

may be set or cleared as a result of the instruction and

overwrite the original data bits written. For example,

executing 

 

CLRF STATUS

 

 will clear register STATUS,

and then set the Z bit leaving 

 

0000 0100b

 

 in the reg-

ister.

10.1.2

PCL AS SOURCE OR DESTINATION 

Read, write or read-modify-write on PCL may have the

following results:

Read PC:

PCL 

 

 

 dest

Write PCL:

PCLATH 

 

 

 PCH;

8-bit destination value 

 

 

 PCL

Read-Modify-Write:

PCL

 

 

 ALU operand

PCLATH 

 

 

 PCH;

8-bit result 

 

 

 PCL

Where PCH = program counter high byte (not an

addressable register), PCLATH = Program counter

high holding latch, dest = destination, WREG or f.

10.1.3

BIT MANIPULATION

All bit manipulation instructions are done by first read-

ing the entire register, operating on the selected bit and

writing the result back (read-modify-write). The user

should keep this in mind when operating on special

function registers, such as ports. 

background image

 

©

 

 1996 Microchip Technology Inc.

DS30559A-page  75

 

PIC16C64X & PIC16C66X

 

TABLE 10-2:

INSTRUCTION SET   

 

Mnemonic,

Operands

Description

Cycles

14-Bit Opcode

Status

Affected

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

f, d

f

-

f, d

f, d

f, d

f, d

f, d

f, d

f, d

f

-

f, d

f, d

f, d

f, d

f, d

 

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1

1

1

1

1

1

1(2)

1

1(2)

1

1

1

1

1

1

1

1

1

 

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

00

0111

0101

0001

0001

1001

0011

1011

1010

1111

0100

1000

0000

0000

1101

1100

0010

1110

0110

dfff

dfff

lfff

0000

dfff

dfff

dfff

dfff

dfff

dfff

dfff

lfff

0xx0

dfff

dfff

dfff

dfff

dfff

ffff

ffff

ffff

0011

ffff

ffff

ffff

ffff

ffff

ffff

ffff

ffff

0000

ffff

ffff

ffff

ffff

ffff

 

C,DC,Z

Z

Z

Z

Z

Z

Z

Z

Z

C

C

C,DC,Z

Z

1,2

1,2

2

1,2

1,2

1,2,3

1,2

1,2,3

1,2

1,2

1,2

1,2

1,2

1,2

1,2

 

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

f, b

f, b

f, b

 

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1

1 (2)

1 (2)

 

01

01

01

01

00bb

01bb

10bb

11bb

bfff

bfff

bfff

bfff

ffff

ffff

ffff

ffff

 

1,2

1,2

3

3

 

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

k

k

-

k

k

k

-

k

-

-

k

k

 

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W 

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

1

1

2

1

2

1

1

2

2

2

1

1

1

 

11

11

10

00

10

11

11

00

11

00

00

11

11

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

0000

110x

1010

kkkk

kkkk

kkkk

0110

kkkk

kkkk

kkkk

0000

kkkk

0000

0110

kkkk

kkkk

kkkk

kkkk

kkkk

0100

kkkk

kkkk

kkkk

1001

kkkk

1000

0011

kkkk

kkkk

 

C,DC,Z

Z

TO

 

,

 

PD

Z

TO

 

,

 

PD

C,DC,Z

Z

Note 1:

When an I/O register is modified as a function of itself ( e.g., 

 

MOVF PORTB, 1

 

), the value used will be that value present 

on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external 

device, the data will be written back with a '0'.

2:

If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned 

to the Timer0 Module.

3:

If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is 

executed as a NOP.

background image

 

PIC16C64X & PIC16C66X

 

DS30559A-page  76

 

©

 

 1996 Microchip Technology Inc.

 

10.2

Instruction Descriptions 

 

ADDLW

Add Literal and W

 

Syntax:

[

 

 label

 

 ]  ADDLW     k

Operands:

 

 

 k 

 

 

 255

Operation:

(W) + k 

 

 

 (W)

Status Affected:

C, DC, Z

Encoding:

 

11

111x

kkkk

kkkk

 

Description:

 

The contents of the W register are 

added to the eight bit literal 'k' and the 

result is placed in the W register

 

.

Words:

1

Cycles:

1

Example

 

ADDLW

0x15

 

Before Instruction

 

W

=

0x10

 

After Instruction

 

W =  0x25

 

ADDWF

Add W and f

 

Syntax:

 

label 

 

]  ADDWF     f,d

Operands:

 

 

 f 

 

 

 127

 

∈ [0,1]

 

Operation:

(W) + (f) 

 

 

 (dest)

Status Affected:

C, DC, Z

Encoding:

 

00

0111

dfff

ffff

 

Description:

 

Add the contents of the W reg