background image

FINAL

Publication#  14971

Rev: Amendment/0

Issue Date:  May 1998

Am27C040

4 Megabit (512 K x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

s

Fast access time

— Available in speed options as fast as 90 ns

s

Low power consumption

— <10 µA typical CMOS standby current

s

JEDEC-approved pinout

— Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs

— Easy upgrade from 28-pin JEDEC EPROMs

s

Single +5 V power supply

s

±

10% power supply tolerance standard

s

100% Flashrite™ programming

— Typical programming time of 1 minute

s

Latch-up protected to 100 mA from –1 V to 

V

CC

 + 1 V

s

High noise immunity

s

Compact 32-pin DIP, PDIP, PLCC packages

GENERAL DESCRIPTION

The Am27C040 is a 4 Mbit ultraviolet erasable pro-

grammable read-only memory. It is organized as 512K

bytes, operates from a single +5 V supply, has a static

standby mode, and features fast single address loca-

tion programming. The device is available in windowed

ceramic DIP packages and plastic one-time program-

mable (OTP) packages.

Data can be typically accessed in less than 90 ns, al-

lowing high-performance microprocessors to operate

without any WAIT states. The device offers separate

Output Enable (OE#) and Chip Enable (CE#) controls,

thus eliminating bus contention in a multiple bus micro-

processor system.

AMD’s CMOS process technology provides high

speed, low power, and high noise immunity. Typical

power consumption is only 100 mW in active mode,

and 50 µW in standby mode.

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in

blocks, or at random. The device supports AMD’s

Flashrite programming algorithm (100 µs pulses) re-

sulting in typical programming time of 1 minute.

BLOCK DIAGRAM

14971G-1

A0–A18 

Address 

Inputs

CE#/PGM#

OE#

V

CC

V

SS

V

PP

Data Outputs 

DQ0–DQ7

Output 

Buffers

Gating

4,194,304-Bit

Cell Matrix

Decoder

Decoder

Output Enable 

Chip Enable 

and 

Prog Logic

background image

2

Am27C040

F I N A L

PRODUCT SELECTOR GUIDE

CONNECTION DIAGRAMS

Top View

DIP

PLCC

Notes:

1. JEDEC nomenclature is in parenthesis.

2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.

PIN DESIGNATIONS

A0–A18

=

Address Inputs

CE# (E#)/PGM# (P#)=

Chip Enable/Program Enable Input

DQ0–DQ7

=

Data Inputs/Outputs

OE# (G#)

=

Output Enable Input

V

CC

=

V

CC

 Supply Voltage

V

PP

=

Program Voltage Input

V

SS

=

GroundLogic Symbol

LOGIC SYMBOL

Family Part Number

Am27C040

Speed Options (V

CC

= 5.0 V 

±

 10%)

-90

-120

-150

-200

Max Access Time (ns)

90

120

150

200

CE# (E#) Access (ns)

90

120

150

200

OE# (G#) Access (ns)

40

50

65

75

3

4

5

2

1

9

10

11

12

13

27

26

25

24

23

7

8

22

21

6

32

31

20

14

30

29

28

15

16

19

18

17

A6

A5

A4

A3

A2

A1

A0

A16

DQ0

A15

A12

A7

DQ1

DQ2

V

SS

A8

A9

A11

OE# (G#)

A10

CE# (E#)/PGM# (P#)

DQ7

V

CC

A18

DQ6

A17

A14

A13

DQ5

DQ4

DQ3

V

PP

14971G-2

5

6

7

8

9

10

11

12

13

17 18 19 20

16

15

14

29

28

27

26

25

24

23

22

21

A7

A6

A5

A4

A3

A2

A1

A0

DQ0

DQ1

DQ2

V

SS

DQ3

DQ4

DQ5

DQ6

1

31 30

2

3

4

32

A14

A13

A8

A9

A11

OE# (G#)

A10

CE# (E#)/PGM# (P#)

DQ7

A12

A15

A16

V

PP

V

CC

A18

A17

14971G-3

19

8

DQ0–DQ7

A0–A18

OE# (G#)

14971E-4

CE# (E#)/PGM#(P#)

background image

Am27C040

3

F I N A L

ORDERING INFORMATION

UV EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am27C040

4 Megabit (512K x 8-Bit) CMOS UV EPROM

AM27C040

-90

D

C

OPTIONAL PROCESSING

Blank = Standard Processing

B

= Burn-In

TEMPERATURE RANGE

C = Commercial (0

°

C to +70

°

C)

I

= Industrial (–40

°

C to +85

°

C)

E

= Extended (–55

°

C to +125

°

C)

PACKAGE TYPE

D = 32-Pin Ceramic DIP (CDV032)

SPEED OPTION

See Product Selector Guide and 

Valid Combinations

Valid Combinations

AM27C040-90

DC, DCB, DI, DIB, DE, DEB

AM27C040-120

AM27C040-150

AM27C040-200

background image

4

Am27C040

F I N A L

ORDERING INFORMATION

OTP EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am27C040

4 Megabit (512K x 8-Bit) CMOS OTP EPROM

AM27C040

-90

J

C

OPTIONAL PROCESSING

Blank = Standard Processing

TEMPERATURE RANGE

C = Commercial (0

°

C to +70

°

C)

I

= Industrial (–40

°

C to +85

°

C)

E

= Extended (–55

°

C to 125

°

C)

PACKAGE TYPE

P

= 32-Pin Plastic DIP (PD 032)

J

= 32-Pin Rectangular Plastic Leaded Chip 

Carrier (PL 032)

SPEED OPTION

See Product Selector Guide and 

Valid Combinations

Valid Combinations

AM27C040-90

PC, PI, JC, JI

AM27C040-120

AM27C040-150

AM27C040-200

background image

Am27C040

5

F I N A L

FUNCTIONAL DESCRIPTION

Device Erasure

In order to clear all locations of their programmed

contents, the device must be exposed to an ultraviolet

light source. A dosage of 15 W seconds/cm

2

 is required

to completely erase the device. This dosage can be ob-

tained by exposure to an ultraviolet lamp — wavelength

of 2537 Å — with intensity of 12,000 µW/cm

2

 for 15 to 20

minutes. The device should be directly under and about

one inch from the source and all filters should be re-

moved from the UV light source prior to erasure.

Note that all UV erasable devices will erase with light

sources having wavelengths shorter than 4000 Å, such

as fluorescent light and sunlight. Although the erasure

process happens over a much longer time period, ex-

posure to any light source should be prevented for

maximum system reliability. Simply cover the package

window with an opaque label or substance.

Device Programming

Upon delivery, or after each erasure, the device has

all of its bits in the “ONE”, or HIGH state. “ZEROs” are

loaded into the device through the programming pro-

cedure.

The programming mode is entered when 12.75 V 

±

0.25 V is applied to the V

PP

 pin, CE#/PGM# is at V

IL

and OE# is at V

IH

 .

For programming, the data to be programmed is ap-

plied 8 bits in parallel to the data output pins.

The flowchart in the EPROM Products Data Book, Pro-

gramming section (Section 5, Figure 5-1) shows AMD’s

Flashrite algorithm. The Flashrite algorithm reduces pro-

gramming time by using a 100 µs programming pulse

and by giving each address only as many pulses to reli-

ably program the data. After each pulse is applied to a

given address, the data in that address is verified. If the

data does not verify, additional pulses are given until it

verifies or the maximum pulses allowed is reached. This

process is repeated while sequencing through each ad-

dress of the device. This part of the algorithm is done at

V

CC

 = 6.25 V to assure that each EPROM bit is pro-

grammed to a sufficiently high threshold voltage. After

the final address is completed, the entire EPROM mem-

ory is verified at V

CC

 = V

PP

 = 5.25 V.

Please refer to the EPROM Products Data Book, Sec-

tion 5 for the programming flow chart and characteris-

tics.

Program Inhibit

Programming different data to multiple devices in par-

allel is easily accomplished. Except for CE#/PGM#, all

like inputs of the devices may be common. A TTL

low-level program pulse applied to one device’s CE#/

PGM# input with V

PP

 = 12.75 V 

±

 0.25 V will program

that particular device. A high-level CE#/PGM# input in-

hibits the other devices from being programmed.

Program Verify

A verification should be performed on the programmed

bits to determine that they were correctly programmed.

The verify should be performed with OE# at V

IL

, CE#/

PGM# at V

IH

, and V

PP

 between 12.5 V and 13.0 V.

Auto Select Mode

The autoselect mode provides manufacturer and de-

vice identification through identifier codes on DQ0–

DQ7. This mode is primarily intended for programming

equipment to automatically match a device to be pro-

grammed with its corresponding programming algo-

rithm. This mode is functional in the 25

°

±

  5

°

C

ambient temperature range that is required when pro-

gramming the device.

To activate this mode, the programming equipment

must force V

H

 on address line A9. Two identifier bytes

may then be sequenced from the device outputs by tog-

gling address line A0 from V

IL

 to V

IH 

(that is, changing

the address from 00h to 01h). All other address lines

must be held at V

IL

 during the autoselect mode.

Byte 0 (A0 = V

IL

) represents the manufacturer code,

and Byte 1 (A0 = V

IH

), the device identifier code. Both

codes have odd parity, with DQ7 as the parity bit.

Read Mode

To obtain data at the device outputs, Chip Enable (CE#/

PGM#) and Output Enable (OE#) must be driven low.

CE#/PGM# controls the power to the device and is typ-

ically used to select the device. OE# enables the device

to output data, independent of device selection. Ad-

dresses must be stable for at least t

ACC

–t

OE

.

 

Refer to

the Switching Waveforms section for the timing dia-

gram.

Standby Mode

The device enters the CMOS standby mode when

CE#/PGM# is at V

CC

 

±

 0.3 V. Maximum V

CC 

current is

reduced to 100 µA. The device enters the TTL-standby

mode when CE#/PGM# is at V

IH

. Maximum V

CC 

cur-

rent is reduced to 1.0 mA. When in either standby

mode, the device places its outputs in a high-imped-

ance state, independent of the OE# input.

Output OR-Tieing

To accommodate multiple memory connections, a

two-line control function is provided to allow for:

s

Low memory power dissipation, and 

s

Assurance that output bus contention will not occur

CE#/PGM# should be decoded and used as the pri-

mary device-selecting function, while OE# be made a

background image

6

Am27C040

F I N A L

common connection to all devices in the array and con-

nected to the READ line from the system control bus.

This assures that all deselected memory devices are in

their low-power standby mode and that the output pins

are only active when data is desired from a particular

memory device.

System Applications

During the switch between active and standby condi-

tions, transient current peaks are produced on the ris-

ing and falling edges of Chip Enable. The magnitude of

these transient current peaks is dependent on the out-

put capacitance loading of the device. At a minimum, a

0.1 µF ceramic capacitor (high frequency, low inherent

inductance) should be used on each device between

V

CC

 and V

SS

 to minimize transient effects. In addition,

to overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on EPROM ar-

rays, a 4.7 µF bulk electrolytic capacitor should be used

between V

CC

 and V

SS

 for each eight devices. The loca-

tion of the capacitor should be close to where the

power supply is connected to the array.

MODE SELECT TABLE

Note:

1. V

H

 

= 12.0 V 

±

 0.5 V.

2. X = Either V

IH 

or V

IL

3. A1 – A8 = A10 – A18 = V

IL

4. See DC Programming Characteristics in the EPROM Products Data Book for V

PP 

voltage during programming

Mode

CE#/PGM#

OE#

A0

A9

V

PP

Outputs

Read

V

IL

V

IL

X

X

X

D

OUT

Output Disable

V

IL

V

IH

X

X

X

HIGH Z

Standby (TTL)

V

IH

X

X

X

X

HIGH Z

Standby (CMOS)

V

CC 

+ 0.3 V

X

X

X

X

HIGH Z

Program

V

IL

V

IH

X

X

V

PP

D

IN

Program Verify

V

IL

V

IL

X

X

V

PP

D

OUT

Program Inhibit

V

IH

X

X

X

V

PP

HIGH Z

Auto Select

(Note 3)

Manufacturer Code

V

IL

V

IL

V

IL

V

H

X

01h

Device Code

V

IL

V

IL

V

IH

V

H

X

9Bh

background image

Am27C040

7

F I N A L

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

OTP Products . . . . . . . . . . . . . . . . –65

°

C to +125

°

C

All Other Products. . . . . . . . . . . . . –65

°

C to +150

°

C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . .–55

°

C to + 125

°

C

Voltage with Respect to V

SS

All pins except A9, V

PP

,

V

CC

 (Note 1) . . . . . . . . . . . . . . –0.6 V to V

CC

 +0.5 V

A9 and V

PP

 (Note 2)  . . . . . . . . . . . . –0.6 V to +13.5 V

V

CC

  . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to +7.0 V

1. During voltage transitions, inputs may overshoot V

SS

 to –

2.0 V for periods of up to 20 ns. Maximum DC voltage on

input and I/O pins may overshoot to V

CC

 + 2.0 V for

periods up to 20 ns.

2. During voltage transitions, A9 and V

PP

 may overshoot

V

SS

 to –2.0 V for periods of up to 20 ns. A9 and V

PP

 must

not exceed +13.5 V at any time. 

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the op-

erational sections of this specification is not implied. Expo-

sure of the device to absolute maximum rating conditions for

extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

A

)  . . . . . . . . . . .0

°

C to +70

°

C

Industrial (I) Devices

Ambient Temperature (T

A

)  . . . . . . . . .–40

°

C to +85

°

C

Extended (E) Devices

Ambient Temperature (T

A

)  . . . . . . . .–55

°

C to +125

°

C

Supply Read Voltages

V

CC

 for ± 5% devices  . . . . . . . . . .  +4.75 V to +5.25 V

V

CC

 for ± 10% devices  . . . . . . . . .  +4.50 V to +5.50 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

background image

8

Am27C040

F I N A L

DC CHARACTERISTICS  over operating ranges unless otherwise specified

Caution: The device must not be removed from (or inserted into) a socket when V

CC

 or V

PP

 is applied.

Notes:

1. V

CC

 must be applied simultaneously or before V

PP 

and removed simultaneously or after V

PP

2. I

CC1

 is tested with OE# = V

IH 

to simulate open outputs.

3. Minimum DC Input Voltage is –0.5. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns. Maxi-

mum DC Voltage on output pins is Vcc +0.5 V, which may overshoot to V

CC 

+2.0 V for periods less than 20 ns.

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

V

OH

Output HIGH Voltage

I

OH

 = –400 µA

2.4

V

V

OL

Output LOW Voltage

I

OL

 = 2.1 mA

0.45

V

V

IH

Input HIGH Voltage

2.0

V

CC

 + 0.5

V

V

IL

Input LOW Voltage

–0.5

+0.8

V

I

LI

Input Load Current

V

IN

 = 0 V to V

CC

C/I Devices

1.0

µA

E Devices

5.0

I

LO

Output Leakage Current

V

OUT

 = 0 V to V

CC

5.0

µA

I

CC1

V

CC

 Active Current (Note 3)

CE# = V

IL

, f = 10 MHz,

I

OUT

 = 0 MA

C/I Devices

40

mA

E Devices

60

I

CC2

V

CC

 TTL Standby Current

CE# = V

IH

1.0

mA

I

CC3

V

CC

 CMOS Standby 

Current

CE# = V

CC

 

±

 0.3 V

100

µA

I

PP1

V

PP

 Current During Read

CE# = OE# = V

IL

, V

PP

 

= V

CC

100

µA

1

6

10

25

15

5

10

20

2

3

4

5

7

8

9

Frequency in MHz

Su

pply

 Cu

rre

nt

in mA

Figure 1.

Typical Supply Current vs. Frequency

V

CC

 = 5.5 V, T = 25

°

C

14971E-1

–75

50

150

25

15

5

10

20

–50 –25

0

25

75

100 125

Temperature in 

°

C

Su

pply

 Cu

rre

nt

in mA

Figure 2.

Typical Supply Current vs. Temperature

V

CC

 = 5.5 V, f = 10 MHz

14971E-1

background image

Am27C040

9

F I N A L

TEST CONDITIONS

Table 1.

Test Specifications

SWITCHING TEST WAVEFORM

KEY TO SWITCHING WAVEFORMS

2.7 k

CL

6.2 k

5.0 V

Device

Under

Test

14971G-5

Figure 1.

Test Setup

Note:

Diodes are IN3064 or equivalents.

Test Condition

All

Unit

Output Load

1 TTL gate 

Output Load Capacitance, C

L

(including jig capacitance) 

100

pF

Input Rise and Fall Times

 20

ns

Input Pulse Levels

0.45–2.4

V

Input timing measurement reference 

levels

0.8, 2.0

V

Output timing measurement 

reference levels

0.8, 2.0

V

2.4 V

0.45 V

Input

Output

Test Points

2.0 V

2.0 V

0.8 V

0.8 V

14971G-6

3 V

0 V

Input

Output

1.5 V

1.5 V

Test Points

Note: For C

L

 = 100 pF.

Note: For C

L

 = 30 pF.

KS000010-PAL

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Changing, State Unknown

Does Not Apply

Center Line is High Impedance State (High Z) 

background image

10

Am27C040

F I N A L

AC CHARACTERISTICS

Caution: Do not remove the device from (or inserted into) a socket when V

CC

 or V

PP

 is applied.

Notes:

1. V

CC

 must be applied simultaneously or before V

PP

, and removed simultaneously or after V

PP

.

2. This parameter is sampled and not 100% tested.

3. Switching characteristics are over operating range, unless otherwise specified.

4. See Figure 1 and Table 1 for test specifications.

SWITCHING WAVEFORMS

PACKAGE CAPACITANCE

Notes:

1. This parameter is only sampled and not 100% tested.

2. T

A

 = +25

°

C, f = 1 MHz.

Parameter Symbols

Description

Test Setup

Am27C040

Unit

JEDEC

Std.

-90

-120

-150

-200

t

AVQV

t

ACC

Address to Output Delay

CE# = OE# 

= V

IL

Max

90

120

150

200

ns

t

ELQV

t

CE

Chip Enable to Output Delay

OE# = V

IL

Max

90

120

150

200

ns

t

GLQV

t

OE

Output Enable to Output Delay

CE# = V

IL

Max

40

50

65

75

ns

t

EHQZ

t

GHQZ

t

DF

(Note 2)

Chip Enable High or Output Enable High, 

Whichever Occurs First, to Output High Z

Max

30

30

30

40

ns

t

AXQX

t

OH

Output Hold Time from Addresses, CE# or 

OE#, Whichever Occurs First

Min

0

0

0

0

ns

Parameter 

Symbol

Parameter 

Description

Test 

Conditions

CDV032

PD 032

PL 032

Unit

Typ

Max

Typ

Max

Typ

Max

C

IN

Input Capacitance

V

IN 

=  0  V

10

12

10

12

8

10

pF

C

OUT

Output Capacitance V

OUT 

=  0  V

12

15

12

15

9

12

pF

Addresses

CE#/PGM#

OE#

Output

Addresses Valid

High Z

High Z

t

CE

Valid Output 

2.4

0.45

2.0

0.8

2.0

0.8

t

ACC

(Note 1)

t

OE

t

DF

(Note 2)

t

OH

Note:

1. OE# may be delayed up to t

ACC

 - t

OE

 after the falling edge of the addresses without impact on t

ACC.

2. t

DF

 is specified from OE# or CE#, whichever occurs first.

14971E-1

background image

Am27C040

11

F I N A L

PHYSICAL DIMENSIONS

PD 032—32-Pin Plastic Dual In-Line Package (measured in inches) 

PL 032—32-Pin Plastic Leaded Chip Carrier (measured in inches)

Pin 1 I.D.

1.640

1.670

.530

.580

.005 MIN

.045

.065

.090

.110

.140

.225

.120

.160

.016

.022

SEATING PLANE

.015

.060

16-038-S_AG

PD 032

EC75

5-28-97 lv

32

17

16

.630

.700

0

°

10

°

.600

.625

.009

.015

.050 REF.

.026

.032

TOP VIEW

Pin 1 I.D.

.485

.495

.447

.453

.585

.595

.547

.553

16-038FPO-5

PL 032

DA79

6-28-94 ae

SIDE VIEW

SEATING

PLANE

.125

.140

.009

.015

.080

.095

.042

.056

.013

.021

.400

REF.

.490

.530

background image

12

Am27C040

F I N A L

PHYSICAL DIMENSIONS*

CDV032—32-Pin Ceramic DIP, UV Lens (measured in inches) 

* For reference only. BSC is an ANSI standard for Basic Space Centering.

REVISION SUMMARY FOR AM27C040

Revision E/1

Product Selector Guide:

Added -90 (90 ns, 

±

10% V

CC

) and deleted -100 speed options.

Ordering Information, UV EPROM Products:

The -90 part number is now listed in the example.

Valid Combinations: Added -90 and deleted -100 speed options in valid combinations.

Ordering Information, OTP EPROM Products:

The -90 part number is now listed in the example.

Valid Combinations: Added -90 and deleted -100 speed options in valid combinations.

Programming the Am27C040:

The fourth paragraph should read, “Please refer to Section 5 for programming…”.

TOP VIEW

SIDE VIEW

END VIEW

INDEX AND

TERMINAL NO. 1

I.D. AREA

.565

.605

1.635

1.680

.005 MIN

.045

.065

.014

.026

.100 BSC

.015

.060

.160

.220

.125

.200

BASE PLANE

SEATING PLANE

.300 BSC

.600

BSC

.008

.018

94

°

105

°

.700

MAX

16-000038H-3

CDV032

DF11

3-30-95 ae

DATUM D

CENTER PLANE

DATUM D

CENTER PLANE

1

UV Lens

background image

Am27C040

13

F I N A L

Operating Ranges:

Changed Supply Read Voltages listings to match those

in the Product Selector Guide.

AC Characteristics:

Added -90 and deleted -100 speed options in table, re-

arranged notes, moved text from table title to Note 4,

renamed table.

Revision F

Deleted -255 speed option.

Changed all active low signal designations from over-

bars or trailing “#”s.

Revision G

Global

Made formatting and layout consistent with other data

sheets. Used updated common tables and diagrams.

Distinctive Characteristics:

Low Power Consumption: Changed “100 µA maximum”

to “<10 µA typical”.

TSOP package deleted.

General Description:

In the third paragraph, changed “100 µW in standby

mode” to 50 µW in standby mode”.

Connection Diagrams:

Deleted TSOP Pinout figure.

Pin Designations:

Changed “Chip Enable Input” to “Chip Enable/Program

Enable Input”.

Ordering Information:

UV EPROM Products: Changed -75 speed option to

-90.

OTP EPROM Products: Changed -75 speed option to

-90. 

Temperature Range: Added “E = Extended (–55

°

C to

125

°

C)

”.

Package Type: Deleted “E = 32-pin Thin Small Outline

Package (TSOP) Standard Pinout (TS 032)”.

Valid Combinations: Deleted EC and EI options.

Functional Description:

Replaced device specific text with generic text.

Test Conditions:

New section with Test Setup Figure and Test Specifica-

tions Table.

Switching Test Waveform:

Modified figure.

Operating Ranges:

Supply Read Voltages: Replaced with generic data.

DC Characteristics:

Modified Figures 1 and 2.

Switching Waveform:

Corrected “DF” to “t

DF

” in Note 2.

Package Capacitance:

Deleted TSOP data.

Physical Dimensions:

New section, added figures for the 32-Pin Ceramic DIP,

32-Pin Plastic DIP, and 32-Pin Plastic Leaded Chip

Carrier.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Flashrite is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.


Document Outline