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FINAL

Publication#  06780

Rev: Amendment/0

Issue Date:  May 1998

Am27C1024

1 Megabit (65 K x 16-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

s

Fast access time

— Speed options as fast as 55 ns

s

Low power consumption

— 20 µA typical CMOS standby current

s

JEDEC-approved pinout

— 40-Pin DIP/PDIP

— 44-Pin PLCC

s

Single +5 V power supply

s

±

10% power supply tolerance standard

s

100% Flashrite™ programming

— Typical programming time of 8 seconds

s

Latch-up protected to 100 mA from –1 V to 

V

CC

 + 1 V

s

High noise immunity

s

Versatile features for simple interfacing

— Both CMOS and TTL input/output compatibility

— Two line control functions

GENERAL DESCRIPTION

The Am27C1024 is a 1 Megabit, ultraviolet erasable

programmable read-only memory. It is organized as 64

Kwords by 16 bits per word, operates from a single

+5 V supply, has a static standby mode, and features

fast single address location programming. Products are

available in windowed ceramic DIP packages, as well

as plastic one time programmable (OTP) PDIP and

PLCC packages. 

Data can be typically accessed in less than 55 ns, al-

lowing high-performance microprocessors to operate

without any WAIT states. The device offers separate

Output Enable (OE#) and Chip Enable (CE#) controls,

thus eliminating bus contention in a multiple bus micro-

processor system.

AMD’s CMOS process technology provides high

speed, low power, and high noise immunity. Typical

power consumption is only 125 mW in active mode,

and 100 µW in standby mode.

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in

blocks, or at random. The device supports AMD’s

Flashrite programming algorithm (100 µs pulses), re-

sulting in a typical programming time of 8 seconds.

BLOCK DIAGRAM

06780J-1

A0–A15 

Address 

Inputs

PGM#

CE#

OE#

V

CC

V

SS

V

PP

Data Outputs 

DQ0–DQ15

Output 

Buffers

Gating

1,048,576

Bit Cell 

Matrix

Decoder

Decoder

Output Enable 

Chip Enable 

and 

Prog Logic

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2

Am27C1024

PRODUCT SELECTOR GUIDE

CONNECTION DIAGRAMS

DIP

PLCC

Notes:

1. JEDEC nomenclature is in parenthesis.

2. Don’t use (DU) for PLCC.

PIN DESIGNATIONS

A0–A15

= Address Inputs

CE# (E#)

= Chip Enable Input

DQ0–DQ15 = Data Input/Outputs

OE# (G#)

= Output Enable Input

PGM# (P#)

= Program Enable Input

V

CC

= V

CC

 Supply Voltage

V

PP

= Program Voltage Input

V

SS

= Ground

NC

= No Internal Connection

LOGIC SYMBOL

Family Part Number

Am27C1024

Speed Options

V

CC

= 5.0 V 

±

 5%

-55

-255

V

CC

= 5.0 V 

±

 10%

-55

-70

-90

-120

-150

-200

Max Access Time (ns)

55

70

90

120

150

200

250

CE# (E#) Access (ns)

55

70

90

120

150

200

250

OE# (G#) Access (ns)

40

40

45

50

65

75

75

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

V

CC

PGM# (P#)

NC

A15

A14

A13

A12

A11

A10

A9

V

SS

A8

A7

A6

A5

A4

A3

A2

A1

A0

V

PP

CE# (E#)

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

V

SS

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

OE# (G#)

06780J-2

1 44 43 42

5

4

3

2

6

41 40

7

8

9

10

11

12

13

14

15

16

17

A13

A12

A11

A10

A9

V

SS

NC

A8

A7

A6

A5

DQ13

DQ14

DQ15

CE (E)

V

PP

DU (Note 2)

V

CC

PGM# (P#)

NC

A15

A14

39

38

37

36

35

34

33

32

31

30

29

DQ12

DQ11

DQ10

DQ9

DQ8

V

SS

NC

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

OE# (G#)

DU (Note 2)

A0

A1

A2

A3

A4

23 24 25 26

19 20 21 22

18

27 28

06780J-3

16

16

DQ0–DQ15

A0–A15

CE# (E#)

OE# (G#)

06780J-4

PGM# (P#)

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Am27C1024

3

ORDERING INFORMATION

UV EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am27C1024

1 Megabit (64 K x 16-Bit) CMOS UV EPROM

AM27C1024

-55

D

C

OPTIONAL PROCESSING

Blank = Standard Processing

B

= Burn-In

VOLTAGE TOLERANCE

5

= V

CC

 ± 

5%, 55 ns only

See Product Selector Guide and Valid Combinations

TEMPERATURE RANGE

C = Commercial (0

°

C to +70

°

C)

I

= Industrial (–40

°

C to +85

°

C)

E

= Extended (–55

°

C to +125

°

C)

PACKAGE TYPE

D = 40-Pin Ceramic DIP (CDV040)

SPEED OPTION

See Product Selector Guide and Valid Combinations

5

B

Valid Combinations

AM27C1024-55

V

CC 

= 5.0 V 

±

 5%

DC5, DC5B, DI5, DI5B

AM27C1024-55

V

CC 

= 5.0 V 

±

 10%

DC, DCB, DI, DIB

AM27C1024-70

AM27C1024-90

AM27C1024-120

DC, DCB, DI, DIB, DE, DEB

AM27C1024-150

AM27C1024-200

AM27C1024-255

V

CC 

= 5.0 V 

±

 5%

DC, DCB, DI, DIB

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4

Am27C1024

ORDERING INFORMATION

OTP EPROM Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the following:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am27C1024

1 Megabit (64 K x 16-Bit) CMOS OTP EPROM

AM27C1024

-55

J

C

OPTIONAL PROCESSING

Blank = Standard Processing

VOLTAGE TOLERANCE

5

= V

CC

 ± 

5%, 55 ns only

See Product Selector Guide and Valid Combinations

TEMPERATURE RANGE

C = Commercial (0

°

C to +70

°

C)

I

= Industrial (–40

°

C to +85

°

C)

PACKAGE TYPE

P

= 40-Pin Plastic DIP (PD 040)

J

= 44-Pin Plastic Leaded Chip Carrier (PL 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

5

Valid Combinations

AM27C1024-55

V

CC 

= 5.0 V 

±

 5%

PC5, PI5, JC5, JI5

AM27C1024-55

V

CC 

= 5.0 V 

±

 10%

JC, PC, JI, PI

AM27C1024-70

AM27C1024-90

AM27C1024-120

AM27C1024-150

AM27C1024-200

AM27C1024-255

V

CC 

= 5.0 V 

±

 5%

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Am27C1024

5

FUNCTIONAL DESCRIPTION

Device Erasure

In order to clear all locations of their programmed con-

tents, the device must be exposed to an ultraviolet light

source. A dosage of 15 W seconds/cm

2

 is required to

completely erase the device. This dosage can be ob-

tained by exposure to an ultraviolet lamp—wavelength

of 2537 Å—with intensity of 12,000 µW/cm

2

 for 15 to 20

minutes. The device should be directly under and about

one inch from the source, and all filters should be re-

moved from the UV light source prior to erasure.

Note that all UV erasable devices will erase with light

sources having wavelengths shorter than 4000 Å, such

as fluorescent light and sunlight. Although the erasure

process happens over a much longer time period, ex-

posure to any light source should be prevented for

maximum system reliability. Simply cover the package

window with an opaque label or substance.

Device Programming

Upon delivery, or after each erasure, the device has

all of its bits in the “ONE”, or HIGH state. “ZEROs” are

loaded into the device through the programming pro-

cedure.

The device enters the programming mode when 12.75

±

 0.25  V is applied to the V

PP

 pin, and CE# and

PGM# are at V

IL

.

For programming, the data to be programmed is ap-

plied 16 bits in parallel to the data pins.

The flowchar t in the Programming section of the

EPROM Products Data Book (Section 5, Figure 5-1)

shows AMD’s Flashrite algorithm. The Flashrite algo-

rithm reduces programming time by using a 100 µs pro-

gramming pulse and by giving each address only as

many pulses to reliably program the data. After each

pulse is applied to a given address, the data in that ad-

dress is verified. If the data does not verify, additional

pulses are given until it verifies or the maximum pulses

allowed is reached. This process is repeated while se-

quencing through each address of the device. This part

of the algorithm is done at V

CC

 = 6.25 V to assure that

each EPROM bit is programmed to a sufficiently high

threshold voltage. After the final address is completed,

the entire EPROM memory is verified at V

CC

 = V

PP

 =

5.25 V.

Please refer to Section 5 of the EPROM Products Data

Book for additional programming information and spec-

ifications.

Program Inhibit

Programming different data to multiple devices in par-

allel is easily accomplished. Except for CE#, all like in-

puts of the devices may be common. A TTL low-level

program pulse applied to one device’s CE# input with

V

PP

 = 12.75 V 

±

 0.25 V and PGM# LOW will program

that particular device. A high-level CE# input inhibits

the other devices from being programmed.

Program Verify

A verification should be performed on the programmed

bits to determine that they were correctly programmed.

The verify should be performed with OE# and CE# at

V

IL

, PGM# at V

IH

, and V

PP

 between 12.5 V and 13.0 V.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification through identifier codes on DQ0–

DQ7. This mode is primarily intended for programming

equipment to automatically match a device to be pro-

grammed with its corresponding programming algo-

rithm. This mode is functional in the 25

°

±

  5

°

C

ambient temperature range that is required when pro-

gramming the device.

To activate this mode, the programming equipment

must force V

H

 on address line A9. Two identifier bytes

may then be sequenced from the device outputs by tog-

gling address line A0 from V

IL

 to V

IH 

(that is, changing

the address from 00h to 01h). All other address lines

must be held at V

IL

 during the autoselect mode.

Byte 0 (A0 = V

IL

) represents the manufacturer code,

and Byte 1 (A0 = V

IH

), the device identifier code. Both

codes have odd parity, with DQ7 as the parity bit.

Read Mode

To obtain data at the device outputs, Chip Enable (CE#)

and Output Enable (OE#) must be driven low. CE# con-

trols the power to the device and is typically used to se-

lect the device. OE# enables the device to output data,

independent of device selection. Addresses must be

stable for at least t

ACC

–t

OE

.

 

Refer to the Switching

Waveforms section for the timing diagram.

Standby Mode

The device enters the CMOS standby mode when CE#

is at V

CC

 

±

 0.3 V. Maximum V

CC 

current is reduced to

100 µA. The device enters the TTL-standby mode

when CE# is at V

IH

. Maximum V

CC 

current is reduced

to 1.0 mA. When in either standby mode, the device

places its outputs in a high-impedance state, indepen-

dent of the OE# input.

Output OR-Tieing

To accommodate multiple memory connections, a

two-line control function provides:

s

Low memory power dissipation, and

s

Assurance that output bus contention will not occur.

CE# should be decoded and used as the primary de-

vice-selecting function, while OE# be made a common

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6

Am27C1024

connection to all devices in the array and connected to

the READ line from the system control bus. This as-

sures that all deselected memory devices are in their

low-power standby mode and that the output pins are

only active when data is desired from a particular mem-

ory device.

System Applications

During the switch between active and standby condi-

tions, transient current peaks are produced on the ris-

ing and falling edges of Chip Enable. The magnitude of

these transient current peaks is dependent on the out-

put capacitance loading of the device. At a minimum, a

0.1 µF ceramic capacitor (high frequency, low inherent

inductance) should be used on each device between

V

CC

 and V

SS

 to minimize transient effects. In addition,

to overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on EPROM ar-

rays, a 4.7 µF bulk electrolytic capacitor should be used

between V

CC

 and V

SS

 for each eight devices. The loca-

tion of the capacitor should be close to where the

power supply is connected to the array.

MODE SELECT TABLE

Notes:

1. V

= 12.0 V 

±

 0.5 V.

2. X = Either V

IH

 or V

IL

.

3. A1–A8 and A10–15 = V

IL

4. See DC Programming Characteristics for V

PP

 voltage during programming.

Mode

CE#

OE#

PGM#

A0

A9

V

PP

Outputs

Read

V

IL

V

IL

X

X

X

X

D

OUT

Output Disable

X

V

IH

X

X

X

X

High Z

Standby (TTL)

V

IH

X

X

X

X

X

High Z

Standby (CMOS)

V

CC

 

±

 0.3 V

X

X

X

X

X

High Z

Program

V

IL

X

V

IL

X

X

V

PP

D

IN

Program Verify

V

IL

V

IL

V

IH

X

X

V

PP

D

OUT

Program Inhibit

V

IH

X

X

X

X

V

PP

High Z

Autoselect 

(Note 3)

Manufacturer Code

V

IL

V

IL

V

IH

V

IL

V

H

X

01h

Device Code

V

IL

V

IL

V

IH

V

IH

V

H

X

8Ch

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Am27C1024

7

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

OTP Products. . . . . . . . . . . . . . . . . . –65

°

C to +125

°

C

All Other Products  . . . . . . . . . . . . . . –65

°

C to +150

°

C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55

°

C to +125

°

C

Voltage with Respect to V

SS

All pins except A9, V

PP

, V

CC

 . .  –0.6 V to V

CC

 + 0.6 V

A9 and V

PP

 (Note 2)  . . . . . . . . . . . . . –0.6 V to 13.5 V

V

CC 

(Note 1). . . . . . . . . . . . . . . . . . . . . –0.6 V to 7.0 V

Notes:

1. Minimum DC voltage on input or I/O pins –0.5 V. During

voltage transitions, the input may overshoot V

SS

 to –2.0 V

for periods of up to 20 ns. Maximum DC voltage on input

and I/O pins is V

CC

 + 5 V. During voltage transitions, input

and I/O pins may overshoot to V

CC

 + 2.0 V for periods up

to 20  ns.

2. Minimum DC input voltage on A9 is –0.5 V. During voltage

transitions, A9 and V

PP

 may overshoot V

SS

 

to –2.0 V for

periods of up to 20 ns. A9 and V

PP 

must not exceed +13.5

V at any time.

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these

or any other conditions above those indicated in the opera-

tional sections of this specification is not implied. Exposure of

the device to absolute maximum ratings for extended periods

may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T

A

)  . . . . . . . . . . .0

°

C to +70

°

C

Industrial (I) Devices

Ambient Temperature (T

A

)  . . . . . . . . .–40

°

C to +85

°

C

Extended (E) Devices

Ambient Temperature (T

A

)  . . . . . . . .–55

°

C to +125

°

C

Supply Read Voltages

V

CC

 for ± 5% devices  . . . . . . . . . .  +4.75 V to +5.25 V

V

CC

 for ± 10% devices  . . . . . . . . .  +4.50 V to +5.50 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

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8

Am27C1024

DC CHARACTERISTICS over operating range (unless otherwise specified)

Caution: The device must not be removed from (or inserted into) a socket when V

CC

 or V

PP

 is applied.

Notes:

1. V

CC

 must be applied simultaneously or before V

PP

, and removed simultaneously or after V

PP

..

2. I

CC1

 is tested with OE# = V

IH 

to simulate open outputs.

3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns. 

Maximum DC Voltage on output pins is V

CC

 + 0.5 V, which may overshoot to V

CC

 + 2.0 V for periods less than 20 ns.

Figure 1.

Typical Supply Current vs. Frequency

V

CC

 = 5.5 V, T = 25

°

C

Figure 2.

Typical Supply Current vs. Temperature

V

CC

 = 5.5 V, f = 10 MHz

Parameter 

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

V

OH

Output HIGH Voltage

I

OH

 = –400 µA

2.4

V

V

OL

Output LOW Voltage

I

OL

 = 2.1 mA

0.45

V

V

IH

Input HIGH Voltage

2.0

V

CC

 + 0.5

V

V

IL

Input LOW Voltage

–0.5

+0.8

V

I

LI

Input Load Current

V

IN

 = 0 V to V

CC

C/I Devices

1.0

µA

E Devices

5.0

I

LO

Output Leakage Current

V

OUT

 = 0 V to V

CC

5.0

µA

I

CC1

V

CC

 Active Current (Note 2)

CE# = V

IL

, f = 10 MHz, 

I

OUT

 = 0 mA

C/I Devices

50

mA

E Devices

60

I

CC2

V

CC

 TTL Standby Current

CE# = V

IH

1.0

mA

I

CC3

V

CC

 CMOS Standby Current

CE# = V

CC

 

±

 0.3 V

100

µA

I

PP1

V

PP

 Supply Current (Read)

CE# = OE# = V

IL

, V

PP

 = V

CC

100

µA

06780J-5

1

2

3

4

5

6

7

8

9

10

40

35

30

25

20

Frequency in MHz

S

upp

ly C

u

rrent

in m

A

06780J-6

–75 –50 –55

0

25

50

75 100 125 150

40

35

30

25

20

Temperature in 

°

C

S

upp

ly C

urr

ent

in

 mA

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Am27C1024

9

TEST CONDITIONS

Table 1.

Test Specifications

SWITCHING TEST WAVEFORM

KEY TO SWITCHING WAVEFORMS 

2.7 k

C

L

6.2 k

5.0 V

Device

Under

Test

06780J-7

Figure 3.

Test Setup

Note:

Diodes are IN3064 or equivalents.

Test Condition

-55

All

others

Unit

Output Load

1 TTL gate 

Output Load Capacitance, C

L

(including jig capacitance) 

30

100

pF

Input Rise and Fall Times

 20

ns

Input Pulse Levels

0.0–3.0

0.45–2.4

V

Input timing measurement 

reference levels

1.5 

0.8, 2.0

V

Output timing measurement 

reference levels

1.5

0.8, 2.0

V

2.4 V

0.45 V

Input

Output

Test Points

2.0 V

2.0 V

0.8 V

0.8 V

06780J-8

Note: For C

L

 = 100 pF.

3 V

0 V

Input

Output

1.5 V

1.5 V

Test Points

Note: For C

L

 = 30 pF.

KS000010-PAL

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Changing, State Unknown

Does Not Apply

Center Line is High Impedance State (High Z) 

background image

10

Am27C1024

AC CHARACTERISTICS

Caution: Do not remove the device from (or insert it into) a socket or board that has V

PP

 or V

CC 

applied.

Notes:

1. V

CC

 must be applied simultaneously or before V

PP

, and removed simultaneously or after V

PP

.

2. This parameter is sampled and not 100% tested.

3. Switching characteristics are over operating range, unless otherwise specified.

4. See Figure 3 and Table 1 for test specifications.

SWITCHING WAVEFORMS

Notes:

1. OE# may be delayed up to t

ACC

 – t

OE

 after the falling edge of the addresses without impact on t

ACC

.

2. t

DF

 is specified from OE# or CE#, whichever occurs first.

PACKAGE CAPACITANCE

Notes:

1. This parameter is only sampled and not 100% tested.

2. T

A

 = +25

°

C, f = 1 MHz.

Parameter Symbols

Description

Test Setup

Am27C1024

Unit

JEDEC

Standard

-55

-70

-90

-120 -150 -200 -255

t

AVQV

t

ACC

Address to Output Delay

CE#, 

OE# = V

IL

Max

55

70

90

120

150

200

250

ns

t

ELQV

t

CE

Chip Enable to Output Delay

OE# = V

IL

Max

55

70

90

120

150

200

250

ns

t

GLQV

t

OE

Output Enable to Output Delay CE# = V

IL

Max

40

40

45

50

65

75

75

ns

t

EHQZ

t

GHQZ

t

DF

(Note 2)

Chip Enable High or Output 

Enable High to Output High Z, 

Whichever Occurs First

Max

30

30

40

50

50

50

50

ns

t

AXQX

t

OH

Output Hold Time from 

Addresses, CE# or OE#, 

Whichever Occurs First

Min

0

0

0

0

0

0

0

ns

Addresses

CE#

OE#

Output

06780J-9

Addresses Valid

High Z

High Z

t

CE

Valid Output 

2.4

0.45

2.0

0.8

2.0

0.8

t

ACC

 

(Note 1)

t

OE

t

DF

 (Note 2)

t

OH

Parameter Symbol

Parameter 

Description

Test Conditions

CDV040

PD 040

PL 044

Unit

Typ

Max

Typ

Max

Typ

Max

C

IN

Input Capacitance

V

IN

 = 0

9

12

7

12

8

10

pF

C

OUT

Output Capacitance

V

OUT 

=  0

12

14

11

14

11

14

pF

background image

Am27C1024

11

PHYSICAL DIMENSIONS*

CDV040—40-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)

* For reference only. BSC is an ANSI standard for Basic Space Centering.

PD 040—40-Pin Plastic Dual In-Line Package (measured in inches)

TOP VIEW

SIDE VIEW

END VIEW

INDEX AND

TERMINAL NO. 1

I.D. AREA

.565

.605

2.035

2.080

.005 MIN

.045

.065

.014

.026

.100 BSC

.015

.060

.160

.220

.125

.200

BASE PLANE

SEATING PLANE

.300 BSC

.600

BSC

.008

.018

94

°

105

°

.700

MAX

16-000038H-3

CDV040

DF11

3-30-95 ae

DATUM D

CENTER PLANE

DATUM D

CENTER PLANE

1

UV Lens

Pin 1 I.D.

2.040

2.080

.530

.580

.005 MIN

.045

.065

.090

.110

.140

.225

.120

.160

.014

.022

SEATING PLANE

.015

.060

16-038-SC_AF

PD 040

DG76

2-28-95 ae

40

21

20

.630

.700

0

°

10

°

.600

.625

.008

.015

background image

12

Am27C1024

PHYSICAL DIMENSIONS 

PL 044—44-Pin Plastic Leaded Chip Carrier (measured in inches)

l

REVISION SUMMARY FOR AM27C1024

Revision J

Global

Changed formatting to match current data sheets.

Distinctive Characteristics

Low power consumption: Changed 100 µA to 20 µA.

Trademarks

Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Flashrite is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

TOP VIEW

SEATING PLANE

.685

.695

.650

.656

Pin 1 I.D.

.685

.695

.650

.656

.026

.032

.050 REF

.042

.056

.062

.083

.013

.021

.590

.630

.500

REF

.009

.015

.165

.180

.090

.120

16-038-SQ

PL 044

EC80

11.3.97 lv

SIDE VIEW