background image

Philips Semiconductors

Product specification

 

 N-channel logic level TrenchMOS

 transistor PSMN004-25B, PSMN004-25P

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

V

DSS

 = 25 V

• Very low on-state resistance

• Fast switching

I

D

 = 75 A

• Low thermal resistance

R

DS(ON)

 

 4 m

 (V

GS

 = 10 V)

R

DS(ON)

 

 5 m

 (V

GS

 = 5 V)

GENERAL DESCRIPTION

SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in

each package at each voltage rating.

Applications:-

• d.c. to d.c. converters

• switched mode power supplies

The PSMN004-25P is supplied in the SOT78 (TO220AB) conventional leaded package.

The PSMN004-25B is supplied in the SOT404 surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404 (D

2

PAK)

PIN

DESCRIPTION

1

gate

2

drain

1

3

source

tab

drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DSS

Drain-source voltage

T

j

 = 25 ˚C to 175˚C

-

25

V

V

DGR

Drain-gate voltage

T

j

 = 25 ˚C to 175˚C; R

GS

 = 20 k

-

25

V

V

GS

Continuous gate-source

-

±

 16

V

voltage

V

GSM

Peak pulsed gate-source

T

j

 

 150 ˚C

-

±

 20

V

voltage

I

D

Continuous drain current

T

mb

 =  25 ˚C; V

GS

 = 5 V

-

75

2

A

T

mb

 = 100 ˚C; V

GS

 = 5 V

-

75

2

A

I

DM

Pulsed drain current

T

mb

 = 25 ˚C

-

240

A

P

D

Total power dissipation

T

mb

 = 25 ˚C

-

230

W

T

j

, T

stg

Operating junction and

- 55

175

˚C

storage temperature

d

g

s

1

3

tab

2

1 2 3

tab

It is not possible to make connection to pin:2 of the SOT404 package

maximum continuous current limited by package

January 2000

1

Rev 1.200

background image

Philips Semiconductors

Product specification

 

 N-channel logic level TrenchMOS

 transistor

PSMN004-25B, PSMN004-25P

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN.

TYP. MAX. UNIT

R

th j-mb

Thermal resistance junction

-

-

0.65

K/W

to mounting base

R

th j-a

Thermal resistance junction

SOT78 package, vertical in still air

-

60

-

K/W

to ambient

SOT404 package, pcb mounted, minimum

-

50

-

K/W

footprint

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

E

AS

Non-repetitive avalanche

Unclamped inductive load, I

AS

 = 75 A;

-

120

mJ

energy

t

p

 = 100 

µ

s; T

j

 prior to avalanche = 25˚C;

V

DD

 

 15 V; R

GS

 = 50 

; V

GS

 = 5 V

I

AS

Non-repetitive avalanche

-

75

A

current

ELECTRICAL CHARACTERISTICS

T

j

= 25˚C  unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN.

TYP. MAX. UNIT

V

(BR)DSS

Drain-source breakdown

V

GS

 = 0 V; I

D

 = 0.25 mA;

25

-

-

V

voltage

T

j

 = -55˚C

22

-

-

V

V

GS(TO)

Gate threshold voltage

V

DS

 = V

GS

; I

D

 = 1 mA

1

1.5

2

V

 T

j

 = 175˚C

0.5

-

-

V

T

j

 = -55˚C

-

-

2.3

V

R

DS(ON)

Drain-source on-state

V

GS

 = 10 V; I

D

 = 25 A

-

3.5

4

m

resistance

V

GS

 = 5 V; I

D

 = 25 A

-

4

5

m

V

GS

 = 4.5 V; I

D

 = 25 A

-

-

5.4

m

V

GS

 = 5 V; I

D

 = 25 A; T

j

 = 175˚C

-

-

9.25

m

I

GSS

Gate-source leakage current V

GS

 = 

±

 10 V; V

DS

 = 0 V;

-

0.02

100

nA

I

DSS

Zero gate voltage drain

V

DS

 = 25 V; V

GS

 = 0 V;

-

0.05

10

µ

A

current

 T

j

 = 175˚C

-

-

500

µ

A

Q

g(tot)

Total gate charge

I

= 75 A; V

DD 

= 15 V; V

GS

 = 5 V

-

97

-

nC

Q

gs

Gate-source charge

-

20

-

nC

Q

gd

Gate-drain (Miller) charge

-

39

-

nC

t

d on

Turn-on delay time

V

DD

 = 15 V; R

D

 = 1.2 

-

45

-

ns

t

r

Turn-on rise time

V

GS

 = 5 V; R

G

 = 5.6 

-

220

-

ns

t

d off

Turn-off delay time

Resistive load

-

435

-

ns

t

f

Turn-off fall time

-

320

-

ns

L

d

Internal drain inductance

Measured tab to centre of die

-

3.5

-

nH

L

d

Internal drain inductance

Measured from drain lead to centre of die

-

4.5

-

nH

(SOT78 package only)

L

s

Internal source inductance

Measured from source lead to source

-

7.5

-

nH

bond pad

C

iss

Input capacitance

V

GS

 = 0 V; V

DS

 = 20 V; f = 1 MHz

-

6000

-

pF

C

oss

Output capacitance

-

1700

-

pF

C

rss

Feedback capacitance

-

1400

-

pF

January 2000

2

Rev 1.200

background image

Philips Semiconductors

Product specification

 

 N-channel logic level TrenchMOS

 transistor

PSMN004-25B, PSMN004-25P

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

T

j

 = 25˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN.

TYP. MAX. UNIT

I

S

Continuous source current

-

-

75

A

(body diode)

I

SM

Pulsed source current (body

-

-

240

A

diode)

V

SD

Diode forward voltage

I

F

 = 25 A; V

GS

 = 0 V

-

0.85

1.2

V

I

F

 = 75 A; V

GS

 = 0 V

-

1.1

-

t

rr

Reverse recovery time

I

F

 = 20 A; -dI

F

/dt = 100 A/

µ

s;

-

400

-

ns

Q

rr

Reverse recovery charge

V

GS

 = 0 V; V

R

 = 25 V

-

1

-

µ

C

January 2000

3

Rev 1.200

background image

Philips Semiconductors

Product specification

 

 N-channel logic level TrenchMOS

 transistor

PSMN004-25B, PSMN004-25P

Fig.1.   Normalised power dissipation.

PD% = 100

P

D

/P

D 25 ˚C 

= f(T

mb

)

Fig.2.   Normalised continuous drain current.

ID% = 100

I

D

/I

D 25 ˚C 

= f(T

mb

)

Fig.3.   Safe operating area. T

mb

 = 25 ˚C

I

D

 & I

DM

 = f(V

DS

); I

DM

 single pulse; parameter t

p

Fig.4.  Transient thermal impedance.

Z

th j-mb

 = f(t); parameter D = t

p

/T

Fig.5.  Typical output characteristics, T

j

 = 25 ˚C.

I

D

 = f(V

DS

)

Fig.6.   Typical on-state resistance, T

j

 = 25 ˚C.

R

DS(ON)

 = f(I

D

)

Normalised Power Derating, PD (%)

0

10

20

30

40

50

60

70

80

90

100

0

25

50

75

100

125

150

175

Mounting Base temperature, Tmb (C)

0.001

0.01

0.1

1

1E-06

1E-05

1E-04

1E-03

1E-02

1E-01

1E+00

Pulse width, tp (s)

Transient thermal impedance, Zth j-mb (K/W)

single pulse

D = 0.5

0.2

0.1

0.05

0.02

tp

D = tp/T

D

P

T

Normalised Current Derating, ID (%)

0

10

20

30

40

50

60

70

80

90

100

0

25

50

75

100

125

150

175

Mounting Base temperature, Tmb (C)

0

10

20

30

40

50

60

70

80

90

100

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

Drain-Source Voltage, VDS (V)

Drain Current, ID (A)

2.4 V

Tj = 25 C

VGS = 2.6 V

2.8 V

4.5 V

1.8 V

2 V

10 V

2.2 V

5 V

1

10

100

1000

1

10

100

Drain-Source Voltage, VDS (V)

Peak Pulsed Drain Current, IDM (A)

D.C.

100 ms

10 ms

RDS(on) = VDS/ ID

1 ms

tp = 10 us

100 us

0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.02

0

10

20

30

40

50

60

70

80

90

100

Drain Current, ID (A)

Drain-Source On Resistance, RDS(on) (Ohms)

VGS = 10V

Tj = 25 C

2.6 V

5 V

2.4 V

2.8 V

2 V

2.2 V

4.5 V

January 2000

4

Rev 1.200

background image

Philips Semiconductors

Product specification

 

 N-channel logic level TrenchMOS

 transistor

PSMN004-25B, PSMN004-25P

Fig.7.   Typical transfer characteristics.

I

D

 = f(V

GS

)

Fig.8.   Typical transconductance, T

j

 = 25 ˚C.

g

fs

 = f(I

D

)

Fig.9.   Normalised drain-source on-state resistance.

R

DS(ON)

/R

DS(ON)25 ˚C 

= f(T

j

)

Fig.10.   Gate threshold voltage.

V

GS(TO)

 = f(T

j

); conditions: I

D

 = 1 mA; V

DS

 = V

GS

Fig.11.   Sub-threshold drain current.

I

D

 = f(V

GS)

; conditions: T

j

 = 25 ˚C; V

DS

 = V

GS

Fig.12.   Typical capacitances, C

iss

, C

oss

, C

rss

.

C = f(V

DS

); conditions: V

GS

 = 0 V; f = 1 MHz

0

10

20

30

40

50

60

70

80

90

100

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

3

Gate-source voltage, VGS (V)

Drain current, ID (A)

VDS > ID X RDS(ON)

Tj = 25 C

175 C

Threshold Voltage, VGS(TO) (V)

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

2.25

-60

-40

-20

0

20

40

60

80

100

120

140

160

180

Junction Temperature, Tj (C)

typical

maximum

minimum

0

20

40

60

80

100

120

140

0

10

20

30

40

50

60

70

80

90

100

Drain current, ID (A)

Transconductance, gfs (S)

Tj = 25 C

175 C

VDS > ID X RDS(ON)

Drain current, ID (A)

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

0

0.5

1

1.5

2

2.5

3

Gate-source voltage, VGS (V)

minimum

typical

maximum

VDS = 5 V

Normalised On-state Resistance

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2

-60

-40

-20

0

20

40

60

80

100

120

140

160

180

Junction temperature, Tj (C)

1000

10000

100000

0.1

1

10

100

Drain-Source Voltage, VDS (V)

Capacitances, Ciss, Coss, Crss (pF)

Ciss

Coss

Crss

January 2000

5

Rev 1.200

background image

Philips Semiconductors

Product specification

 

 N-channel logic level TrenchMOS

 transistor

PSMN004-25B, PSMN004-25P

Fig.13.  Typical turn-on gate-charge characteristics.

V

GS 

= f(Q

G

)

Fig.14.   Typical reverse diode current.

I

F

 = f(V

SDS

); conditions: V

GS 

= 0 V; parameter T

j

Fig.15.  Maximum permissible non-repetitive

avalanche current (I

AS

) versus avalanche time (t

AV

);

unclamped inductive load

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0

25

50

75

100

125

150

175

200

225

250

Gate charge, QG (nC)

Gate-source voltage, VGS (V)

ID = 75 A

Tj = 25 C

VDD = 15 V

1

10

100

0.001

0.01

0.1

1

10

Avalanche time, t

AV

 (ms)

Maximum Avalanche Current, I

AS

 (A)

Tj prior to avalanche = 150 C

25 C

0

10

20

30

40

50

60

70

80

90

100

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

Source-Drain Voltage, VSDS (V)

Source-Drain Diode Current, IF (A)

Tj = 25 C

175 C

VGS = 0 V

January 2000

6

Rev 1.200

background image

Philips Semiconductors

Product specification

 

 N-channel logic level TrenchMOS

 transistor

PSMN004-25B, PSMN004-25P

MECHANICAL DATA

Fig.16.  SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static

discharge during transport or handling.

2. Refer to mounting instructions for SOT78 (TO220AB) package.

3. Epoxy meets UL94 V0 at 1/8".

 REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

 IEC

 JEDEC

 EIAJ

 SOT78

TO-220

D

D1

q

P

L

1

2

3

L2

(1)

b1

e

e

b

0

5

10 mm

scale

Plastic single-ended package; heatsink mounted; 1 mounting hole;  3-lead TO-220

SOT78

DIMENSIONS (mm are the original dimensions)

A

E

A1

c

Note

1. Terminals in this zone are not tinned.

Q

L1

UNIT

A1

b1

D1

e

P

mm

2.54

q

Q

A

b

D

c

L2

(1)

max.

3.0

3.8

3.6

15.0

13.5

3.30

2.79

3.0

2.7

2.6

2.2

0.7

0.4

15.8

15.2

0.9

0.7

1.3

1.0

4.5

4.1

1.39

1.27

6.4

5.9

10.3

9.7

L1

E

L

97-06-11

January 2000

7

Rev 1.200

background image

Philips Semiconductors

Product specification

 

 N-channel logic level TrenchMOS

 transistor

PSMN004-25B, PSMN004-25P

MECHANICAL DATA

Fig.17.  SOT404 surface mounting package. Centre pin connected to mounting base.

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static

discharge during transport or handling.

2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.

3. Epoxy meets UL94 V0 at 1/8".

UNIT

A

 REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

 IEC

 JEDEC

 EIAJ

mm

A1

D1

D

max.

E

e

Lp

HD

Q

c

2.54

2.60

2.20

15.40

14.80

2.90

2.10

11

1.60

1.20

10.30

9.70

4.50

4.10

1.40

1.27

0.85

0.60

0.64

0.46

b

DIMENSIONS (mm are the original dimensions)

 SOT404

0

2.5

5 mm

scale

Plastic single-ended surface mounted package (Philips version of D

2

-PAK); 3 leads

(one lead cropped)

SOT404

e

e

E

b

D1

HD

D

Q

Lp

c

A1

A

1

3

2

mounting

base

98-12-14

99-06-25

January 2000

8

Rev 1.200

background image

Philips Semiconductors

Product specification

 

 N-channel logic level TrenchMOS

 transistor

PSMN004-25B, PSMN004-25P

MOUNTING INSTRUCTIONS

Dimensions in mm

Fig.18.  SOT404 : soldering pattern for surface mounting.

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134).  Stress above one

or more of the limiting values may cause permanent damage to the device.  These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied.  Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 2000

All rights are reserved.  Reproduction in whole or in part is prohibited without the prior written consent of the

copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice.  No liability will be accepted by the publisher for any

consequence of its use.  Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury.  Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

17.5

11.5

9.0

5.08

3.8

2.0

January 2000

9

Rev 1.200