background image

1

TQFP

Top View

2 3

1

I N D E X

C O R N E R

3 4

OE

2/I

OE

1/I

I/O

GCLR/I

4 2

4 3

4 0

4 1

6

5

4

4 4

3

2

2 6

2 5

2 8

2 7

2 4

1 8

1 9

2 0

2 1

2 2

I / O

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

2 9

3 0

3 9

3 8

3 7

3 6

3 5

3 3

3 2

3 1

GND

GND

CLK/I

I/O

I / O

V C C

V C C

G N D

VCC

VCC

G N D

I / O

I / O

I / O

I / O

I / O

I / O

I / O

I / O

I / O

I / O

I / O

I / O

I / O

I / O

I / O

I / O

I/O

I/O/PD

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

PLCC

Top View

Pin Configurations

Pin 

Name

Function

CLK

Clock

I

Logic Inputs

I/O

Bidirectional 

Buffers

GCLR

Register Reset 

(active low)

OE1, 

OE2

Output Enable 

(active low)

V

CC

+5V Supply

PD

Power Down 

(active high)

Features

High Density, High Performance Electrically Erasable Complex 

Programmable Logic Device 

– 44-Pin, 32 I/O CPLD 

– 7.5 ns Maximum Pin-to-Pin Delay 

– Registered Operation Up To 125 MHz 

– Fully Connected Input and Feedback Logic Array

– Backward Compatibility with ATF1500/L Software and Hardware

Flexible Logic Macrocell 

D/T/Latch Configurable Flip Flops 

– Global and Individual Register Control Signals 

– Global and Individual Output Enable 

– Programmable Output Slew Rate 

Advanced Power Management Features 

– Automatic 3 mA Stand-By (ATF1500AL)

– Pin-Controlled 5 

µ

A Stand-By Mode (Typical) 

– Programmable Pin-Keeper Inputs and I/Os

Available in Commercial and Industrial Temperature Ranges

Available in 44-Pin PLCC and TQFP Packages

Advanced Flash Technology 

– 100% Tested 

– Completely Reprogrammable 

– 100 Program/Erase Cycles 

– 20 Year Data Retention 

– 2000V ESD Protection 

– 200 mA Latch-Up Immunity 

Supported By Popular 3rd Party Tools 

Security Fuse Feature

Description

The ATF1500A is a high performance, high density Complex PLD. Built on an

advanced Flash technology, it has maximum pin to pin delays of 7.5 ns and supports

sequential logic operation at speeds up to 125 MHz. With 32 logic macrocells and up

to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic PLDs.

The ATF1500A's global input and feedback architecture simplifies logic placement

and eliminates pinout changes due to design changes.

High 

Performance E

2

 

PLD

ATF1500A/AL

Rev. 0759C–04/98

(continued)

background image

ATF1500A/AL

2

Functional Logic Diagram

(1)

Note:

1.

Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.

background image

ATF1500A/AL

3

I/O Diagram

100K

V

CC

V

CC

DATA

OE

I/O

PROGRAMMABLE

OPTION

Input Diagram

100K

V

CC

ESD

PROTECTION

CIRCUIT

INPUT

PROGRAMMABLE

OPTION

The ATF1500A has 32 bi-directional I/O pins and 4 dedi-

cated input pins. Each dedicated input pin can also serve

as a global control signal: register clock, register reset or

output enable. Each of these control signals can be

selected for use individually within each macrocell.

Each of the 32 logic macrocells generates a buried feed-

back, which goes to the global bus. Each input and I/O pin

also feeds into the global bus. Because of this global bus-

sing, each of these signals is always available to all 32

macrocells in the device.

Each macrocell also generates a foldback logic term, which

goes to a regional bus. All signals within a regional bus are

connected to all 16 macrocells within the region.

Cascade logic between macrocells in the ATF1500A allows

fast, efficient generation of complex logic functions. The

ATF1500A contains 4 such logic chains, each capable of

creating sum term logic with a fan in of up to 40 product

terms. 

Bus Friendly Pin-Keeper Input and I/O’s

All Input and I/O pins on the ATF1500A have programma-

ble “data keeper” circuits. If activated, when any pin is

driven high or low and then subsequently left floating, it will

stay at that previous high or low level. 

This circuitry prevents unused Input and I/O lines from

floating to intermediate voltage levels, which cause unnec-

essary power consumption and system noise. The keeper

circuits eliminate the need for external pull-up resistors and

eliminate their DC power consumption. 

Pin-keeper circuits can be disabled. Programming is con-

trolled in the logic design file. Once the pin-keeper circuits

are disabled, normal termination procedures are required

for unused inputs and I/Os.

Speed/Power Management

The ATF1500A has several built-in speed and power man-

agement features. The ATF1500A contains circuitry that

automatically puts the device into a low power stand-by

mode when no logic transitions are occurring. This not only

reduces power consumption during inactive periods, but

also provides a proportional power savings for most appli-

cations running at system speeds below 10 MHz.

All ATF1500As also have an optional pin-controlled power

down mode. In this mode, current drops to below 10 

µ

A.

When the power down option is selected, the PD pin is

used to power down the part. The power down option is

selected in the design source file. When enabled, the

device goes into power down when the PD pin is high. In

the power down mode, all internal logic signals are latched

and held, as are any enabled outputs. All pin transitions are

ignored until the PD is brought low. When the power down

feature is enabled, the PD cannot be used as a logic input

or output. However, the PD pin's macrocell may still be

used to generate buried foldback and cascade logic sig-

nals.

Each output also has individual slew rate control. This may

be used to reduce system noise by slowing down outputs

that do not need to operate at maximum speed. Outputs

default to slow switching, and may be specified as fast

switching in the design file. 

Design Software Support

ATF1500A designs are supported by several 3rd party

tools. Automated fitters allow logic synthesis using a variety

of high level description languages and formats.

background image

ATF1500A/AL

4

ATF1500A/AL Macrocell

ATF1500A Macrocell

The ATF1500A macrocell is flexible enough to support

highly complex logic functions operating at high speed. The

macrocell consists of five sections: product terms and prod-

uct term select multiplexer; OR/XOR/CASCADE logic; a flip

flop; output select and enable; and logic array inputs.

Product Terms and Select Mux

Each ATF1500A macrocell has five product terms. Each

product term receives as its inputs all signals from both the

global bus and regional bus. 

The product term select multiplexer (PTMUX) allocates the

five product terms as needed to the macrocell logic gates

and control signals. The PTMUX programming is deter-

mined by the design compiler, which selects the optimum

macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1500A macrocell's OR/XOR/CASCADE logic

structure is designed to efficiently support all types of logic.

Within a single macrocell, all the product terms can be

routed to the OR gate, creating a five input AND/OR sum

term. With the addition of the CASIN from neighboring

macrocells, this can be expanded to as many as 40 product

terms with a very small additional delay.

The macrocell's XOR gate allows efficient implementation

of compare and arithmetic functions. One input to the XOR

comes from the OR sum term. The other XOR input can be

a product term or a fixed high or low level. For combinato-

rial outputs, the fixed level input allows output polarity

selection. For registered functions, the fixed levels allow De

Morgan minimization of the product terms. The XOR gate is

also used to emulate JK type flip flops.

Flip Flop

The ATF1500A's flip flop has very flexible data and control

functions. The data input can come from either the XOR

gate or from a separate product term. Selecting the sepa-

rate product term allows creation of a buried registered

feedback within a combinatorial output macrocell.

(continued)

background image

ATF1500A/AL

5

In addition to D, T, JK and SR operation, the flip flop can

also be configured as a flow-through latch. In this mode,

data passes through when the clock is high and is latched

when the clock is low. 

The clock itself can be either the global CLK pin or an indi-

vidual product term. The flip flop changes state on the

clock's rising edge. When the CLK pin is used as the clock,

one of the macrocell product terms can be selected as a

clock enable. When the clock enable function is active and

the enable signal (product term) is low, all clock edges are

ignored.

The flip flop's asynchronous reset signal (AR) can be either

the pin global clear (GCLR), a product term, or always off.

AR can also be a logic OR of GCLR with a product term.

The asynchronous preset (AP) can be a product term or

always off.

Output Select and Enable

The ATF1500A macrocell output can be selected as regis-

tered or combinatorial. When the output is registered, the

same registered signal is fed back internally to the global

bus. When the output is combinatorial, the buried feedback

can be either the same combinatorial signal or it can be the

register output if the separate product term is chosen as

the flip flop input.

The output enable multiplexer (MOE) controls the output

enable signals. Any buffer can be permanently enabled for

simple output operation. Buffers can also be permanently

disabled to allow use of the pin as an input. In this configu-

ration all the macrocell resources are still available, includ-

ing the buried feedback, expander and CASCADE logic.

The output enable for each macrocell can also be selected

as either of the two OE pins or as an individual product

term.

Global/Regional Busses

The global bus contains all Input and I/O pin signals as well

as the buried feedback signal from all 32 macrocells.

Together with the complement of each signal, this provides

a 68 bit bus as input to every product term. Having the

entire global bus available to each macrocell eliminates any

potential routing problems. With this architecture designs

can be modified without requiring pinout changes.

Each macrocell also generates a foldback product term.

This signal goes to the regional bus, and is available to 16

macrocells. The foldback is an inverse polarity of one of the

macrocell's product terms. The 16 foldback terms in each

region allow generation of high fan-in sum terms (up to 21

product terms) with a small additional delay.

background image

ATF1500A/AL

6

Note:

1. All I

CC

 parameters measured with outputs open, and a 16-bit loadable, up/down counter programmed into each region.

Absolute Maximum Ratings*

Temperature Under Bias .................................. -40°C to +85°C

*NOTICE:

Stresses beyond those listed under “Absolute 

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and 

functional operation of the device at these or any 

other conditions beyond those indicated in the 

operational sections of this specification is not 

implied.  Exposure to absolute maximum rating 

conditions for extended periods may affect device 

reliability.

Note:

1.

Minimum voltage is -0.6V dc, which may under-

shoot to -2.0V for pulses of less than 20 ns. Max-

imum output pin voltage is Vcc+ 0.75V dc, which 

may overshoot to 5.25V for pulses of less than 20 

ns.

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin with 

Respect to Ground ........................................ -2.0V to +7.0V

(1)

Voltage on Input Pins 

with Respect to Ground 

During Programming.................................... -2.0V to +14.0V

(1)

Programming Voltage with 

Respect to Ground ...................................... -2.0V to +14.0V

(1)

DC and AC Operating Conditions

Commercial

Industrial

Operating Temperature(case)

0

°

C - 70

°

C

-40

°

C - 85

°

C

VCC Power Supply

5V 

±

 5%

5V 

±

 10%

DC Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

I

IL

Input or I/O 

Low Leakage Current

≤ 

V

IN

 

≤ 

V

IL

(max)

-10

µ

A

I

IH

Input or I/O 

High Leakage Current

V

IH

,min 

≤ 

V

IN

 

≤ 

V

CC

10

µ

A

I

CC1

(1)

Power Supply Current,

Standby

V

CC

 = MAX, 

V

IN

 = 0, V

CC

ATF1500A

Com.

70

mA

Ind.

100

mA

ATF1500A

Com.

3

mA

Ind.

5

mA

I

CC2

Power Supply Current,

Power Down Mode

V

CC

 = MAX,

V

IN

 = 0, V

CC

5

µ

A

I

CC3

(1)

Clocked Power Supply

Current

V

CC

 = MAX, 

V

IN

 = 0, V

CC

ATF1500AL

2

mA/MHz

I

OS

Output Short Circuit

Current

V

OUT

 = 0.5V

-130

mA

V

IL

Input Low Voltage

V

CC

, min < V

CC

 

< V

CC

, max

-0.5

0.8

V

V

IH

Input High Voltage

2.0

V

CC

 + 1

V

V

OL

Output Low Voltage

V

CC

 = MIN

I

OL

 = 4 mA

0.45

V

V

OH

Output High Voltage

V

CC

 = MIN

I

OH

 = -4 mA

2.4

V

I

OH

 = -0.2 mA

V

CC

 - .2

V

background image

ATF1500A/AL

7

AC Waveforms

Note:

1. For slow slew outputs, add t

SSO

 .

Register AC Characteristics, Input Pin Clock

Symbol

Parameter

-7

-10

-12

-15

-20

-25

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

t

COS

(1)

Clock  to  Output

4.5

2

5

2

6

2

8

2

9

2

9

ns

t

CFS

Clock to Feedback

2

2

2

2

2

2

ns

t

SIS

I, I/O Setup Time

6

8

10

11

14

16

ns

t

SFS

Feedback Setup Time

6

8

10

11

12

13

ns

t

HS

Input, I/O, 

Feedback Hold Time

0

0

0

0

0

0

ns

t

PS

Clock Period

6

8

9

10

11

12

ns

t

WS

Clock  Width

3

4

4.5

5

5.5

6

ns

F

MAXS

External Feedback 

1/(t

SIS

 + t

COS

)

95

76.9

62.5

52.6

43

40

MHz

Internal Feedback 

1/(t

SFS

 + t

CFS

)

125

100

83.3

76.9

71

66

MHz

No Feedback 1/(t

PS

)

166.7

125

111

100

91

83

MHz

t

RPRS

Reset Pin Recovery 

Time

2

3

3

4

5

5

ns

t

RTRS

Reset Term Recovery 

Time

6

9

10

12

13

14

ns

background image

ATF1500A/AL

8

Note:

1. For slow slew outputs, add t

SSO 

.

Register AC Characteristics, Product Term Clock

Symbol

Parameter

-7

-10

-12

-15

-20

-25

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

t

COA

(1)

Clock  to  Output

7.5

10

12

15

18

20

ns

t

CFA

Clock to Feedback

5

7

7

9

12

15

ns

t

SIA

I, I/O Setup Time

3

3

4

4

8

10

ns

t

SFA

Feedback Setup Time

3

3

4

4

12

15

ns

t

HA

Input, I/O,

 Feedback Hold Time

2

3

4

4

5

5

ns

t

PA

Clock Period

6

8

10

12

24

30

ns

t

WA

Clock Width

3

4

5

6

12

15

ns

F

MAXA

External Feedback

 1/(t

SIA

 + t

COA

)

95.2

76.9

62.5

52.6

38

33.3

MHz

Internal Feedback

 1/(t

SFA

 + t

CFA

)

125

100

90.9

76.9

41.7

33.3

MHz

No Feedback 1/(t

PA

)

166.7

125

100

83.3

41.7

33.3

MHz

t

RPRA

Reset Pin 

Recovery Time

0

0

0

0

0

0

ns

t

RTRA

Reset Term 

Recovery Time

4

5

6

6

7

8

ns

background image

ATF1500A/AL

9

Note:

1. For slow slew outputs, add t

SSO 

.

AC Characteristics

Symbol

Parameter

-7

-10

-12

-15

-20

-25

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

t

PD

(1)

I, I/O or FB to 

Non-Registered 

Output

2

7.5

3

10

3

12

3

15

3

20

3

25

ns

t

PD2

 I, I/O to Feedback

5

7

8

9

12

14

ns

t

PD3

(1)

Feedback to 

Non-Registered 

Output

2

7.5

3

10

3

12

3

15

3

20

3

25

ns

t

PD4

Feedback to 

Feedback

5

7

8

9

12

14

ns

t

EA

(1)

OE Term to Output 

Enable

2

7.5

3

10

3

12

3

15

3

20

3

25

ns

t

ER

OE Term to Output

 Disable

2

7.5

2

10

2

12

2

15

2

20

2

25

ns

t

PZX

(1)

OE Pin to Output

 Enable

2

5.5

2

7

2

8

2

9

2

10

2

11

ns

t

PXZ

OE Pin to Output 

Disable

1.5

5.5

1..5

7

1.5

8

1.5

9

1.5

10

1.5

11

ns

t

PF

Preset to Feedback

6

9

9

12

18

20

ns

t

PO

(1)

Preset to Registered 

Output

8.5

12

14

20

23

25

ns

t

RPF

Reset Pin to 

Feedback

3

4

3

5

5.5

6

ns

t

RPO

(1)

Reset Pin to 

Registered Output

5.5

7

8

11

13

15

ns

t

RTF

Reset Term to 

Feedback

6

9

9

12

15

20

ns

t

RTO

(1)

Reset Term to 

Registered Output

8.5

12

14

20

23

25

ns

t

CAS

Cascade Logic Delay

0.8

0.8

1

1

1.5

1.5

ns

t

SSO

Slow Slew Output 

Adder

3

3

3

4

4

4

ns

t

FLD

Foldback Term Delay

4

5

7

8

10

12

ns

background image

ATF1500A/AL

10

Output Test Load

Input Test Waveforms and Measurement Levels

Notes:

1. For slow slew outputs, add t

SSO 

.

2. Pin or Product Term.

Power Down AC Characteristics

Symbol

Parameter

-7

-10

-12

-15

-20

-25

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

t

IVDH

Valid I, I/O Before

 PD High

7

10

12

15

20

25

ns

t

GVDH

Valid OE

(2)

 Before PD High

7

10

12

15

20

25

ns

t

CVDH

Valid Clock

(2)

 

Before PD High

7

10

12

15

20

25

ns

t

DHIX

Input Don't Care

 After PD High

15

20

22

25

30

35

ns

t

DHGX

 OE Don't Care

 After PD High

15

20

22

25

30

35

ns

t

DHCX

Clock Don't Care

 After PD High

15

20

22

25

30

35

ns

t

DLIV

PD Low to Valid I,

 I/O

1

1

1

1

1

1

µ

s

t

DLGV

PD Low to Valid

 OE

(2)

1

1

1

1

1

1

µ

s

t

DLCV

PD Low to Valid

 Clock

(2)

1

1

1

1

1

1

µ

s

t

DLOV

(1)

PD Low to Valid

 Output

1

1

1

1

1

1

µ

s

Note:

1. Typical values for nominal supply voltage.  This parameter is only sampled and is not 100% tested.

Pin Capacitance

f = 1 MHz, T = 25°C)

(1)

Typ

Max

Units

Conditions

C

IN

4.5

5.5

pF

V

IN

 = 0V

C

OUT

3.5

4.5

pF

V

OUT

 = 0V

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ATF1500A/AL

11

Power Up Reset

The ATF1500A's registers are designed to reset during

power up. At a point delayed slightly from V

CC

 crossing

V

RST

, all registers will be reset to the low state. As a result,

the registered output state will always be low on power-up.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the

uncertainty of how V

CC

 actually rises in the system, the fol-

lowing conditions are required:

1. The V

CC

 rise must be monotonic, from below .7 volts,

2. After reset occurs, all input and feedback setup times 

must be met before driving the clock signal high, and

3. Signals from which clocks are derived must remain sta-

ble during t

PR

Power Down Mode

The ATF1500A includes an optional pin controlled power

down feature. When this mode is enabled, the PD pin acts

as the power down pin. When the PD pin is high, the device

supply current is reduced to less than 10 

µ

A. During power

down, all output data and internal logic states are latched

and held. Therefore, all registered and combinatorial output

data remain valid. Any outputs which were in a HI-Z state at

the onset of power down will remain at HI-Z. During power

down, all input signals except the power down pin are

blocked. Input and I/O hold latches remain active to insure

that pins do not float to indeterminate levels, further reduc-

ing system power. The power down pin feature is enabled

in the logic design file. Designs using the power down pin

may not use the PD pin logic array input. However, all other

PD pin macrocell resources may still be used, including the

buried feedback and foldback product  term array inputs.

Register Preload

The ATF1500A's registers are provided with circuitry to

allow loading of each register with either a high or a low.

This feature will simplify testing since any state can be

forced into the registers to control test sequencing. A

JEDEC file with preload is generated when a source file

with preload vectors is compiled. Once downloaded, the

JEDEC file preload sequence will be done automatically

when vectors are run by any approved programmers.  The

preload mode is enabled by raising an input pin to a high

voltage level. Contact Atmel PLD Applications for PRE-

LOAD pin assignments, timing and voltage requirements. 

Output Slew Rate Control

Each ATF1500A macrocell contains a configuration bit for

each I/O to control its output slew rate. This allows selected

data paths to operate at maximum throughput while reduc-

ing system noise from outputs that are not speed-critical.

Outputs default to slow edges, and may be individually set

to fast in the design file. Output transition times for outputs

configured as “slow” have a t

SSO

 delay adder.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying

of the ATF1500A fuse patterns. Once programmed, fuse

verify and preload are prohibited. However, the 160-bit

User Signature remains accessible.

The security fuse should be programmed last, as its effect

is immediate. 

Parameter

Description

Typ

Max

Units

t

PR

Power-Up

Reset Time

2

10

µ

s

V

RST

Power-Up

Reset 

Voltage

3.8

4.5

V

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ATF1500A/AL

12

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ATF1500A/AL

13

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ATF1500A/AL

14

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ATF1500A/AL

15

Ordering Information

t

PD

(ns)

t

COS

 (ns)

F

MAXS

(MHz)

Ordering Code

Package

Operation Range

7.5

4.5

95

ATF1500A-7AC

ATF1500A-7JC

44A

44J

Commercial

(0

°

C to 70

°

C)

10

5

76.9

ATF1500A-10AC

ATF1500A-10JC

44A

44J

Commercial

(0

°

C to 70

°

C)

ATF1500A-10AI

ATF1500A-10JI

44A

44J

Industrial

(-40

°

C to 85

°

C)

12

6

62.5

ATF1500A-12AC

ATF1500A-12JC

44A

44J

Commercial

(0

°

C to 70

°

C)

ATF1500A-12AI

ATF1500A-12JI

44A

44J

Industrial

(-40

°

C to 85

°

C)

15

8

52.6

ATF1500A-15AC

ATF1500A-15JC

44A

44J

Commercial

(0

°

C to 70

°

C)

ATF1500A-15AI

ATF1500A-15JI

44A

44J

Industrial

(-40

°

C to 85

°

C)

20

9

40

ATF1500AL-20AC

ATF1500AL-20JC

44A

44J

Commercial

(0

°

C to 70

°

C)

ATF1500AL-20AI

ATF1500AL-20JI

44A

44J

Industrial

(-40

°

C to 85

°

C)

25

9

43

ATF1500AL-25AC

ATF1500AL-25JC

44A

44J

Commercial

(0

°

C to 70

°

C)

ATF1500AL-25AI

ATF1500AL-25JI

44A

44J

Industrial

(-40

°

C to 85

°

C)

Package Type

 44A

44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

 44J

44 Lead, Plastic J-Leaded Chip Carrier (PLCC)

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ATF1500A/AL

16

Packaging Information

*Controlling dimension: millimeters

.045(1.14) X 45°

PIN NO. 1

IDENTIFY

.045(1.14) X 30° - 45°

.012(.305)

.008(.203)

.021(.533)

.013(.330)

.630(16.0)

.590(15.0)

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.500(12.7) REF SQ

.032(.813)

.026(.660)

.050(1.27) TYP

.022(.559) X 45° MAX (3X)

.656(16.7)

.650(16.5)

.695(17.7)

.685(17.4)

SQ

SQ

44A, 44-Lead, Thin (1.0 mm)

Plastic Gull Wing Quad Flat Package (TQFP)

Dimensions in Millimeters and (Inches)*

44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

© Copyright Atmel Corporation 1997.

Atmel Corporation assumes no responsibility for the use of any circuitr y other than circuitry embodied in an

Atmel Cor poration product. No other circuit patent licenses are implied. Atmel Corporation’s products are not

authorized for use as critical components in life suppor t devices or systems.

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 Printed on recycled paper.

0759C–04/98/5M