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4-104

FAST AND LS TTL DATA

4-BIT PARALLEL

ACCESS SHIFT REGISTER

The functional characteristics of the MC74F195 4-Bit Parallel Access Shift

Register are indicated in the Logic Diagram and Function Table.  The device

is useful in a wide variety of shifting, counting, and storage applications.  It per-

forms serial, parallel, serial-to-parallel, or parallel-to-serial data transfers at

very high speeds.

The MC74F195 operates in two primary modes, shift right (Q0-Q1) and par-

allel load, which are controlled by the state of the Parallel Enable (PE) input.

Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE

input is HIGH, and is shifted 1 bit in the direction Q0-Q1-Q2-Q3 following each

LOW-to-HIGH clock transition.  The J and K inputs provide the flexibility of the

JK type input is made for special applications, and by tying the two pins togeth-

er  the simple D-type input is made for general applications.  The device ap-

pears as four common clocked D flip-flops when the PE input is LOW.  After

the LOW-to-HIGH clock transition, data on the parallel inputs (D0-D3) is trans-

ferred to the respective Q0-Q3 outputs.  Shift left operation (Q3-Q2) can be

achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input

LOW.

All parallel and serial data transfers are synchronous, occurring after each

LOW-to-HIGH clock transition.  The MC74F195 utilizes edge-triggering;

therefore, there is no restriction on the activity of the J, K, Dn, and PE inputs

for logic operation, other than the setup and hold time requirements.

A LOW on the asynchronous Master Reset (MR) input sets all Q outputs

LOW, independent of any other input condition.

Shift Right and Parallel Load Capability

J-K (D-Type) Inputs to First Stage

Complement Output from Last Stage

Asynchronous Master Reset

CONNECTION DIAGRAM DIP

15

16

14

13

12

11

10

2

1

3

4

5

6

7

VCC

9

8

Q0

Q1

Q2

Q3

Q3

CP

PE

MR

J

K

D0

D1

D2

D3

GND

MC74F195

4-BIT PARALLEL

ACCESS SHIFT REGISTER

FAST

 SCHOTTKY TTL

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

ORDERING INFORMATION

MC74FXXXJ

Ceramic

MC74FXXXN

Plastic

MC74FXXXD

SOIC

16

1

D SUFFIX

SOIC

CASE 751B-03

LOGIC SYMBOL

PE  D0  D1  D2  D3

J

K

CP

MR  Q0  Q1  Q2  Q3

Q3

VCC = PIN 16

GND = PIN 8

 9          5     6     7

2

3

10

11

 1   15   14   13  12

4

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4-105

FAST AND LS TTL DATA

MC74F195

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

74

4.5

5.0

5.5

V

TA

Operating Ambient Temperature Range

74

0

25

70

°

C

IOH

Output Current 

 High

74

–1.0

mA

IOL

Output Current 

Low

74

20

mA

S

R

RD

CP

Q

S

R

RD

CP

Q

Q

MR

CP

S

R

RD

CP

Q

Q0

Q1

Q2

Q3 Q3

D3

D2

D1

D0

J

K

PE

S

R

RD

CP

Q

Q

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Outputs

Operating Modes

MR

CP

PE

J

K

Dn

Q0

Q1

Q2

Q3

Q3

Asynchronous Reset

L

X

X

X

X

X

L

L

L

L

H

Shift, Set First Stage

H

h

h

h

X

H

q0

q1

q2

q2

Shift, Reset First Stage

H

h

l

l

X

L

q0

q1

q2

q2

Shift, Toggle First Stage

H

h

h

l

X

q0

q0

q1

q2

q2

Shift, Retain First Stage

H

h

l

h

X

q0

q0

q1

q2

q2

Parallel Load

H

l

X

X

dn

d0

d1

d2

d3

d3

H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

dn (qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition.

 = LOW-to-HIGH clock transition

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4-106

FAST AND LS TTL DATA

MC74F195

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

VIH

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage

VIK

Input Clamp Diode Voltage

–1.2

V

IIN = –18 mA

VCC = MIN

VOH

Output HIGH Voltage

74

2.5

V

IOH = –1.0 mA

VCC = 4.5 V

74

2.7

V

VCC = 4.75 V

VOL

Output LOW Voltage

0.5

V

IOL = 20 mA

VCC = 4.5 V

IIH

Input HIGH Current

20

µ

A

VIN = 2.7 V

VCC = MAX

100

VIN = 7.0 V

IIL

Input LOW Current

–0.6

mA

VCC = MAX

IOS

Output Short Circuit Current (Note 2)

–60

–150

mA

VOUT = 0 V

VCC = MAX

ICC

Power Supply Current

38

mA

VCC = MAX

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.

2. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS

54/74F

74F

 

TA = + 25

°

C

VCC = + 5.0 V

CL = 50 pF

TA = 0

°

C to + 70

°

C

VCC = 5.0 V 

±

 10%

CL = 50 pF

Symbol

 Parameter

Min

Max

Min

Max

Unit

fmax

105

90

MHz

tPLH

Propagation Delay

2.5

7.0

2.5

8.0

ns

tPHL

CP to Q/Q

2.5

8.0

2.5

9.0

tPHL

Propagation Delay, MR to Q

3.0

10

3.0

11

ns

tPLH

Propagation Delay, MR to Q

3.0

10.5

3.0

11

ns

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4-107

FAST AND LS TTL DATA

MC74F195

AC OPERATING REQUIREMENTS

74F

74F

 

TA = + 25

°

C

VCC = + 5.0 V

CL = 50 pF

TA = 0

°

C to + 70

°

C

VCC = 5.0 V 

±

 10%

CL = 50 pF

Symbol

 Parameter

Min

Max

Min

Max

Unit

ts (H)

Setup Time, HIGH or LOW J, K, D to CP

4.0

4.0

ns

ts (L)

4.0

4.0

th (H)

Hold Time, HIGH or LOW J, K, D to CP

0

1.0

ns

th (L)

0

1.0

ts (H)

Setup Time, HIGH or LOW PE to CP

8.0

9.0

ns

ts (L)

8.0

9.0

th (H)

Hold Time, HIGH or LOW PE to CP

0

0

ns

th (L)

0

0

tw (H)

CP Pulse Width, HIGH

5.0

5.5

ns

tw (L)

MR Pulse Width, LOW

5.0

5.0

ns

trec

Recovery Time, MR to CP

7.0

8.0

ns