background image

¡ Semiconductor

MSM51V17800D/DSL

1/17

DESCRIPTION

The MSM51V17800D/DSL is a 2,097,152-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate

CMOS technology. The MSM51V17800D/DSL achieves high integration, high-speed operation,

and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/

double-layer metal CMOS process. The MSM51V17800D/DSL is available in a 28-pin plastic SOJ or

28-pin plastic TSOP. The MSM51V17800DSL (the self-refresh version) is specially designed for

lower-power applications.

FEATURES

• 2,097,152-word ¥ 8-bit configuration

• Single  3.3 V power supply, 

±

0.3 V tolerance

• Input

: LVTTL compatible, low input capacitance

• Output : LVTTL compatible, 3-state

• Refresh : 2048 cycles/32 ms, 2048 cycles/128 ms (SL version)

• Fast page mode, read modify write capability

• CAS before RAS refresh, hidden refresh, RAS-only refresh capability

• CAS before RAS self-refresh capability (SL version)

• Multi-bit test mode capability

• Package options:

28-pin 400 mil plastic SOJ

(SOJ28-P-400-1.27)

(Product : MSM51V17800D/DSL-xxJS)

28-pin 400 mil plastic TSOP

(TSOPII28-P-400-1.27-K) (Product : MSM51V17800D/DSL-xxTS-K)

xx indicates speed rank.

PRODUCT FAMILY

¡ Semiconductor

MSM51V17800D/DSL

2,097,152-Word 

¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE

MSM51V17800D/DSL-70 70 ns

130 ns

90 ns

288 mW

360 mW

Family

Access Time (Max.)

Cycle Time

(Min.)

Standby (Max.)

Power Dissipation 

MSM51V17800D/DSL-50

t

RAC

50 ns

35 ns

t

AA

25 ns

20 ns

t

CAC

13 ns

20 ns

t

OEA

13 ns

MSM51V17800D/DSL-60 60 ns

110 ns

324 mW

30 ns

15 ns

15 ns

Operating (Max.)

1.8 mW/

0.72 mW (SL version)

Preliminary

E2G0127-17-61

This version:  Mar. 1998

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¡ Semiconductor

MSM51V17800D/DSL

2/17

PIN CONFIGURATION (TOP VIEW)

3

4

5

9

10

11

12

13

DQ2

DQ3

DQ4

A10R

A0

A1

A2

A3

26

25

24

20

19

18

17

16

DQ7

DQ6

DQ5

A8

A7

A6

A5

A4

2

DQ1

27 DQ8

1

V

CC

28 V

SS

28-Pin Plastic SOJ

3

4

5

9

10

11

12

13

26

25

24

20

19

18

17

16

2

27

1

28

28-Pin Plastic TSOP

(K Type)







6

WE

23 CAS

23

8

NC

21 A9

21

6

8

7

RAS

22 OE

22

7

14

V

CC

15 V

SS

14

15

DQ2

DQ3

DQ4

A10R

A0

A1

A2

A3

DQ1

V

CC

WE

NC

RAS

V

CC

DQ7

DQ6

DQ5

A8

A7

A6

A5

A4

DQ8

V

SS

CAS

A9

OE

V

SS

Pin Name

Function

A0 - A9, A10R

Address Input

RAS

Row Address Strobe

CAS

Column Address Strobe

DQ1 - DQ8

Data Input/Data Output

OE

Output Enable

WE

Write Enable

V

CC

Power Supply (3.3 V)

V

SS

Ground (0 V)

NC

No Connection

Note :

The same power supply voltage must be provided to every V

CC

 pin, and the same GND

voltage level must be provided to every V

SS

 pin.

background image

¡ Semiconductor

MSM51V17800D/DSL

3/17

BLOCK DIAGRAM

Timing 

Generator

Refresh

Control Clock

Column

Address

Buffers

Internal

Address

Counter

Row

Address

Buffers

Row

Deco-

ders

Word

Drivers

Memory

Cells

Sense Amplifiers

Column Decoders

I/O

Controller

I/O

Selector

Output

Buffers

Input

Buffers

On Chip

V

BB

 Generator

V

CC

DQ1 - DQ8

CAS

WE

A0 - A9

10

10

8

8

8

8

8

8

11

10

OE

RAS

V

SS

1

A10R

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¡ Semiconductor

MSM51V17800D/DSL

4/17

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Recommended Operating Conditions

Capacitance

*: Ta = 25

°

C

Voltage on Any Pin Relative to V

SS

Short Circuit Output Current

Power Dissipation

Operating Temperature

Storage Temperature

V

T

Symbol

I

OS

P

D

*

T

opr

T

stg

–0.5 to 4.6

50

1

0 to 70

–55 to 150

Rating

mA

W

°C

°C

Parameter

V

Unit

Power Supply Voltage

Input High Voltage

Input Low Voltage

V

CC

Symbol

V

SS

V

IH

V

IL

3.3

0

Typ.

Parameter

3.0

0

2.0

–0.3

Min.

3.6

0

V

CC 

+ 0.3

0.8

Max.

(Ta = 0°C to 70°C)

V

Unit

V

V

V

Input Capacitance (A0 - A9, A10R) 

Input Capacitance (RAS, CAS, WE, OE)

Output Capacitance (DQ1 - DQ8)

C

IN1

Symbol

C

IN2

C

I/O

5

7

7

Max.

pF

Unit

pF

pF

Parameter

(V

CC

 = 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz)

Typ.

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¡ Semiconductor

MSM51V17800D/DSL

5/17

DC Characteristics

Parameter

Symbol

Condition

MSM51V17800

D/DSL-50

MSM51V17800

D/DSL-60

MSM51V17800

D/DSL-70

(V

CC

 = 3.3 V ±0.3 V, Ta = 0°C to 70°C)

I

OH

 = –2.0 mA

Output High Voltage

I

OL

 = 2.0 mA

Output Low Voltage

0 V £ V

I

 £ V

CC

 + 0.3 V;

All other pins not

Input Leakage Current

under test = 0 V

DQ disable

Output Leakage Current

0 V £ V

O

 £ V

CC

RAS, CAS cycling,

Average Power

t

RC

 = Min.

Supply Current

(Operating)

RAS, CAS = V

IH

Power Supply

RAS, CAS

Current (Standby)

RAS cycling,

Average Power

CAS = V

IH

,

Supply Current

t

RC

 = Min.

(RAS-only Refresh)

RAS = V

IH

,

Power Supply

CAS = V

IL

,

Current (Standby)

DQ = enable

Average Power

CAS before RAS

Supply Current

(CAS before RAS Refresh)

Average Power

RAS £ 0.2 V,

Supply Current

CAS £ 0.2 V

(CAS before RAS

V

OH

V

OL

I

LI

I

LO

I

CC1

I

CC2

I

CC3

I

CC5

I

CC6

I

CCS

≥ V

CC

 –0.2 V

Min.

Max.

Min.

Max.

Min.

Max.

Unit Note

RAS cycling,

2.4

0

–10

–10

V

CC

0.4

10

10

100

2

0.5

100

100

300

5

2.4

0

–10

–10

V

CC

0.4

10

10

90

2

0.5

90

90

300

5

2.4

0

–10

–10

V

CC

0.4

10

10

80

2

0.5

80

80

300

5

200

200

200

V

V

mA

mA

mA

mA

mA

mA

mA

mA

1, 2

1, 2

1, 2

1, 5

1

1

mA

1, 5

t

RC

 = 62.5 ms,

Average Power

CAS before RAS,

Supply Current

t

RAS

 £ 1 ms

(Battery Backup)

I

CC10

300

300

300

mA

1, 4,

RAS = V

IL

,

Average Power

CAS cycling,

Supply Current

t

PC

 = Min.

(Fast Page Mode)

I

CC7

75

70

65

mA

1, 3

5

Self-Refresh)

Notes : 1. I

CC

 Max. is specified as I

CC

 for output open condition.

2. The address can be changed once or less while RAS = V

IL

.

3. The address can be changed once or less while CAS = V

IH

.

4. V

CC

 – 0.2 V £ V

IH

 £ V

CC

 + 0.3 V, –0.3 V £ V

IL

 £ 0.2 V.

5. SL version.

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¡ Semiconductor

MSM51V17800D/DSL

6/17

AC Characteristics (1/2)

Parameter

MSM51V17800

D/DSL-60

MSM51V17800

D/DSL-70

MSM51V17800

D/DSL-50

(V

CC

 = 3.3 V ±0.3 V, Ta = 0°C to 70°C)  Note 1, 2, 3, 11, 12

Random Read or Write Cycle Time 

Read Modify Write Cycle Time

Fast Page Mode Cycle Time

Fast Page Mode Read Modify Write

Cycle Time

Access Time from RAS

Access Time from CAS

Access Time from Column Address

Access Time from CAS Precharge

CAS to Data Output Buffer Turn-off Delay Time

Transition Time

RAS Precharge Time

RAS Pulse Width

RAS Pulse Width (Fast Page Mode)

RAS Hold Time

CAS Pulse Width

CAS Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

CAS to RAS Precharge Time

Row Address Set-up Time

Row Address Hold Time

Column Address Set-up Time

Column Address Hold Time

Column Address to RAS Lead Time

Read Command Set-up Time

Read Command Hold Time

Read Command Hold Time referenced to RAS

Access Time from OE

OE to Data Output Buffer Turn-off Delay Time

Refresh Period

RAS Hold Time referenced to OE

Unit

Min.

Max.

Min.

Max.

RAS Hold Time from CAS Precharge

Symbol

t

RC

t

RWC

t

PC

t

PRWC

t

RAC

t

CAC

t

AA

t

CPA

t

OFF

t

T

t

RP

t

RAS

t

RASP

t

RSH

t

CAS

t

CSH

t

RCD

t

RAD

t

CRP

t

ASR

t

RAH

t

ASC

t

CAH

t

RAL

t

RCS

t

RCH

t

RRH

t

OEA

t

OEZ

t

REF

t

ROH

t

RHCP

Note

Min.

Max.

Output Low Impedance Time from CAS

t

CLZ

CAS Precharge Time (Fast Page Mode)

t

CP

4, 5, 6

4, 5

4, 6

4

7

5

6

8

8

4

7

4

3

13

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ms

ns

ns

90

131

35

76

0

0

3

30

50

50

13

7

13

50

17

12

5

0

7

0

7

25

0

0

0

0

13

30

50

13

25

30

13

50

10,000

100,000

10,000

37

25

13

13

32

130

185

45

100

0

0

3

50

70

70

20

10

20

70

20

15

5

0

10

0

15

35

0

0

0

0

20

40

70

20

35

40

20

50

10,000

100,000

10,000

50

35

20

20

32

110

155

40

85

0

0

3

40

60

60

15

10

15

60

20

15

5

0

10

0

10

30

0

0

0

0

15

35

60

15

30

35

15

50

10,000

100,000

10,000

45

30

15

15

32

Refresh Period (SL version)

t

REF

ms

128

128

128

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¡ Semiconductor

MSM51V17800D/DSL

7/17

AC Characteristics (2/2)

MSM51V17800

D/DSL-60

MSM51V17800

D/DSL-70

MSM51V17800

D/DSL-50

Write Command Pulse Width

Write Command to CAS Lead Time

Write Command to RAS Lead Time

Data-in Set-up Time

CAS to WE Delay Time

RAS to WE Delay Time

Column Address to WE Delay Time

RAS to CAS Hold Time (CAS before RAS)

CAS Active Delay Time from RAS Precharge

Data-in Hold Time

Write Command Hold Time

OE Command Hold Time

OE to Data-in Delay Time

(V

CC

 = 3.3 V ±0.3 V, Ta = 0°C to 70°C)  Note 1, 2, 3, 11, 12

Write Command Set-up Time

t

WP

t

CWL

t

RWL

t

DS

t

CWD

t

RWD

t

AWD

t

CHR

t

RPC

t

DH

t

WCH

t

OEH

t

OED

t

WCS

Min.

Max.

Parameter

Symbol

Unit Note

Min.

Max.

Min.

Max.

RAS to CAS Set-up Time (CAS before RAS) t

CSR

WE to RAS Precharge Time (CAS before RAS) t

WRP

WE Hold Time from RAS (CAS before RAS) t

WRH

RAS to WE Set-up Time (Test Mode)

t

WTS

CAS Precharge WE Delay Time

t

CPWD

RAS to WE Hold Time (Test Mode) 

t

WTH

10

9

9

9

10

9

9

10

10

10

10

10

15

15

0

40

85

55

10

10

5

10

10

15

15

0

60

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

10

10

10

10

7

13

13

0

36

73

48

10

10

5

7

7

13

13

0

53

10

10

10

10

10

20

20

0

50

100

65

10

10

5

15

15

20

20

0

70

RAS Pulse Width

t

RASS

13

100

ms

100

100

(CAS before RAS Self-Refresh)

RAS Precharge Time

t

RPS

13

110

ns

90

130

(CAS before RAS Self-Refresh)

CAS Hold Time

t

CHS

13

–50

ns

–50

–50

(CAS before RAS Self-Refresh)

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¡ Semiconductor

MSM51V17800D/DSL

8/17

Notes:

1. A start-up delay of 200 

µ

s is required after power-up, followed by a minimum of eight

initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device

operation is achieved.

2. The AC characteristics assume t

= 5 ns.

3. V

IH

 (Min.) and V

IL

 (Max.) are reference levels for measuring input timing signals.

Transition times (t

T

) are measured between V

IH

 and V

IL

.

4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF.

The output timing reference levels are V

OH

 = 2.0 V and V

OL

 = 0.8 V.

5. Operation within the t

RCD

 (Max.) limit ensures that t

RAC

 (Max.) can be met.

t

RCD

 (Max.) is specified as a reference point only. If t

RCD

 is greater than the specified

t

RCD

 (Max.) limit, then the access time is controlled by t

CAC

.

6. Operation within the t

RAD

 (Max.) limit ensures that t

RAC

 (Max.) can be met.

t

RAD

 (Max.) is specified as a reference point only. If t

RAD

 is greater than the specified

t

RAD

 (Max.) limit, then the access time is controlled by t

AA

.

7. t

OFF

 (Max.) and t

OEZ

 (Max.) define the time at which the output achieves the open

circuit condition and are not referenced to output voltage levels.

8. t

RCH

 or t

RRH

 must be satisfied for a read cycle.

9. t

WCS

, t

CWD

, t

RWD

, t

AWD 

and t

CPWD

 are not restrictive operating parameters. They are

included in the data sheet as electrical characteristics only. If t

WCS 

 t

WCS 

(Min.), then

the cycle is an early write cycle and the data out will remain open circuit (high

impedance) throughout the entire cycle. If t

CWD 

 t

CWD 

(Min.) , t

RWD 

 t

RWD

 (Min.),

t

AWD 

 t

AWD

 (Min.) and t

CPWD 

 t

CPWD

 (Min.), then the cycle is a read modify write

cycle and data out will contain data read from the selected cell; if neither of the above

sets of conditions is satisfied, then the condition of the data out (at access time) is

indeterminate.

10. These parameters are referenced to the CAS leading edge in an early write cycle, and

to the WE leading edge in an OE control write cycle, or a read modify write cycle.

11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.

This mode is latched and remains in effect until the exit cycle is generated.

The test mode  specified in this data sheet is a 2-bit parallel test function. CA9 is not

used.  In a read cycle, if all internal bits are equal, the DQ pin will indicate a high

level. If any internal bits are not equal, the DQ pin will indicate a low level.

The test mode is cleared and the memory device returned to its normal operating

state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.

12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the

specified value. These parameters should be specified in test mode cycle by adding the

above value to the specified value in this data sheet.

13. Only SL version.

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¡ Semiconductor

MSM51V17800D/DSL

9/17

TIMING WAVEFORM

Read Cycle

Write Cycle (Early Write)

,



"H" or "L"

RAS

CAS

V

IH

V

IL

V

IH

V

IL

DQ

V

OH

V

OL

Address

V

IH

V

IL

WE

V

IH

V

IL

OE

V

IH

V

IL

,,





,













































t

RC

t

RAS

t

RP

t

CRP

t

CSH

t

CRP

t

RCD

t

RSH

t

CAS

t

RAD

t

ASR

t

RAH

t

ASC

t

CAH

t

RAL

Row

Column

t

RCS

t

RRH

t

RCH

t

AA

t

ROH

t

OEA

t

CAC

t

RAC

t

OEZ

t

OFF

Open

t

CLZ

Valid Data-out





"H" or "L"

RAS

CAS

V

IH

V

IL

V

IH

V

IL

DQ

V

IH

V

IL

Address

V

IH

V

IL

WE

V

IH

V

IL

OE

V

IH

V

IL

,,,,



















t

RC

t

RAS

t

RP

t

CRP

t

RCD

t

CSH

t

RSH

t

CRP

t

CAS

t

RAD

t

RAH

t

ASR

t

ASC

t

CAH

Row

Column

t

WCS

t

WCH

t

DS

t

DH

Valid Data-in

t

WP

t

RAL











Open

t

CWL

t

RWL

E2G0101-17-41N

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¡ Semiconductor

MSM51V17800D/DSL

10/17



"H" or "L"

RAS

CAS

V

IH

V

IL

V

IH

V

IL

DQ

V

I/OH

V

I/OL

Address

V

IH

V

IL

WE

V

IH

V

IL

OE

V

IH

V

IL

,





,,





















t

RWC

t

RAS

t

RP

t

CRP

t

CSH

t

RCD

t

CRP

t

RSH

t

CAS

t

ASR

t

RAH

t

ASC

t

CAH

Row

Column

t

CWD

t

CWL

t

RWD

t

RWL

t

WP

t

AA

t

AWD

t

OEA

t

OED

t

CAC

t

RAC

t

OEZ

t

DS

t

DH

t

CLZ

Valid

Data-out

Valid

Data-in

t

RAD







t

RCS







t

OEH

Read Modify Write Cycle

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¡ Semiconductor

MSM51V17800D/DSL

11/17

Fast Page Mode Read Cycle

Fast Page Mode Write Cycle (Early Write)



"H" or "L"

RAS

CAS

V

IH

V

IL

V

IH

V

IL

DQ

V

IH

V

IL

Address

V

IL

WE

V

IH

V

IL

,





,





































,





























t

RASP

t

RP

t

CRP

t

RCD

t

CAS

t

CP

t

CAS

t

RSH

t

CRP

t

CAS

t

ASR

t

RAH

t

CAH

t

CSH

t

ASC

t

CAH

t

ASC

t

CAH

t

RAL

Row

Column

Column

Column

t

RAD

t

WCS

t

WCH

t

WP

t

WCS

t

WCH

t

WP

t

WCS

t

WCH

t

WP

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

Valid Data-in

Valid

Data-in

Valid

Data-in

Note:  

OE = "H" or "L"

V

IH

t

ASC

t

PC

t

RHCP

t

CP

t

CWL

t

CWL

t

RWL

t

CWL

,



"H" or "L"

RAS

CAS

V

IH

V

IL

V

IH

V

IL

DQ

V

OH

V

OL

Address

V

IH

V

IL

WE

V

IH

V

IL

OE

V

IH

V

IL

,











,













,





























t

RASP

t

RP

t

CRP

t

RCD

t

PC

t

RSH

t

CRP

t

CAS

t

CAS

t

CP

t

CAS

t

RAD

t

ASR

t

RAH

t

ASC

t

CAH

t

CSH

t

ASC

t

CAH

t

ASC

t

CAH

t

RAL

Row

Column

Column

Column

t

RCS

t

RCH

t

RCS

t

RCS

t

RCH

t

AA

t

OEA

t

AA

t

AA

t

RRH

t

OEA

t

OEA

t

CAC

t

RAC

t

OFF

t

OEZ

t

CAC

t

CLZ

t

OFF

t

OEZ

t

CAC

t

CLZ

t

OEZ

t

OFF

t

CLZ

Valid

Data-out

Valid

Data-out

Valid

Data-out

t

RHCP

t

CP

t

RCH

t

CPA

t

CPA

background image

¡ Semiconductor

MSM51V17800D/DSL

12/17

RAS

CAS

V

IH

V

IL

V

IH

V

IL

Address

V

IH

V

IL











,



t

RC

t

RAS

t

RP

t

CRP

t

RPC

t

ASR

t

RAH

Row



"H" or "L"

DQ

V

OH

V

OL

Note:  

WE, OE = "H" or "L"

Open

t

OFF

Fast Page Mode Read Modify Write Cycle

t

WP

RAS

CAS

Address

OE

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

WE

V

IH

V

IL

DQ

V

I/OH

V

I/OL

,





,





,





,



,



,



,





t

RASP

t

RP

t

CSH

t

PRWC

t

RSH

t

RCD

t

CAS

t

CP

t

CAS

t

CP

t

CAS

t

CRP

t

RAD

t

RAH

t

ASR

t

ASC

t

CAH

t

ASC

t

CAH

t

ASC

t

CAH

t

RAL

Row

Column

Column

Column

t

RWD

t

RCS

t

CWD

t

CWL

t

CWD

t

CWL

t

CWD

t

RWL

t

CWL

t

AWD

t

AWD

t

AWD

t

OEA

t

WP

t

OEA

t

WP

t

OEA

t

AA

t

OED

t

CAC

t

DS

t

DH

t

CAC

t

AA

t

RAC

t

DS

t

DH

t

CPA

t

OED

t

CAC

t

AA

t

DS

t

DH

t

CLZ

t

CLZ

t

CLZ

Out

In

Out

Out

In

In

t

ROH

t

OEZ

t

OEZ

t

CPA

t

OED

t

RCS

t

RCS

t

CPWD

t

CPWD





"H" or "L"

t

OEZ

RAS-Only Refresh Cycle

background image

¡ Semiconductor

MSM51V17800D/DSL

13/17

CAS before RAS Refresh Cycle

Hidden Refresh Read Cycle

RAS

CAS

V

IH

V

IL

V

IH

V

IL

Column

Row

DQ

V

OH

V

OL

WE

V

IH

V

IL

OE

V

IH

V

IL

Address

V

IH

V

IL









,,











,































t

RC

t

RC

t

RAS

t

RP

t

RAS

t

RP

t

CRP

t

RCD

t

RSH

t

CHR

t

RAD

t

ASR

t

ASC

t

RAH

t

CAH

t

RCS

t

RAL

t

RRH

t

AA

t

ROH

t

OEA

t

CAC

t

CLZ

t

RAC

t

OFF

t

OEZ

Valid Data-out

,

"H" or "L"

PQRS^KLM

V

IH

V

IL

RAS

t

RP

CAS

V

IH

V

IL

V

IH

V

IL

WE

V

V

t

RC

t

RAS

t

RPC

t

CHR

t

RP

t

RPC

t

CP

t

CSR

t

WRP

t

WRH

t

OFF

t

WRP

Open

OL

OH

DQ

Note:  OE, Address = "H" or "L"



"H" or "L"

background image

¡ Semiconductor

MSM51V17800D/DSL

14/17

Hidden Refresh Write Cycle





























t

ASR

Row

Column

V

IH

V

IL

RAS

Address

WE

CAS

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

t

CRP

t

RC

t

ASC

t

RP

t

RAS

t

RCD

t

RSH

t

RAD

t

CAH

t

RAH

t

RAL







DQ

V

IH

V

IL

t

WCS

t

CHR

t

RAS

t

WRH

t

WRP

t

RC

t

RP

OE

V

IH

V

IL

,,,,





t

DS

,









t

WP

t

WCH

t

DH





Valid Data-in





"H" or "L"

CAS before RAS Self-Refresh Cycle

RAS

CAS

V

IH

V

IL

V

IH

V

IL

"H" or "L"

,









DQ

V

OH

V

OL

t

RP

t

RASS

t

RPS

t

RPC

t

CSR

t

CP

t

RPC

t

CHS

Open

Note:  WE, OE, Address = "H" or "L"

            Only SL version 

t

OFF



"H" or "L"

background image

¡ Semiconductor

MSM51V17800D/DSL

15/17

Test Mode Initiate Cycle

V

IH

V

IL

RAS

CAS

V

IH

V

IL

t

RAS

V

OH

V

OL

V

IH

V

IL

Open

t

RC







t

WTH







,





t

RPC

t

WTS

t

CP

t

CSR

t

CHR

t

OFF

Note:  

OE, Address = "H" or "L"

t

RP

WE

DQ





"H" or "L"

background image

¡ Semiconductor

MSM51V17800D/DSL

16/17

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which

are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the

product name, package name, pin number, package code and desired mounting conditions

(reflow method, temperature and times).

SOJ28-P-400-1.27

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more

1.30 TYP.

Mirror finish

background image

¡ Semiconductor

MSM51V17800D/DSL

17/17

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which

are very susceptible to heat in reflow mounting and humidity absorbed in storage.

Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the

product name, package name, pin number, package code and desired mounting conditions

(reflow method, temperature and times).

TSOP

II28-P-400-1.27-K

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more

0.51 TYP.

Mirror finish