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¡ Semiconductor

MSM5118160D/DSL

DESCRIPTION

The MSM5118160D/DSL is a 1,048,576-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate

CMOS technology. The MSM5118160D/DSL achieves high integration, high-speed operation, and

low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/

double-layer metal CMOS process. The MSM5118160D/DSL is available in a 42-pin plastic SOJ or

50/44-pin plastic TSOP.  The MSM5118160DSL (the self-refresh version) is specially designed for

lower-power applications.

FEATURES

• 1,048,576-word ¥ 16-bit configuration

• Single  5 V power supply, 

±

10% tolerance

• Input

: TTL compatible, low input capacitance

• Output : TTL compatible, 3-state

• Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (SL version)

• Fast page mode, read modify write capability

• CAS before RAS refresh, hidden refresh, RAS-only refresh capability

• CAS before RAS self-refresh capability (SL version)

• Package options:

42-pin 400 mil plastic SOJ

(SOJ42-P-400-1.27)

(Product : MSM5118160D/DSL-xxJS)

50/44-pin 400 mil plastic TSOP (TSOPII50/44-P-400-0.80-K)(Product : MSM5118160D/DSL-xxTS-K)

(TSOPII50/44-P-400-0.80-L) (Product : MSM5118160D/DSL-xxTS-L)

xx indicates speed rank.

PRODUCT FAMILY

¡ Semiconductor

MSM5118160D/DSL

1,048,576-Word 

¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE

MSM5118160D/DSL-70

70 ns

130 ns

90 ns

633 mW

743 mW

Family

Access Time (Max.)

Cycle Time

(Min.)

Standby (Max.)

Power Dissipation 

MSM5118160D/DSL-50

t

RAC

50 ns

35 ns

t

AA

25 ns

20 ns

t

CAC

13 ns

20 ns

t

OEA

13 ns

MSM5118160D/DSL-60

60 ns

110 ns

688 mW

30 ns

15 ns

15 ns

Operating (Max.)

5.5 mW/

1.1 mW (SL version)

E2G0152-29-41

This version:  Apr. 1999

Previous version:  Oct. 1998

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¡ Semiconductor

MSM5118160D/DSL

PIN CONFIGURATION (TOP VIEW)

A9

A8

A7

A6

A5

A4

NC

NC

A0

A1

A2

A3

A9

A8

A7

A6

A5

A4

NC

NC

A0

A1

A2

A3

1

2

3

4

5

6

7

8

9

10

11

12

13

21

22

30

31

32

33

34

35

36

37

38

39

40

41

42

V

CC

DQ1

DQ2

DQ3

DQ4

V

CC

DQ5

DQ6

DQ7

DQ8

NC

NC

WE

V

CC

V

SS

UCAS

LCAS

NC

DQ9

DQ10

DQ11

DQ12

V

SS

DQ13

DQ14

DQ15

DQ16

V

SS

14

29

RAS

OE

15

28

NC

A9

16

27

NC

A8

17

26

A0

A7

18

25

A1

A6

19

24

A2

A5

20

23

A3

A4

1

2

3

4

5

6

7

8

9

10

11

25

26

40

41

42

43

44

45

46

47

48

49

50

V

CC

DQ1

DQ2

DQ3

DQ4

V

CC

DQ5

DQ6

DQ7

DQ8

NC

V

CC

V

SS

NC

DQ9

DQ10

DQ11

DQ12

V

SS

DQ13

DQ14

DQ15

DQ16

V

SS

15

36

NC

NC

16

35

NC

LCAS

17

34

WE

UCAS

18

33

RAS

OE

19

32

20

31

21

30

22

29

23

28

24

27

1

2

3

4

5

6

7

8

9

10

11

25

26

40

41

42

43

44

45

46

47

48

49

50

V

CC

DQ1

DQ2

DQ3

DQ4

V

CC

DQ5

DQ6

DQ7

DQ8

NC

V

CC

V

SS

NC

DQ9

DQ10

DQ11

DQ12

V

SS

DQ13

DQ14

DQ15

DQ16

V

SS

15

36

NC

NC

16

35

NC

LCAS

17

34

WE

UCAS

18

33

RAS

OE

19

32

20

31

21

30

22

29

23

28

24

27

42-Pin Plastic SOJ

50/44-Pin Plastic TSOP

(K Type)

50/44-Pin Plastic TSOP

(L Type)





Note :

The same power supply voltage must be provided to every V

CC

 pin, and the same GND

voltage level must be provided to every V

SS

 pin.

Pin Name

Function

A0 - A9

Address Input

RAS

Row Address Strobe

LCAS

Lower Byte Column Address Strobe

DQ1 - DQ16

Data Input/Data Output

OE

Output Enable

WE

Write Enable

V

CC

Power Supply (5 V)

NC

No Connection

UCAS

Upper Byte Column Address Strobe

V

SS

Ground (0 V)

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¡ Semiconductor

MSM5118160D/DSL

BLOCK DIAGRAM

Timing 

Generator

Refresh

Control Clock

Column

Address

Buffers

Internal

Address

Counter

Row

Address

Buffers

Row

Deco-

ders

Word

Drivers

Memory

Cells

Sense Amplifiers

Column Decoders

I/O

Controller

I/O

Controller

I/O

Selector

Input

Buffers

Output

Buffers

Output

Buffers

Input

Buffers

On Chip

V

BB

 Generator

V

CC

DQ1 - DQ8

DQ9 - DQ16

UCAS

WE

A0

 - 

A9

10

16

8

8

16

8

8

8

8

8

8

10

OE

RAS

LCAS

On Chip

IV

CC

 Generator

V

SS

10

10

FUNCTION TABLE

Function Mode

RAS

H

L

Input Pin

LCAS

*

H

L

UCAS

H

WE

H

H

H

L

L

OE

L

L

L

H

L

L

L

L

L

H

L

L

H

L

L

H

L

*

*

*

*

*

H

Lower Byte Read

Upper Byte Read

Word Read

Refresh

Standby

Lower Byte Write

DQ Pin

DQ1 - DQ8

High-Z

High-Z

D

OUT

D

IN

DQ9 - DQ16

High-Z

High-Z

High-Z

D

OUT

Don't Care

High-Z

D

OUT

D

OUT

Don't Care

D

IN

Upper Byte Write

L

L

L

L

H

D

IN

D

IN

Word Write

H

L

L

L

H

High-Z

High-Z

H

*: "H" or "L"

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¡ Semiconductor

MSM5118160D/DSL

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Voltage on Any Pin Relative to V

SS

Short Circuit Output Current

Power Dissipation

Operating Temperature

Storage Temperature

V

IN

, V

OUT

Symbol

I

OS

P

D

*

T

opr

T

stg

–0.5 to V

CC

 + 0.5

50

1

0 to 70

–55 to 150

Rating

mA

W

°C

°C

Parameter

V

Unit

Voltage on V

CC

 Supply Relative to V

SS

V

CC

–0.5 to 7

V

Recommended Operating Conditions

*: Ta = 25

°

C

Power Supply Voltage

Input High Voltage

Input Low Voltage

V

CC

Symbol

V

SS

V

IH

V

IL

5.0

0

Typ.

Parameter

4.5

0

2.4

–0.5

*2

Min.

5.5

0

V

CC

 + 0.5

*1

0.8

Max.

(Ta = 0°C to 70°C)

V

Unit

V

V

V

Notes : *1. The input voltage is V

CC

 + 2.0 V when the pulse width is less than 20 ns (the pulse width

is with respect to the point at which V

CC

 is applied).

*2. The input voltage is V

SS

  – 2.0 V when the pulse width is less than 20 ns (the pulse width

is with respect to the point at which V

SS

 is applied).

Capacitance

Input Capacitance (A0 - A9) 

Input Capacitance

Output Capacitance (DQ1 - DQ16)

C

IN1

Symbol

C

IN2

C

I/O

5

7

7

Max.

pF

Unit

pF

pF

Parameter

(V

CC

 = 5 V ±10%, Ta = 25°C, f = 1 MHz)

Typ.

(

RAS, LCAS, UCAS, WE, OE)

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¡ Semiconductor

MSM5118160D/DSL

DC Characteristics

Parameter

Symbol

Condition

MSM5118160

D/DSL-50

MSM5118160

D/DSL-60

MSM5118160

D/DSL-70

(V

CC

 = 5 V ±10%, Ta = 0°C to 70°C)

I

OH

 = –5.0 mA

Output High Voltage

I

OL

 = 4.2 mA

Output Low Voltage

0 V £ V

I

 £ 6.5 V;

All other pins not

Input Leakage Current

under test = 0 V

DQ disable

Output Leakage Current

0 V £ V

O

 £ V

CC

RAS, CAS cycling,

Average Power

t

RC

 = Min.

Supply Current

(Operating)

RAS, CAS = V

IH

Power Supply

RAS, CAS

Current (Standby)

RAS cycling,

Average Power

CAS = V

IH

,

Supply Current

t

RC

 = Min.

(

RAS-only Refresh)

RAS = V

IH

,

Power Supply

CAS = V

IL

,

Current (Standby)

DQ = enable

Average Power

CAS before RAS

Supply Current

(

CAS before RAS Refresh)

Average Power

RAS £ 0.2 V,

Supply Current

CAS £ 0.2 V

(

CAS before RAS

V

OH

V

OL

I

LI

I

LO

I

CC1

I

CC2

I

CC3

I

CC5

I

CC6

I

CCS

≥ V

CC

 –0.2 V

Min.

Max.

Min.

Max.

Min.

Max.

Unit Note

RAS cycling,

2.4

0

–10

–10

V

CC

0.4

10

10

135

2

1

135

135

300

5

2.4

0

–10

–10

V

CC

0.4

10

10

125

2

1

125

125

300

5

2.4

0

–10

–10

V

CC

0.4

10

10

115

2

1

115

115

300

5

200

200

200

V

V

mA

mA

mA

mA

mA

mA

mA

mA

1, 2

1, 2

1, 2

1, 5

1

1

mA

1, 5

t

RC

 = 125 ms,

Average Power

CAS before RAS,

Supply Current

t

RAS

 £ 1 ms

(Battery Backup)

I

CC10

300

300

300

mA

1, 4,

RAS = V

IL

,

Average Power

CAS cycling,

Supply Current

t

PC

 = Min.

(Fast Page Mode)

I

CC7

135

125

115

mA

1, 3

5

Self-Refresh)

Notes : 1. I

CC

 Max. is specified as I

CC

 for output open condition.

2. The address can be changed once or less while RAS = V

IL

.

3. The address can be changed once or less while CAS = V

IH

.

4. V

CC

 – 0.2 V £ V

IH

 £ V

CC

 + 0.5 V, –0.5 V £ V

IL

 £ 0.2 V.

5. SL version.

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¡ Semiconductor

MSM5118160D/DSL

AC Characteristics (1/2)

Parameter

MSM5118160

D/DSL-60

MSM5118160

D/DSL-70

MSM5118160

D/DSL-50

(V

CC

 = 5 V ±10%, Ta = 0°C to 70°C)  Note 1, 2, 3

Random Read or Write Cycle Time 

Read Modify Write Cycle Time

Fast Page Mode Cycle Time

Fast Page Mode Read Modify Write

Cycle Time

Access Time from 

RAS

Access Time from 

CAS

Access Time from Column Address

Access Time from 

CAS Precharge

CAS to Data Output Buffer Turn-off Delay Time

Transition Time

RAS Precharge Time

RAS Pulse Width

RAS Pulse Width (Fast Page Mode)

RAS Hold Time

CAS Pulse Width

CAS Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

CAS to RAS Precharge Time

Row Address Set-up Time

Row Address Hold Time

Column Address Set-up Time

Column Address Hold Time

Column Address to 

RAS Lead Time

Read Command Set-up Time

Read Command Hold Time

Read Command Hold Time referenced to 

RAS

Access Time from 

OE

OE to Data Output Buffer Turn-off Delay Time

Refresh Period

RAS Hold Time referenced to OE

Unit

Min.

Max.

Min.

Max.

RAS Hold Time from CAS Precharge

Symbol

t

RC

t

RWC

t

PC

t

PRWC

t

RAC

t

CAC

t

AA

t

CPA

t

OFF

t

T

t

RP

t

RAS

t

RASP

t

RSH

t

CAS

t

CSH

t

RCD

t

RAD

t

CRP

t

ASR

t

RAH

t

ASC

t

CAH

t

RAL

t

RCS

t

RCH

t

RRH

t

OEA

t

OEZ

t

REF

t

ROH

t

RHCP

Note

Min.

Max.

Output Low Impedance Time from 

CAS

t

CLZ

CAS Precharge Time (Fast Page Mode)

t

CP

11

4, 5, 6

4, 5

4, 6

4, 12

7

14

5

6

12

11

11

8, 11

8

4

7

4

3

15

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ms

ns

ns

90

131

35

76

0

0

3

30

50

50

13

7

13

50

17

12

5

0

7

0

7

25

0

0

0

0

13

30

50

13

25

30

13

50

10,000

100,000

10,000

37

25

13

13

16

130

185

45

100

0

0

3

50

70

70

20

10

20

70

20

15

5

0

10

0

15

35

0

0

0

0

20

40

70

20

35

40

20

50

10,000

100,000

10,000

50

35

20

20

16

110

155

40

85

0

0

3

40

60

60

15

10

15

60

20

15

5

0

10

0

10

30

0

0

0

0

15

35

60

15

30

35

15

50

10,000

100,000

10,000

45

30

15

15

16

Refresh Period (SL version)

t

REF

ms

128

128

128

12

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¡ Semiconductor

MSM5118160D/DSL

AC Characteristics (2/2)

MSM5118160

D/DSL-60

MSM5118160

D/DSL-70

MSM5118160

D/DSL-50

Write Command Pulse Width

Write Command to 

CAS Lead Time

Write Command to 

RAS Lead Time

Data-in Set-up Time

CAS to WE Delay Time

RAS to WE Delay Time

Column Address to 

WE Delay Time

RAS to CAS Hold Time (CAS before RAS)

CAS Active Delay Time from RAS Precharge

Data-in Hold Time

Write Command Hold Time

OE Command Hold Time

OE to Data-in Delay Time

(V

CC

 = 5 V ±10%, Ta = 0°C to 70°C)  Note 1, 2, 3

Write Command Set-up Time

t

WP

t

CWL

t

RWL

t

DS

t

CWD

t

RWD

t

AWD

t

CHR

t

RPC

t

DH

t

WCH

t

OEH

t

OED

t

WCS

Min.

Max.

Parameter

Symbol

Unit Note

Min.

Max.

Min.

Max.

RAS to CAS Set-up Time (CAS before RAS) t

CSR

CAS Precharge WE Delay Time

t

CPWD

13

10, 11

9

9

9

11

12

11

10, 11

11

9, 11

9

10

15

15

0

40

85

55

10

10

5

10

10

15

15

0

60

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

7

13

13

0

36

73

48

10

10

5

7

7

13

13

0

53

10

20

20

0

50

100

65

10

10

5

15

15

20

20

0

70

RAS Pulse Width

t

RASS

15

100

ms

100

100

(

CAS before RAS Self-Refresh)

RAS Precharge Time

t

RPS

15

110

ns

90

130

(

CAS before RAS Self-Refresh)

CAS Hold Time

t

CHS

15

–50

ns

–50

–50

(

CAS before RAS Self-Refresh)

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¡ Semiconductor

MSM5118160D/DSL

Notes:

1. A start-up delay of 200 

µ

s is required after power-up, followed by a minimum of eight

initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device

operation is achieved.

2. The AC characteristics assume t

= 5 ns.

3. V

IH

 (Min.) and V

IL

 (Max.) are reference levels for measuring input timing signals.

Transition times (t

T

) are measured between V

IH

 and V

IL

.

4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.

5. Operation within the t

RCD

 (Max.) limit ensures that t

RAC

 (Max.) can be met.

t

RCD

 (Max.) is specified as a reference point only. If t

RCD

 is greater than the specified

t

RCD

 (Max.) limit, then the access time is controlled by t

CAC

.

6. Operation within the t

RAD

 (Max.) limit ensures that t

RAC

 (Max.) can be met.

t

RAD

 (Max.) is specified as a reference point only. If t

RAD

 is greater than the specified

t

RAD

 (Max.) limit, then the access time is controlled by t

AA

.

7. t

OFF

 (Max.) and t

OEZ

 (Max.) define the time at which the output achieves the open

circuit condition and are not referenced to output voltage levels.

8. t

RCH

 or t

RRH

 must be satisfied for a read cycle.

9. t

WCS

, t

CWD

, t

RWD

, t

AWD 

and t

CPWD

 are not restrictive operating parameters. They are

included in the data sheet as electrical characteristics only. If t

WCS 

 t

WCS 

(Min.), then

the cycle is an early write cycle and the data out will remain open circuit (high

impedance) throughout the entire cycle. If t

CWD 

 t

CWD 

(Min.) , t

RWD 

 t

RWD

 (Min.),

t

AWD 

 t

AWD

 (Min.) and t

CPWD 

 t

CPWD

 (Min.), then the cycle is a read modify write

cycle and data out will contain data read from the selected cell; if neither of the above

sets of conditions is satisfied, then the condition of the data out (at access time) is

indeterminate.

10. These parameters are referenced to the UCAS and LCAS, leading edges in an early

write cycle, and to the WE leading edge in an OE control write cycle, or a read modify

write cycle.

11. These parameters are determined by the falling edge of either UCAS or LCAS,

whichever is earlier.

12. These parameters are determined by the rising edge of either UCAS or LCAS,

whichever is later.

13. t

CWL

 should be satisfied by both UCAS and LCAS.

14. t

CP

 is determined by the time both UCAS and LCAS are high.

15. Only SL version.

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¡ Semiconductor

MSM5118160D/DSL

TIMING WAVEFORM

Read Cycle

Write Cycle (Early Write)

,



"H" or "L"

RAS

CAS

V

IH

V

IL

V

IH

V

IL

DQ

V

OH

V

OL

Address

V

IH

V

IL

WE

V

IH

V

IL

OE

V

IH

V

IL

,,





,













































t

RC

t

RAS

t

RP

t

CRP

t

CSH

t

CRP

t

RCD

t

RSH

t

CAS

t

RAD

t

ASR

t

RAH

t

ASC

t

CAH

t

RAL

Row

Column

t

RCS

t

RRH

t

RCH

t

AA

t

ROH

t

OEA

t

CAC

t

RAC

t

OEZ

t

OFF

Open

t

CLZ

Valid Data-out





"H" or "L"

RAS

CAS

V

IH

V

IL

V

IH

V

IL

DQ

V

IH

V

IL

Address

V

IH

V

IL

WE

V

IH

V

IL

OE

V

IH

V

IL

,,,,



















t

RC

t

RAS

t

RP

t

CRP

t

RCD

t

CSH

t

RSH

t

CRP

t

CAS

t

RAD

t

RAH

t

ASR

t

ASC

t

CAH

Row

Column

t

WCS

t

WCH

t

DS

t

DH

Valid Data-in

t

WP

t

RAL











Open

t

CWL

t

RWL

E2G0103-29-41P

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¡ Semiconductor

MSM5118160D/DSL



"H" or "L"

RAS

CAS

V

IH

V

IL

V

IH

V

IL

DQ

V

I/OH

V

I/OL

Address

V

IH

V

IL

WE

V

IH

V

IL

OE

V

IH

V

IL

,





,,





















t

RWC

t

RAS

t

RP

t

CRP

t

CSH

t

RCD

t

CRP

t

RSH

t

CAS

t

ASR

t

RAH

t

ASC

t

CAH

Row

Column

t

CWD

t

CWL

t

RWD

t

RWL

t

WP

t

AA

t

AWD

t

OEA

t

OED

t

CAC

t

RAC

t

OEZ

t

DS

t

DH

t

CLZ

Valid

Data-out

Valid

Data-in

t

RAD







t

RCS







t

OEH

Read Modify Write Cycle

background image

11/16

¡ Semiconductor

MSM5118160D/DSL

Fast Page Mode Read Cycle

Fast Page Mode Write Cycle (Early Write)



"H" or "L"

RAS

CAS

V

IH

V

IL

V

IH

V

IL

DQ

V

IH

V

IL

Address

V

IL

WE

V

IH

V

IL

,





,





































,





























t

RASP

t

RP

t

CRP

t

RCD

t

CAS

t

CP

t

CAS

t

RSH

t

CRP

t

CAS

t

ASR

t

RAH

t

CAH

t

CSH

t

ASC

t

CAH

t

ASC

t

CAH

t

RAL

Row

Column

Column

Column

t

RAD

t

WCS

t

WCH

t

WP

t

WCS

t

WCH

t

WP

t

WCS

t

WCH

t

WP

t

DS

t

DH

t

DS

t

DH

t

DS

t

DH

Valid Data-in

Valid

Data-in

Valid

Data-in

Note:  

OE = "H" or "L"

V

IH

t

ASC

t

PC

t

RHCP

t

CP

t

CWL

t

CWL

t

RWL

t

CWL

,



"H" or "L"

RAS

CAS

V

IH

V

IL

V

IH

V

IL

DQ

V

OH

V

OL

Address

V

IH

V

IL

WE

V

IH

V

IL

OE

V

IH

V

IL

,











,













,





























t

RASP

t

RP

t

CRP

t

RCD

t

PC

t

RSH

t

CRP

t

CAS

t

CAS

t

CP

t

CAS

t

RAD

t

ASR

t

RAH

t

ASC

t

CAH

t

CSH

t

ASC

t

CAH

t

ASC

t

CAH

t

RAL

Row

Column

Column

Column

t

RCS

t

RCH

t

RCS

t

RCS

t

RCH

t

AA

t

OEA

t

AA

t

AA

t

RRH

t

OEA

t

OEA

t

CAC

t

RAC

t

OFF

t

OEZ

t

CAC

t

CLZ

t

OFF

t

OEZ

t

CAC

t

CLZ

t

OEZ

t

OFF

t

CLZ

Valid

Data-out

Valid

Data-out

Valid

Data-out

t

RHCP

t

CP

t

RCH

t

CPA

t

CPA

background image

12/16

¡ Semiconductor

MSM5118160D/DSL

RAS

CAS

V

IH

V

IL

V

IH

V

IL

Address

V

IH

V

IL











,



t

RC

t

RAS

t

RP

t

CRP

t

RPC

t

ASR

t

RAH

Row



"H" or "L"

DQ

V

OH

V

OL

Note:  

WE, OE = "H" or "L"

Open

t

OFF

Fast Page Mode Read Modify Write Cycle

t

WP

RAS

CAS

Address

OE

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

WE

V

IH

V

IL

DQ

V

I/OH

V

I/OL

,





,





,





,



,



,



,





t

RASP

t

RP

t

CSH

t

PRWC

t

RSH

t

RCD

t

CAS

t

CP

t

CAS

t

CP

t

CAS

t

CRP

t

RAD

t

RAH

t

ASR

t

ASC

t

CAH

t

ASC

t

CAH

t

ASC

t

CAH

t

RAL

Row

Column

Column

Column

t

RWD

t

RCS

t

CWD

t

CWL

t

CWD

t

CWL

t

CWD

t

RWL

t

CWL

t

AWD

t

AWD

t

AWD

t

OEA

t

WP

t

OEA

t

WP

t

OEA

t

AA

t

OED

t

CAC

t

DS

t

DH

t

CAC

t

AA

t

RAC

t

DS

t

DH

t

CPA

t

OED

t

CAC

t

AA

t

DS

t

DH

t

CLZ

t

CLZ

t

CLZ

Out

In

Out

Out

In

In

t

ROH

t

OEZ

t

OEZ

t

CPA

t

OED

t

RCS

t

RCS

t

CPWD

t

CPWD





"H" or "L"

t

OEZ

RAS-Only Refresh Cycle

background image

13/16

¡ Semiconductor

MSM5118160D/DSL

CAS before RAS Refresh Cycle

Hidden Refresh Read Cycle

RAS

CAS

V

IH

V

IL

V

IH

V

IL

Column

Row

DQ

V

OH

V

OL

WE

V

IH

V

IL

OE

V

IH

V

IL

Address

V

IH

V

IL









,,











,































t

RC

t

RC

t

RAS

t

RP

t

RAS

t

RP

t

CRP

t

RCD

t

RSH

t

CHR

t

RAD

t

ASR

t

ASC

t

RAH

t

CAH

t

RCS

t

RAL

t

RRH

t

AA

t

ROH

t

OEA

t

CAC

t

CLZ

t

RAC

t

OFF

t

OEZ

Valid Data-out

,

"H" or "L"

^

V

IH

V

IL

RAS

t

RP

CAS

V

IH

V

IL

V

V

t

RC

t

RAS

t

RPC

t

CHR

t

RP

t

RPC

t

CP

t

CSR

t

OFF

Open

OL

OH

DQ

Note:  

WE, OE, Address = "H" or "L"



"H" or "L"

background image

14/16

¡ Semiconductor

MSM5118160D/DSL

Hidden Refresh Write Cycle





























t

ASR

Row

Column

V

IH

V

IL

RAS

Address

WE

CAS

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

t

CRP

t

RC

t

ASC

t

RP

t

RAS

t

RCD

t

RSH

t

RAD

t

CAH

t

RAH

t

RAL







DQ

V

IH

V

IL

t

WCS

t

CHR

t

RAS

t

WRH

t

WRP

t

RC

t

RP

OE

V

IH

V

IL

,,,,





t

DS

,









t

WP

t

WCH

t

DH





Valid Data-in





"H" or "L"

CAS before RAS Self-Refresh Cycle

RAS

CAS

V

IH

V

IL

V

IH

V

IL

"H" or "L"

,









DQ

V

OH

V

OL

t

RP

t

RASS

t

RPS

t

RPC

t

CSR

t

CP

t

RPC

t

CHS

Open

Note:  

WE, OE, Address = "H" or "L"

            Only SL version 

t

OFF



"H" or "L"

background image

15/16

¡ Semiconductor

MSM5118160D/DSL

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type

packages, which are very susceptible to heat in reflow mounting and humidity absorbed in

storage.  Therefore, before you perform reflow mounting, contact Oki’s responsible sales person

on the product name, package name, pin number, package code and desired mounting conditions

(reflow method, temperature and times).

SOJ42-P-400-1.27

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more

1.86 TYP.

Mirror finish

background image

16/16

¡ Semiconductor

MSM5118160D/DSL

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type

packages, which are very susceptible to heat in reflow mounting and humidity absorbed in

storage.  Therefore, before you perform reflow mounting, contact Oki’s responsible sales person

on the product name, package name, pin number, package code and desired mounting conditions

(reflow method, temperature and times).

Package material

Lead frame material

Pin treatment

Solder plate thickness

Package weight (g)

Epoxy resin

42 alloy

Solder plating

5 mm or more

0.60 TYP.

TSOP

II50/44-P-400-0.80-K

Mirror finish

background image

NOTICE

1.

The information contained herein can change without notice owing to product and/or

technical improvements. Before using the product, please make sure that the information

being referred to is up-to-date.

2.

The outline of action and examples for application circuits described herein have been

chosen as an explanation for the standard action and performance of the product. When

planning to use the product, please ensure that the external conditions are reflected in the

actual circuit, assembly, and program designs.

3.

When designing your product, please use our product below the specified maximum

ratings and within the specified operating ranges including, but not limited to, operating

voltage, power dissipation, and operating temperature.

4.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or

unexpected operation resulting from misuse, neglect, improper installation, repair, alteration

or accident, improper handling, or unusual physical or electrical stress including, but not

limited to, exposure to parameters beyond the specified maximum ratings or operation

outside the specified operating range.

5.

Neither indemnity against nor license of a third party’s industrial and intellectual property

right, etc. is granted by us in connection with the use of the product and/or the information

and drawings contained herein. No responsibility is assumed by us for any infringement

of a third party’s right which may result from the use thereof.

6.

The products listed in this document are intended for use in general electronics equipment

for commercial applications (e.g., office automation, communication equipment,

measurement equipment, consumer electronics, etc.). These products are not authorized

for use in any system or application that requires special or enhanced quality and reliability

characteristics nor in any system or application where the failure of such system or

application may result in the loss or damage of property, or death or injury to humans.

Such applications include, but are not limited to, traffic and automotive equipment, safety

devices, aerospace equipment, nuclear power control, medical equipment, and life-support

systems.

7.

Certain products in this document may need government approval before they can be

exported to particular countries. The purchaser assumes the responsibility of determining

the legality of export of these products and will take appropriate and necessary steps at their

own expense for these.

8.

No part of the contents cotained herein may be reprinted or reproduced without our prior

permission.

9.

MS-DOS is a registered trademark of Microsoft Corporation.

Copyright 1999 Oki Electric Industry Co., Ltd.

Printed in Japan

E2Y0002-29-11