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MCM6709AR

1

MOTOROLA FAST SRAM

64K x 4 Bit Static RAM

The MCM6709AR is a 262,144 bit static random access memory organized as

65,536 words of 4 bits, fabricated using high–performance silicon–gate BiCMOS

technology. Static design eliminates the need for external clocks or timing

strobes.

Output enable (G) is a special control feature that provides increased system

flexibility and eliminates bus contention problems.

The MCM6709AR meets JEDEC standards and is available in a revolutionary

pinout 300 mil, 28 lead plastic surface–mount SOJ package.

Single 5 V 

±

10% Power Supply

Fully Static — No Clock or Timing Strobes Necessary

All Inputs and Outputs are TTL Compatible

Center Power and I/O Pins for Reduced Noise

Three State Outputs

Fast Access Times: MCM6709AR–6 = 6 ns

MCM6709AR–7 = 7 ns

BLOCK DIAGRAM

G

INPUT

DATA

CONTROL

MEMORY MATRIX

512 ROWS x 128 x 4

COLUMNS

COLUMN I/O

COLUMN DECODER

DQ0

DQ3

E

W

ROW

DECODER

••

••

••

••

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Order this document

by MCM6709AR/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT

MCM6709AR

A0 – A15

Address Inputs

. . . . . . . . . . . . 

W

Write Enable

. . . . . . . . . . . . . . . . . . . . 

G

Output Enable

. . . . . . . . . . . . . . . . . . . 

E

Chip Enable

. . . . . . . . . . . . . . . . . . . . . . 

DQ0 – DQ3

Data Input/Output

. . . . . . . . 

VCC

+ 5 V Power Supply

. . . . . . . . . . . . 

VSS

Ground

. . . . . . . . . . . . . . . . . . . . . . . 

NC

No Connection

. . . . . . . . . . . . . . . . . 

PIN NAMES

J PACKAGE

300 MIL SOJ

CASE 810B–03

5

4

3

2

1

10

9

8

7

6

11

12

13

14

20

21

22

23

24

25

26

19

27

28

18

17

16

15

VCC

A3

A2

A1

A0

A4

VSS

E

A7

A6

A5

DQ0

DQ1

W

G

A12

A13

A14

A15

A8

A9

A10

NC

DQ2

VSS

DQ3

A11

VCC

All power supply and ground pins must

be connected for proper operation of the

device.

5/95

©

 Motorola, Inc. 1995

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MCM6709AR

2

MOTOROLA FAST SRAM

TRUTH TABLE 

(X = Don’t Care)

E

G

W

Mode

Output

Cycle

H

X

X

Not Selected

High–Z

L

H

H

Read

High–Z

L

L

H

Read

Dout

Read Cycle

L

X

L

Write

Din

Write Cycle

ABSOLUTE MAXIMUM RATINGS 

(See Note)

Rating

Symbol

Value

Unit

Power Supply Voltage

VCC

– 0.5 to + 7.0

V

Voltage Relative to VSS for Any Pin

Except VCC

Vin, Vout

– 0.5 to VCC + 0.5

V

Output Current  (per I/O)

Iout

±

30

mA

Power Dissipation

PD

2.0

W

Temperature Under Bias

Tbias

– 10 to + 85

°

C

Operating Temperature

TA

0 to + 70

°

C

Storage Temperature — Plastic

Tstg

– 55 to + 125

°

C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for

extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V 

±

10%, TA = 0 to 70

°

C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

VCC + 0.3*

V

Input Low Voltage

VIL

– 0.5**

0.8

V

* VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 

 2.0 ns) or I 

 30.0 mA.

** VIL (min) = – 0.5 V dc @ 30.0 mA; VIL (min) = – 2.0 V ac (pulse width 

 2.0 ns) or I 

 30.0 mA.

DC CHARACTERISTICS

Parameter

Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC)

Ilkg(I)

±

1.0

µ

A

Output Leakage Current (E = VIH, Vout = 0 to VCC)

Ilkg(O)

±

1.0

µ

A

Output High Voltage (IOH = –  4.0 mA)

VOH

2.4

V

Output Low Voltage (IOL = 8.0 mA)

VOL

0.4

V

POWER SUPPLY CURRENTS

Parameter

Symbol

MCM6709AR–6

MCM6709AR–7

Unit

Notes

AC Active Supply Current (Iout = 0 mA, VCC = max, f = fmax)

ICCA

235

225

mA

1, 2, 3

AC Standby Current (E = VIH, VCC = max, f = fmax)

ISB1

95

85

mA

1, 2, 3

CMOS Standby Current (VCC = max, f = 0 MHz,

 VCC – 0.2 V, Vin 

 VSS, or 

 VCC – 0.2 V)

ISB2

20

20

mA

NOTES:

1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).

2. All addresses transition simultaneously low (LSB) and then high (MSB).

3. Data states are all zero.

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised

that normal precautions be taken to avoid appli-

cation of any voltage higher than maximum

rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been de-

signed to meet the dc and ac specifications

shown in the tables, after thermal equilibrium

has been established. The circuit is in a test

socket or mounted on a printed circuit board

and transverse air flow of at least 500 linear feet

per minute is maintained.

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MCM6709AR

3

MOTOROLA FAST SRAM

CAPACITANCE 

(f = 1.0 MHz, dV = 3.0 V, TA = 25

°

C, Periodically Sampled Rather Than 100% Tested)

Parameter

Symbol

Max

Unit

Address Input Capacitance

Cin

5

pF

Control Pin Input Capacitance (E, G, W)

Cin

6

pF

Input/Output Capacitance

CI/O

6

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V 

±

10%, TA = 0 to + 70

°

C, Unless Otherwise Noted)

Input Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . . . . 

Input Pulse Levels

0 to 3.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input Rise/Fall Time

2 ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Output Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . . 

Output Load

See Figure 1A

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

READ CYCLES 1 AND 2 

(See Notes 1 and 2)

MCM6709AR–6

MCM6709AR–7

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

6

7

ns

3

Address Access Time

tAVQV

6

7

ns

Chip Enable Access Time

tELQV

6

7

ns

Output Enable Access Time

tGLQV

4

4

ns

Output Hold from Address Change

tAXQX

2.5

2.5

ns

Chip Enable Low to Output Active

tELQX

3

3

ns

4, 5, 6

Output Enable Low to Output Active

tGLQX

0

0

ns

4, 5, 6

Chip Enable High to Output High–Z

tEHQZ

0

3

0

3.5

ns

4, 5, 6

Output Enable High to Output High–Z

tGHQZ

0

3

0

3.5

ns

4, 5, 6

NOTES:

1. W is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus

contention conditions during read and write cycles.

3. .All read cycle timings are referenced from the last valid address to the first transitioning address.

4. At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given

device and from device to device.

5. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.

6. This parameter is sampled and not 100% tested.

AC TEST LOADS

OUTPUT

Z0 =  50 

RL  =  50 

VL = 1.5 V

Figure 1A

Figure 1B

5 pF

+5 V

OUTPUT

255 

480 

The table of timing values shows either a

minimum or a maximum limit for each param-

eter. Input requirements are specified from

the external system point of view. Thus, ad-

dress setup time is shown as a minimum

since the system must supply at least that

much time (even though most devices do not

require it). On the other hand, responses from

the memory are specified from the device

point of view. Thus, the access time is shown

as a maximum since the device never pro-

vides data later than that time.

TIMING LIMITS

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MCM6709AR

4

MOTOROLA FAST SRAM

READ CYCLE 1 

(See Note)

tAXQX

tAVAV

tAVQV

DATA VALID

PREVIOUS DATA VALID

A (ADDRESS)

Q (DATA OUT)

NOTE: Device is continuously selected (E = VIL, G = VIL).

READ CYCLE 2 

(See Note)

tGLQX

tAVAV

tELQV

tELQX

tEHQZ

tGHQZ

tGLQV

Q (DATA OUT)

A (ADDRESS)

E (CHIP ENABLE)

G (OUTPUT ENABLE)

DATA VALID

tAVQV

NOTE: Addresses valid prior to or coincident with E going low.

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MCM6709AR

5

MOTOROLA FAST SRAM

WRITE CYCLE 1 

(W Controlled, See Notes 1 and 2)

MCM6709AR–6

MCM6709AR–7

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

6

7

ns

3

Address Setup Time

tAVWL

0

0

ns

Address Valid to End of Write

tAVWH

6

7

ns

Write Pulse Width

tWLWH

tWLEH

6

7

ns

Data Valid to End of Write

tDVWH

3

3.5

ns

Data Hold Time

tWHDX

0

0

ns

Write Low to Data High–Z

tWLQZ

0

3.5

0

3.5

ns

4, 5, 6

Write High to Output Active

tWHQX

3

3

ns

4, 5, 6

Write Recovery Time

tWHAX

0

0

ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus

contention conditions during read and write cycles.

3. All write cycle timing is referenced from the last valid address to the first transitioning address.

4. Transition is measured 200 mV from steady state voltage with load of Figure 1B.

5. This parameter is sampled and not 100% tested.

6. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device.

WRITE CYCLE 1

DATA VALID

HIGH–Z

HIGH–Z

tAVAV

tAVWH

tWHAX

tWHDX

tWHQX

tWLWH

tAVWL

tDVWH

tWLQZ

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

tWLEH

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MCM6709AR

6

MOTOROLA FAST SRAM

WRITE CYCLE 2 

(E Controlled, See Notes 1 and 2)

MCM6709AR–6

MCM6709AR–7

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

6

7

ns

3

Address Setup Time

tAVEL

0

0

ns

Address Valid to End of Write

tAVEH

6

7

ns

Chip Enable to End of Write

tELEH,

tELWH

5

6

ns

4, 5

Data Valid to End of Write

tDVEH

3

3.5

ns

Data Hold Time

tEHDX

0

0

ns

Write Recovery Time

tEHAX

0

0

ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus

contention conditions during read and write cycles.

3. All write cycle timing is referenced from the last valid address to the first transitioning address.

4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.

5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.

WRITE CYCLE 2

DATA VALID

HIGH–Z

tAVAV

tAVEH

tAVEL

tELWH

tEHAX

tDVEH

tEHDX

A (ADDRESS)

E (CHIP ENABLE)

W (WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

tELEH

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MCM6709AR

7

MOTOROLA FAST SRAM

28 LEAD

300 MIL SOJ

CASE 810B–03

MIN

MIN

MAX

MAX

MILLIMETERS

INCHES

DIM

A

B

C

D

E

F

G

H

K

L

M

N

P

R

S

0

°

10

°

1.27 BSC

0.64 BSC

0.050 BSC

0.025 BSC

0

°

10

°

18.29

7.50

3.26

0.39

2.24

0.67

—  

0.89

0.76

8.38

6.60

0.77

18.54

7.74

3.75

0.50

2.48

0.81

0.50

1.14

1.14

8.64

6.86

1.01

0.720

0.295

0.128

0.015

0.088

0.026

—  

0.035

0.030

0.330

0.260

0.030

0.730

0.305

0.148

0.020

0.098

0.032

0.020

0.045

0.045

0.340

0.270

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. DIMENSION A & B DO NOT INCLUDE MOLD

PROTRUSION. MOLD PROTRUSION SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

3. CONTROLLING DIMENSION: INCH.

4. DIM R TO BE DETERMINED AT DATUM -T-.

5. 810B-01 AND -02 OBSOLETE, NEW STANDARD

810B-03.

28

1

15

14

L

G

M

K

DETAIL Z

DETAIL Z

S RAD

F

-B-

-A-

P

R

N

0.10 (0.004)

SEATING PLANE

-T-

0.25 (0.010)

T

S

B

0.18 (0.007)

M

T

S

A

0.18 (0.007)

T

S

B

S

S

M

C

E

24 PL

H BRK

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix

Part Number

Package (J = 300 mil SOJ)

Full Part Numbers — MCM6709ARJ6

MCM6709ARJ6R2

MCM6709ARJ7

MCM6709ARJ7R2

Shipping Method (R2 = Tape and Reel, Blank = Rails)

Speed (6 = 6 ns, 7 = 7 ns)

MCM 6709AR

X

XX

XX

Motorola reserves the right to make changes without further notice to any products herein.  Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limitation consequential or incidental damages.  “Typical” parameters can and do vary in different

applications.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  Motorola does

not convey any license under its patent rights nor the rights of others.  Motorola products are not designed, intended, or authorized for use as components in

systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of

the Motorola product could create a situation where personal injury or death may occur.  Should Buyer purchase or use Motorola products for any such

unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and   

 are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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MCM6709AR

8

MOTOROLA FAST SRAM

Literature Distribution Centers:

USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.

JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.

ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

MCM6709AR/D

*MCM6709AR/D*

CODELINE TO BE PLACED HERE