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MCM69F536C

1

MOTOROLA FAST SRAM

32K x 36 Bit Flow–Through

BurstRAM Synchronous

Fast Static RAM

The MCM69F536C is a 1M–bit synchronous fast static RAM designed to pro-

vide a burstable, high performance, secondary cache for the 68K Family,

PowerPC

, 486, i960

, and Pentium

 microprocessors. It is organized as 32K

words of 36 bits each. This device integrates input registers, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in cache data RAM applications. Synchronous design allows precise cycle

control with the use of an external clock (K). BiCMOS circuitry reduces the overall

power consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G) and Linear Burst Order (LBO) are clock (K) controlled through

positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69F536C (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and

synchronous write enable SW are provided to allow writes to either individual

bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa

controls DQa, SBb controls DQb, and so on. Individual bytes are written if the

selected byte writes SBx are asserted with SW. All bytes are written if either SGW

is asserted or if all SBx and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

The MCM69F536C operates from a 3.3 V power supply and all inputs and

outputs are LVTTL compatible.

MCM69F536C–8.5 = 8.5 ns Access / 12 ns Cycle

MCM69F536C–9 = 9 ns Access / 12 ns Cycle

MCM69F536C–10 = 10 ns Access / 15 ns Cycle

MCM69F536C–12 = 12 ns Access / 16.6 ns Cycle

Single 3.3 V + 10%, – 5% Power Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

5 V Tolerant on all Pins (Inputs and I/Os)

100–Pin TQFP Package

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

i960 and Pentium are trademarks of Intel Corp.

Order this document

by MCM69F536C/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MCM69F536C

TQ PACKAGE

TQFP 

CASE 983A–01

REV 3

2/18/98

©

 Motorola, Inc. 1998

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MCM69F536C

2

MOTOROLA FAST SRAM

WRITE

REGISTER

a

WRITE

REGISTER

b

ENABLE

REGISTER

BURST

COUNTER

ADSP

G

CLR

WRITE

REGISTER

c

WRITE

REGISTER

d

SBa

SBb

SBc

SBd

SE3

13

15

SGW

K2

ADDRESS

REGISTER

15

DATA–IN

REGISTER

32K x 36 ARRAY

SE2

LBO

ADV

K

ADSC

SA

SA1

SA0

SW

SE1

K

4

36

2

2

K2

DQa – DQd

36

FUNCTIONAL BLOCK DIAGRAM

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MCM69F536C

3

MOTOROLA FAST SRAM

PIN ASSIGNMENT

71

72

DQc

VDD

DQb

69

70

66

67

68

64

65

61

62

63

37 38

34 35 36

42 43

39 40 41

45 46

44

60

59

58

57

56

55

54

53

52

51

31 32 33

74

75

76

77

78

79

80

50

49

48

47

DQb

DQb

VSS

DQb

DQb

DQb

DQb

VSS

VDD

DQb

DQb

VDD

VSS

VSS

VDD

DQc

DQc

DQc

DQc

DQc

DQc

DQc

NC

SA

SA

SE1

SBd

K

SBc

ADV

G

ADSC

ADSP

SA0

SA

SA

SA

SA

NC

NC

NC

NC

V

SS

LBO

SA1

V

DD

VDD

NC

DQa

VSS

DQa

DQa

DQa

DQa

VSS

VDD

DQa

DQa

VSS

VDD

DQa

DQa

DQd

VDD

VSS

VSS

VDD

DQd

DQd

DQd

DQd

DQd

73

DQc

94 93

97 96 95

89 88

92 91 90

86 85

87

100 99 98

81

82

83

84

10

9

12

11

15

14

13

17

16

20

19

18

21

22

23

24

25

26

27

28

29

30

7

6

5

4

3

2

1

8

SA

SA

SW

SE2

SBb

SBa

SE3

V

SS

V

DD

SGW

NC

NC

VDD

VSS

DQd

DQd

DQd

NC

NC

SA

SA

SA

SA

SA

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MCM69F536C

4

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

Pin Locations

Symbol

Type

Description

85

ADSC

Input

Synchronous Address Status Controller: Initiates READ, WRITE, or

chip deselect cycle.

84

ADSP

Input

Synchronous Address Status Processor: Initiates READ, WRITE, or

chip deselect cycle (exception — chip deselect does not occur when

ADSP is asserted and SE1 is high).

83

ADV

Input

Synchronous Address Advance: Increments address count in

accordance with counter type selected (linear/interleaved).

(a) 51, 52, 53, 56, 57, 58, 59, 62, 63

(b) 68, 69, 72, 73, 74, 75, 78, 79, 80

(c) 1, 2, 3, 6, 7, 8, 9, 12, 13

(d) 18, 19, 22, 23, 24, 25, 28, 29, 30

DQx

I/O

Synchronous Data I/O: “x” refers to the byte being read or written

(byte a, b, c, d).

86

G

Input

Asynchronous Output Enable Input:

Low — enables output buffers (DQx pins).

High — DQx pins are high impedance.

89

K

Input

Clock: This signal registers the address, data in, and all control signals

except G and LBO.

31

LBO

Input

Linear Burst Order Input: This pin must remain in steady state (this

signal not registered or latched).  It must be tied high or low.

Low — linear burst count (68K/PowerPC).

High — interleaved burst count (486/i960/Pentium).

32, 33, 34, 35, 44, 45, 46,

47, 48, 81, 82, 99, 100

SA

Input

Synchronous Address Inputs: These inputs are registered and must

meet setup and hold times.

36, 37

SA1, SA0

Input

Synchronous Address Inputs: These pins must be wired to the two

LSBs of the address bus for proper burst operation. These inputs are

registered and must meet setup and hold times.

93, 94, 95, 96

(a)  (b)  (c)  (d)

SBx

Input

Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

a, b, c, d).  SGW overrides SBx.

98

SE1

Input

Synchronous Chip Enable: Active low to enable chip.

Negated high — blocks ADSP or deselects chip when ADSC is

asserted.

97

SE2

Input

Synchronous Chip Enable: Active high for depth expansion.

92

SE3

Input

Synchronous Chip Enable: Active low for depth expansion.

88

SGW

Input

Synchronous Global Write: This signal writes all bytes regardless of the

status of the SBx and SW signals. If only byte write signals SBx are

being used, tie this pin high.

87

SW

Input

Synchronous Write: This signal writes only those bytes that have been

selected using the byte write SBx pins. If only byte write signals SBx

are being used, tie this pin low.

4, 11, 15, 20, 27, 41, 54,

61, 65, 70, 77, 91

VDD

Supply

Power Supply: 3.3 V + 10%, – 5%.

5, 10, 17, 21, 26, 40, 55,

60, 67, 71, 76, 90

VSS

Supply

Ground.

64

NC

Input

No Connection: There is no connection to the chip. For compatibility

reasons, it is recommended that this pin be tied low for system designs

that do not have a sleep mode associated with the cache/memory

controller. Other vendors’ RAMs may have implemented this Sleep

Mode (ZZ) feature.

14, 16, 38, 39, 42, 43, 49, 50, 66

NC

No Connection: There is no connection to the chip.

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MCM69F536C

5

MOTOROLA FAST SRAM

TRUTH TABLE 

(See Notes 1 through 4)

Next Cycle

Address

Used

SE1

SE2

SE3

ADSP

ADSC

ADV

G 3

DQx

Write 2, 4

Deselect

None

1

X

X

X

0

X

X

High–Z

X

Deselect

None

0

X

1

0

X

X

X

High–Z

X

Deselect

None

0

0

X

0

X

X

X

High–Z

X

Deselect

None

X

X

1

1

0

X

X

High–Z

X

Deselect

None

X

0

X

1

0

X

X

High–Z

X

Begin Read

External

0

1

0

0

X

X

0

DQ

READ

Begin Read

External

0

1

0

1

0

X

0

DQ

READ

Continue Read

Next

X

X

X

1

1

0

1

High–Z

READ

Continue Read

Next

X

X

X

1

1

0

0

DQ

READ

Continue Read

Next

1

X

X

X

1

0

1

High–Z

READ

Continue Read

Next

1

X

X

X

1

0

0

DQ

READ

Suspend Read

Current

X

X

X

1

1

1

1

High–Z

READ

Suspend Read

Current

X

X

X

1

1

1

0

DQ

READ

Suspend Read

Current

1

X

X

X

1

1

1

High–Z

READ

Suspend Read

Current

1

X

X

X

1

1

0

DQ

READ

Begin Write

Current

X

X

X

1

1

1

X

High–Z

WRITE

Begin Write

Current

1

X

X

X

1

1

X

High–Z

WRITE

Begin Write

External

0

1

0

1

0

X

X

High–Z

WRITE

Continue Write

Next

X

X

X

1

1

0

X

High–Z

WRITE

Continue Write

Next

1

X

X

X

1

0

X

High–Z

WRITE

Suspend Write

Current

X

X

X

1

1

1

X

High–Z

WRITE

Suspend Write

Current

1

X

X

X

1

1

X

High–Z

WRITE

NOTES: 1. X = Don’t Care. 1 = logic high. 0 =  logic low.

2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.

3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.

4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times.

G must also remain negated at the completion of the write cycle to ensure proper write data hold times.

LINEAR BURST ADDRESS TABLE 

(LBO = VSS)

1st Address (External)

2nd Address (Internal)

3rd Address (Internal)

4th Address (Internal)

X . . . X00

X . . . X01

X . . . X10

X . . . X11

X . . . X01

X . . . X10

X . . . X11

X . . . X00

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X00

X . . . X01

X . . . X10

INTERLEAVED BURST ADDRESS TABLE 

(LBO = VDD)

1st Address (External)

2nd Address (Internal)

3rd Address (Internal)

4th Address (Internal)

X . . . X00

X . . . X01

X . . . X10

X . . . X11

X . . . X01

X . . . X00

X . . . X11

X . . . X10

X . . . X10

X . . . X11

X . . . X00

X . . . X01

X . . . X11

X . . . X10

X . . . X01

X . . . X00

WRITE TRUTH TABLE

Cycle Type

SGW

SW

SBa

SBb

SBc

SBd

Read

H

H

X

X

X

X

Read

H

L

H

H

H

H

Write Byte a

H

L

L

H

H

H

Write Byte b

H

L

H

L

H

H

Write Byte c

H

L

H

H

L

H

Write Byte d

H

L

H

H

H

L

Write All Bytes

H

L

L

L

L

L

Write All Bytes

L

X

X

X

X

X

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MCM69F536C

6

MOTOROLA FAST SRAM

ABSOLUTE MAXIMUM RATINGS 

(See Note 1)

Rating

Symbol

Value

Unit

Power Supply Voltage

VDD

– 0.5 to + 4.6

V

Voltage Relative to VSS for Any

Pin Except VDD

Vin, Vout

– 0.5 to  6.0

V

Output Current (per I/O)

Iout

±

 20

mA

Package Power Dissipation (See Note 2)

PD

1.6

W

Temperature Under Bias

Tbias

– 10 to 85

°

C

Storage Temperature

Tstg

– 55 to 125

°

C

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER–

ATING CONDITIONS. Exposure to higher than recommended voltages for extended

periods of time could affect device reliability.

2. Power dissipation capability is dependent upon package characteristics and use

environment. See Package Thermal Characteristics.

PACKAGE THERMAL CHARACTERISTICS

Rating

Symbol

Max

Unit

Notes

Thermal Resistance Junction to Ambient (@ 200 lfm)

Single–Layer Board

Four–Layer Board

R

θ

JA

40

25

°

C/W

1, 2

Thermal Resistance Junction to Board (Bottom)

R

θ

JB

17

°

C/W

1, 3

Thermal Resistance Junction to Case (Top)

R

θ

JC

9

°

C/W

1, 4

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient

temperature, air flow, board population, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method

1012.1).

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised

that normal precautions be taken to avoid

application of any voltage higher than maxi-

mum rated voltages to this high–impedance

circuit.

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MCM69F536C

7

MOTOROLA FAST SRAM

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70

°

C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS 

(Voltages Referenced to VSS = 0 V)

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

VDD

3.135

3.3

3.6

V

Input Low Voltage

VIL

– 0.5*

0.8

V

Input High Voltage

VIH

2.0

5.5**

V

* VIL 

– 2 V for t 

tKHKH/2.

** VIH 

 6 V for tKHKH/2.

DC CHARACTERISTICS AND SUPPLY CURRENTS

Parameter

Symbol

Min

Max

Unit

Notes

Input Leakage Current (0 V 

 Vin 

 VDD) (Excluding LBO)

Ilkg(I)

±

 1

µ

A

Output Leakage Current (0 V 

 Vin 

 VDD)

Ilkg(O)

±

 1

µ

A

AC Supply Current (Device Selected,

MCM69F536C–8.5

All Outputs Open,

MCM69F536C–9

All Inputs Toggling at Vin 

 VIL or 

VIH,

MCM69F536C–10

Cycle Time 

 tKHKH min)

MCM69F536C–12

IDDA

320

320

310

300

mA

1, 2, 3

CMOS Standby Supply Current (Deselected,

MCM69F536C–8.5

Clock (K

Cycle Time 

 tKHKH,

MCM69F536C–9

All Inputs Toggling at CMOS Levels

MCM69F536C–10

Vin 

 VSS + 0.2 V or 

 VDD – 0.2 V)

MCM69F536C–12

ISB1

150

150

140

130

mA

4

Clock Running Supply Current (Deselected, 

MCM69F536C–8.5

Clock (K

Cycle Time 

 tKHKH,

MCM69F536C–9

All Other Inputs Held to Static CMOS Levels

MCM69F536C–10

Vin 

 VSS + 0.2 V or 

 VDD – 0.2 V)

MCM69F536C–12

ISB2

55

55

50

45

mA

4

Output Low Voltage (IOL = 8 mA)

VOL

0.4

V

Output High Voltage (IOH = – 4 mA)

VOH

2.4

V

NOTES:

1. Reference AC Operating Conditions and Characteristics for input and timing.

2. All addresses transition simultaneously low (LSB) and then high (HSB).

3. Data states are all zero.

4. Device in deselected mode as defined by the Truth Table.

CAPACITANCE 

(f = 1.0 MHz, dV = 3.0 V, TA = 25

°

C, Periodically Sampled Rather Than 100% Tested)

Parameter

Symbol

Min

Typ

Max

Unit

Input Capacitance

Cin

4

6

pF

Input/Output Capacitance

CI/O

7

9

pF

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MCM69F536C

8

MOTOROLA FAST SRAM

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70

°

C, Unless Otherwise Noted)

Input Timing Measurement Reference Level

1.5 V

. . . . . . . . . . . . . . . 

Input Pulse Levels

0 to 3.0 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

Input Rise/Fall Time

1 V/ns (20% to 80%)

. . . . . . . . . . . . . . . . . . . . . . 

Output Timing Reference Level

1.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . 

Output Load

See Figure 1 Unless Otherwise Noted

. . . . . . . . . . . . . . 

READ/WRITE CYCLE TIMING 

(See Notes 1, 2, and 3)

P

S

b l

69F536C–8.5

69F536C–9

69F536C–10

69F536C–12

U i

N

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Cycle Time

tKHKH

12

12

15

16.6

ns

Clock High Pulse Width

tKHKL

4

4

5

6

ns

Clock Low Pulse Width

tKLKH

4

4

5

6

ns

Clock Access Time

tKHQV

8.5

9

10

12

ns

Output Enable to Output Valid

tGLQV

5

5

5

6

ns

Clock High to Output Active

tKHQX1

0

0

0

0

ns

4

Clock High to Output Change

tKHQX2

3

3

3

3

ns

4

Output Enable to Output Active

tGLQX

0

0

0

0

ns

4

Output Disable to Q High–Z

tGHQZ

5

5

5

6

ns

4, 5

Clock High to Q High–Z

tKHQZ

2.5

5

3

5

3

5

3

6

ns

4, 5

Setup Times:

Address

ADSP, ADSC, ADV

Data In

Write

Chip Enable

tADKH

tADSKH

tDVKH

tWVKH

tEVKH

2.5

2.5

2.5

2.5

ns

Hold Times: 

Address

ADSP, ADSC, ADV

Data In

Write

Chip Enable

tKHAX

tKHADSX

tKHDX

tKHWX

tKHEX

0.5

0.5

0.5

0.5

ns

NOTES:

1. Write is defined as either any SBx  and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP

or ADSC is asserted.

2. All read and write cycle timings are referenced from K or G.

3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.

4. This parameter is sampled and not 100% tested.

5. Measured at 

±

 200 mV from steady state.

OUTPUT

Z0 = 50 

RL = 50 

VT = 1.5 V

Figure 1. AC Test Load

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MCM69F536C

9

MOTOROLA FAST SRAM

BURST

 READ

SINGLE READ

ADSC

t KHKL

t KHKH

DQx

E

K

ADSP

ADV

Q(A)

Q(n)

BURST

 WRITE

ADSP

, SA

SA

AB

READ/WRITE CYCLES

t KLKH

CD

SE1

W

Q(B)

Q(B+1)

t KHQV

BURST

 WRAPS 

AROUND

Q(B+2)

Q(B+3)

Q(B)

D(C)

D(C+1)

D(C+2)

D(C+3)

Q(D)

t GLQV

DESELECTED

SINGLE READ

SE2, SE3

IGNORED

G

t KHQZ

t KHQX1

t KHQX2

t GHQZ

t GLQX

NOTE: E low = SE2 high and SE3 low

.

W low = SGW low and/or SW and SBx low

.

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MCM69F536C

10

MOTOROLA FAST SRAM

APPLICATION INFORMATION

The MCM69F536C BurstRAM is a high speed synchro-

nous SRAM that is intended for use primarily in secondary or

level two (L2) cache memory applications. L2 caches are

found in a variety of classes of computers — from the desk-

top personal computer to the high–end servers and trans-

action processing machines. For simplicity, the majority of L2

caches today are direct mapped and are single bank imple-

mentations. These caches tend to be designed for bus

speeds in the range of 33 to 66 MHz. At these bus rates,

flow–through (non–pipelined) BurstRAMs can be used since

their access times meet the speed requirements for a mini-

mum–latency, zero–wait state L2 cache interface. Latency is

a measure (time) of “dead” time the memory system exhibits

as a result of a memory request.

For those applications that demand bus operation at great-

er than 66 MHz or multi–bank L2 caches at 66 MHz, the pipe-

lined (register/register) version of the 32K x 36 BurstRAM

(MCM69P536) allows the designer to maintain zero–wait

state operation. Multiple banks of BurstRAMs create addi-

tional bus loading and can cause the system to otherwise

miss its timing requirements. The access time (clock–to–

valid–data) of a pipelined BurstRAM is inherently faster than

a non–pipelined device by a few nanoseconds. This does not

come without cost. The cost is latency — “dead” time.

For L2 cache designs that must minimize both latency and

wait states, flow–through BurstRAMs are the best choice in

achieving the highest performance in L2 cache design.

NON–BURST SYNCHRONOUS OPERATION

Although this BurstRAM has been designed for 68K–,

PowerPC–, 486–, i960–, and Pentium–based systems,

these SRAMs can be used in other high speed L2 cache or

memory applications that do not require the burst address

feature. Most L2 caches designed with a synchronous inter-

face can make use of the MCM69F536C. The burst counter

feature of the BurstRAM can be disabled, and the SRAM can

be configured to act upon a continuous stream of addresses.

See Figure 2.

CONTROL PIN TIE VALUES EXAMPLE 

(H 

 VIH, L 

 VIL)

Non–Burst

ADSP

ADSC

ADV

SE1

SE2

LBO

Sync Non–Burst,

Flow–Through

SRAM

H

L

H

L

H

X

NOTE: Although X is specified in the table as a don’t care, the pin

must be tied either high or low.

WRITES

READS

DQ

K

Q(B)

Q(A)

ADDR

A

B

C

D

E

F

G

H

W

Q(D)

Q(C)

D(E)

D(F)

D(G)

D(H)

G

Figure 2. Example Configuration as Non–Burst Synchronous SRAM

SE3

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MCM69F536C

11

MOTOROLA FAST SRAM

MCM

69F536C

XX

XX X

Motorola Memory Prefix

Part Number

Full Part Numbers — MCM69F536CTQ8.5

MCM69F536CTQ9

MCM69F536CTQ10

MCM69F536CTQ12

MCM69F536CTQ8.5R MCM69F536CTQ9R MCM69F536CTQ10R MCM69F536CTQ12R

Package (TQ = TQFP)

Blank = Trays, R = Tape and Reel

Speed (8.5 = 8.5 ns, 9 = 9 ns, 10 = 10 ns, 12 = 12 ns)

ORDERING INFORMATION

(Order by Full Part Number)

Motorola reserves the right to make changes without further notice to any products herein.  Motorola makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation consequential or incidental damages.  “Typical” parameters which may be provided in Motorola

data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals”

must be validated for each customer application by customer’s technical experts.  Motorola does not convey any license under its patent rights nor the rights of

others.  Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury

or death may occur.  Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Motorola was negligent regarding the design or manufacture of the part. Motorola and        are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal

Opportunity/Affirmative Action Employer.

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MCM69F536C

12

MOTOROLA FAST SRAM

TQ PACKAGE

TQFP

CASE 983A–01

PACKAGE DIMENSIONS

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

A

–––

1.60

–––

0.063

A1

0.05

0.15

0.002

0.006

A2

1.35

1.45

0.053

0.057

b

0.22

0.38

0.009

0.015

b1

0.22

0.33

0.009

0.013

c

0.09

0.20

0.004

0.008

c1

0.09

0.16

0.004

0.006

D

22.00 BSC

0.866 BSC

E

16.00 BSC

0.630 BSC

E1

14.00 BSC

0.551 BSC

e

0.65 BSC

0.026 BSC

L

0.45

0.75

0.018

0.030

L1

1.00 REF

0.039 REF

L2

0.50 REF

S

0.20

–––

0.008

–––

R1

0.08

–––

0.003

–––

R2

0.08

0.20

0.003

0.008

q

 7 

 0 

 7 

 

q  

 –––

 –––

q  

11  

13  

11  

13  

q  

11  

13  

11  

13  

1

2

3

D1

20.00 BSC

0.787 BSC

0.020 REF

_

_

_

_

_

_

_

_

_

_

_

_

_

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS –A–, –B– AND –D– TO BE DETERMINED

AT DATUM PLANE –H–.

5. DIMENSIONS D AND E TO BE DETERMINED AT

SEATING PLANE –C–.

6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.25

(0.010) PER SIDE. DIMENSIONS D1 AND B1 DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE –H–.

7. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE b DIMENSION TO EXCEED 0.45

(0.018).

A–B

0.20 (0.008) H

e

D

A–B

0.20 (0.008) C

D

A–B

0.20 (0.008) C

D

0.10 (0.004) C

0.25 (0.010)

S

0.05 (0.002)

S

A–B

M

0.13 (0.005)

D

S

C

e/2

D/2

E

E1

D1

D

D1/2

E1/2

E/2

4X

2X 30 TIPS

2X 20 TIPS

–D–

–B–

–A–

–C–

–H–

q

1

q

3

q

2

q

100

81

80

51

50

31

30

1

 

PLATING

SECTION B–B

c1

c

b

b1

ÇÇÇÇ

ÇÇÇÇ

ÉÉÉÉ

ÉÉÉÉ

BASE

METAL

A

SEATING

PLANE

VIEW AB

S

VIEW AB

A2

A1

R1

L2

L

L1

R2

GAGE PLANE

–X–

VIEW Y

B

B

X=A, B, OR D

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