background image

DATA  SHEET

Preliminary specification

File under Integrated Circuits, IC02

1996 Aug 13

INTEGRATED CIRCUITS

SAB9076H

Picture-In-Picture (PIP) controller

background image

1996 Aug 13

2

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

FEATURES

Display

Twin PIP in interlaced mode at 8-bit resolution

Sub-title mode features built in

Large display fine positioning area, both channels

independent

Only 2 Mbit required as external VDRAM

(2

×

1 Mbit or 1

×

2 Mbit)

Four 8-bit Analogue Digital Converters (ADCs; > 7-bit

performance) with clamp circuit

Most PIP modes handle interlaced pictures without joint

line error

Two PLLs which generate the line-locked clocks for the

acquisition channels

Display PLL to generate line-locked clock for the display

Three 8-bit Digital Analogue Converters (DACs)

4 : 1 : 1 data format

Data reduction factors 1 to 1, 1 to 2, 1 to 3 and 1 to 4,

horizontal and vertical independent.

I

2

C-bus programmable

Single and double PIP modes can be set

Full field still mode available

Several aspect ratios can be handled

Reduction factors can be set freely

Selection of vertical filtering type

Freeze of live pictures

Fine tuned display position, H (8-bit), V (8-bit),

both channels independent

Fine tuned acquisition area, H (4-bit), V (8-bit),

both channels independent

Eight main borders, sub-borders and background

colours selectable

Border and background brightness adjustable, 30%,

50%, 70% and 100% IRE

Several type of decoder input signals can be set.

GENERAL DESCRIPTION

The SAB9076H is a picture-in-picture controller for NTSC

TV-sets. The circuit contains ADCs, reduction circuitry,

memory control, display control and DACs.

The device inserts one or two live video signals with

original or reduced sizes into a live video signal. All video

signals are expected to be analog baseband signals.

The conversion into the digital environment and back to

the analog environment is carried out on chip. Internal

clocks are generated by two acquisition PLLs and a

display PLL.

Due to the two PIP channels and a large external memory

a wide range of PIP modes are offered. The emphasis is

put on single-PIP, double-PIP, split-screen mode and a

many multi-PIP modes.

background image

1996 Aug 13

3

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

QUICK REFERENCE DATA

Note

1. The internal system frequency is 1728 times the H

Sync

 input frequency for both the Acquisition and Display PLLs.

ORDERING INFORMATION

Note

1. When using IR reflow soldering it is recommended that the Drypack instructions in the

“Quality Reference Handbook”

(order number 9398 510 63011) are followed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V

DD

supply voltage

4.5

5.0

5.5

V

I

DD

supply current

200

mA

f

sys

system frequency

note 1

27

MHz

f

loop

PLL loop bandwidth frequency

4

kHz

t

jitter

PLL short term stability time

jitter during 1 line (64

µ

s)

4

ns

ς

PLL damping factor

0.7

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

SAB9076H

QFP100

(1)

plastic quad flat package; 100 leads (lead length 1.95 mm);

body 14

×

20

×

2.8 mm

SOT317-2

background image

1996 Aug 13

4

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

BLOCK DIAGRAM

handbook, full pagewidth

MGC962

SY

SU

SV

SAV

bias

MAV

DDD

MAV

SSD

MAV

DDA

MAV

SSA

SAV

refT

SAV

refB

71

3

4

12

11

DAV

DDD

DAV

SSD

DAV

DDA

DAV

SSA

TACLK

TC

TDCLK

TM2

TM1

TM0

A0

SCL

SDA

POR

MCV

DDD

MCV

SSD

DCV

SSD

DCV

DDD

DV

DDD

DV

SSD

V

SSD

V

DDD

SCV

SSD

SCV

DDD

SPV

DDA

SPV

SSA

DPV

SSA

DPV

DDA

MPV

DDA

MPV

SSA

91

92

84

83

100

63

18

19

22

21

20

15

16

59

60

61

62

82

81

41

42

43

44

45

46

65

66

97

98

99

SAV

DDD

SAV

SSD

SAV

DDA

SAV

SSA

78

77

69

70

SV

DDD

SV

SSD

MV

DDD

MV

SSD

68

67

13

14

CAS

RAS

49

48

DAO0 to DAO7

47

31

40

32, 34, 36,

38, 39, 37,

35, 33

DAI0 to DAI7

23, 25, 27,

29, 30, 28,

26, 24

AD0 to AD8

51, 53, 55,

57, 58, 56,

54, 52, 50

75

73

76

74

72

DY

DU

DV

DAV

bias

DAV

refT

DAV

refB

86

90

88

85

87

89

DFB

93

DT

WE

SC

DAC

AND

BUFFER

CLAMP AND ADC

MY

MU

MV

MAV

bias

MAV

refT

MAV

refB

10

6

8

5

7

9

CLAMP AND ADC

SPH

sync

SV

sync

SPV

bias

79

64

80

PLL AND CLOCK

GENERATOR

HORIZONTAL

AND

VERTICAL

FILTER

HORIZONTAL

AND

VERTICAL

FILTER

MPH

sync

MV

sync

MPV

bias

2

17

1

PLL AND CLOCK

GENERATOR

DPH

sync

DV

sync

DPV

bias

96

94

95

PLL AND CLOCK

GENERATOR

LINE MEMORY

VDRAM CONTROL AND (RE-) FORMATTING

DISPLAY

CONTROL

LINE MEMORY

I

2

C-BUS CONTROL

LINE MEMORY

SAB9076H

Fig.1  Block diagram.

background image

1996 Aug 13

5

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

PINNING

SYMBOL

PIN

I/O

TYPE

DESCRIPTION

MPV

bias

1

I/O

E027

analog bias reference for main channel

MPH

sync

2

I

HPP01

horizontal synchronization input for main channel

MAV

SSD

3

I/O

E009

digital ground for main channel ADCs and PLLs

MAV

DDD

4

I/O

E030

digital positive power supply for main channel ADCs and PLLs

MAV

bias

5

I

E027

analog bias reference input for main channel ADCs

MU

6

I

E027

analog U input for main channel

MAV

refT

7

I

E027

analog top reference voltage input for main channel ADCs

MV

8

I

E027

analog V input for main channel

MAV

refB

9

I

E027

analog bottom reference voltage input for main channel ADCs

MY

10

I

E027

analog Y input for main channel

MAV

DDA

11

I/O

E030

analog positive power supply for main channel ADCs

MAV

SSA

12

I/O

E009

analog ground for main channel ADCs

MV

SSD

13

I/O

E009

digital ground for main-channel core

MV

DDD

14

I/O

E030

digital positive power supply for main-channel core

MCV

DDD

15

I/O

E030

digital positive power supply for main-clock buffer

MCV

SSD

16

I/O

E009

digital ground for main-clock buffer

MV

sync

17

I

HPP01

vertical synchronization input for main channel

TDCLK

18

I

HPP01

test clock input for display

TC

19

I

HPP01

test control input

TM0

20

I

HPP01

test mode 0 input

TM1

21

I

HPP01

test mode 1 input

n.c.

22

not connected

DAI0

23

I

HPP01

data bus input from memory; bit 0

DAI7

24

I

HPP01

data bus input from memory; bit 7

DAI1

25

I

HPP01

data bus input from memory; bit 1

DAI6

26

I

HPP01

data bus input from memory; bit 6

DAI2

27

I

HPP01

data bus input from memory; bit 2

DAI5

28

I

HPP01

data bus input from memory; bit 5

DAI3

29

I

HPP01

data bus input from memory; bit 3

DAI4

30

I

HPP01

data bus input from memory; bit 4

DT

31

O

OPF20

memory data transfer output; active LOW

DAO0

32

O

OPF20

data bus output to memory; bit 0

DAO7

33

O

OPF20

data bus output to memory; bit 7

DAO1

34

O

OPF20

data bus output to memory; bit 1

DAO6

35

O

OPF20

data bus output to memory; bit 6

DAO2

36

O

OPF20

data bus output to memory; bit 2

DAO5

37

O

OPF20

data bus output to memory; bit 5

DAO3

38

O

OPF20

data bus output to memory; bit 3

DAO4

39

O

OPF20

data bus output to memory; bit 4

SC

40

O

OPF20

memory shift clock output

background image

1996 Aug 13

6

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

DCV

SSD

41

I/O

E009

digital ground for display-clock buffer

DCV

DDD

42

I/O

E030

digital positive power supply for display-clock buffer

DV

DDD

43

I/O

E030

digital positive power supply for display core

DV

SSD

44

I/O

E009

digital ground for display core

V

SSD

45

I/O

E009

digital ground for peripherals

V

DDD

46

I/O

E030

digital positive power supply for peripherals

WE

47

O

OPF20

memory write enable output; active LOW

CAS

48

O

OPF20

memory column address strobe output; active LOW

RAS

49

O

OPF20

memory row address strobe output; active LOW

AD8

50

O

OPF20

memory address bus output; bit 8

AD0

51

O

OPF20

memory address bus output; bit 0

AD7

52

O

OPF20

memory address bus output; bit 7

AD1

53

O

OPF20

memory address bus output; bit 1

AD6

54

O

OPF20

memory address bus output; bit 6

AD2

55

O

OPF20

memory address bus output; bit 2

AD5

56

O

OPF20

memory address bus output; bit 5

AD3

57

O

OPF20

memory address bus output; bit 3

AD4

58

O

OPF20

memory address bus output; bit 4

A0

59

I

HPF01

I

2

C-bus address 0 selection input

SCL

60

I

HPF01

shift clock input for I

2

C-bus

SDA

61

I/O

IOI41

shift I

2

C-bus input data; acknowledge I

2

C-bus output data

POR

62

I

HUP07

power-on reset input

TACLK

63

I

HPP01

test clock input for acquisition

SV

sync

64

I

HPP01

vertical synchronization input for sub-channel

SCV

SSD

65

I/O

E009

digital ground for sub-clock buffer

SCV

DDD

66

I/O

E030

digital positive power supply for sub-clock buffer

SV

DDD

67

I/O

E030

digital positive power supply for sub-channel core

SV

SSD

68

I/O

E009

digital ground for sub-channel core

SAV

SSA

69

I/O

E009

analog ground for sub-channel ADCs

SAV

DDA

70

I/O

E030

analog positive power supply for sub-channel ADCs

SY

71

I

E027

analog Y input for sub-channel

SAV

refB

72

I

E027

analog bottom reference input voltage for sub-channel ADCs

SV

73

I

E027

analog V input for sub-channel

SAV

refT

74

I

E027

analog top reference input voltage for sub-channel ADCs

SU

75

I

E027

analog U input for sub-channel

SAV

bias

76

I/O

E027

analog bias reference input/output for sub-channel ADCs

SAV

DDD

77

I/O

E030

digital positive power supply for sub-channel ADCs and PLLs

SAV

SSD

78

I/O

E009

digital ground for sub-channel ADCs and PLLs

SPH

sync

79

I

HPP01

horizontal synchronization input for sub-channel

SPV

bias

80

I/O

E027

analog bias reference input/output for sub-channel

SPV

SSA

81

I/O

E009

analog ground for sub-channel PLL

SYMBOL

PIN

I/O

TYPE

DESCRIPTION

background image

1996 Aug 13

7

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Table 1

Pin type explanation

SPV

DDA

82

I/O

E030

analog positive power supply for sub-channel PLL

DAV

DDA

83

I/O

E030

analog positive power supply for DACs

DAV

SSA

84

I/O

E009

analog ground for DACs

DAV

bias

85

I

E027

analog bias voltage reference input for DACs

DY

86

O

E027

analog Y output of DAC

DAV

refT

87

I

E027

analog top reference input voltage for DACs

DV

88

O

E027

analog V output of DAC

DAV

refB

89

I

E027

analog bottom reference input voltage for DACs

DU

90

O

E027

analog U output of DAC

DAV

SSD

91

I/O

E009

digital ground for DACs

DAV

DDD

92

I/O

E030

digital positive power supply for DACs

DFB

93

O

OPF20

fast blanking control output signal

DV

sync

94

I

HPP01

vertical synchronization input for display channel

DPH

sync

95

I

HPP01

horizontal synchronization input for display PLL

DPV

bias

96

I/O

E027

analog bias voltage reference input/output for display PLL

DPV

SSA

97

I/O

E009

analog ground for display PLL

DPV

DDA

98

I/O

E030

analog positive power supply for display PLL

MPV

DDA

99

I/O

E030

analog positive power supply for main channel PLL

MPV

SSA

100

I/O

E009

analog ground for main channel PLL

PIN TYPE

DESCRIPTION

E030

V

DD

pin; diode to V

SS

E009

V

SS

pin; diode to V

DD

E027

analog input pin; diode to V

DD

 and V

SS

HPF01

digital input pin; CMOS levels, diode to V

SS

HPP01

digital input pin; CMOS levels, diode to V

DD

 and V

SS

HUP07

digital input pin; CMOS levels with hysteresis, pull-up resistor to V

DD

, diode to V

DD

 and V

SS

IOI41

I

2

C-bus pull-down output stage; CMOS input levels, diode to V

SS

OPF20

digital output pin; CMOS levels

SYMBOL

PIN

I/O

TYPE

DESCRIPTION

background image

1996 Aug 13

8

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

handbook, full pagewidth

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

MGC963

SAB9076H

MPVbias

MPHsync

MAVSSD

MAVDDD

MAVbias

MU

MAVrefT

MV

MAVrefB

MY

MAVDDA

MAVSSA

MVSSD

MVDDD

MCVDDD

MCVSSD

MVsync

TDCLK

TC

TM0

TM1

n.c.

DAI0

DAI7

DAI1

DAI6

DAI2

DAI5

DAI3

DAI4

DT

DAO0

DAO7

DAO1

DAO6

DAO2

DAO5

DAO3

DAO4

SC

DCV

SSD

DCV

DDD

DV

DDD

DV

SSD

V

SSD

V

DDD

WE

CAS

RAS

AD8

SPVbias

SPHsync

SAVSSD

SAVDDD

SAVbias

SU

SAVrefT

SV

SAVrefB

SY

SAVDDA

SAVSSA

SVSSD

SVDDD

SCVDDD

SCVSSD

SVsync

TACLK

POR

SDA

SCL

A0

AD4

AD3

AD5

AD2

AD6

AD1

AD7

AD0

MPV

SSA

MPV

DDA

DPV

DDA

DPV

SSA

DPV

bias

DPH

sync

DV

sync

DFB

DAV

DDD

DAV

SSD

DU

DAV

refB

DV

DAV

refT

DY

DAV

bias

DAV

SSA

DAV

DDA

SPV

DDA

SPV

SSA

Fig.2  Pin configuration.

background image

1996 Aug 13

9

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

FUNCTIONAL DESCRIPTION

Pixel rate

The internal chrominance format used is 4 : 1 : 1. It is

expected that the bandwidth of the input signals is limited

to 4.5 MHz for the Y input and 1.125 MHz for the U/V input.

The Y input is sampled with a 1728

×

HS (

27.0 MHz)

clock and is filtered and down sampled to the internal

864

×

HS (

13.5 MHz) pixel rate.

The U and V inputs are multiplexed and sampled with a

432

×

HS clock and down sampled to the internal

216

×

HS (

3.375 MHz) pixel rate.

Acquisition area

Synchronisation is achieved via the acquisition H

Sync

 and

V

sync

 pins. With the acquisition fine positioning added to a

system constant the starting point of the acquisition can be

controlled.

The acquisition area is 672 pixels/line and 228 lines/field

for NTSC. Both main and sub-channels are equivalent in

handling the data.

Display mode

The internal display pixel rate is 864

×

DPH

sync

 which is

13.5 MHz. This pixel rate is up sampled by interpolation to

1728

×

DPH

sync

 before the DAC stage.

Display area

The display background is an area of 696 pixels and

238 lines. This can be put on/off by the BGON bit

independent of the PIPON bit. This area can be moved by

the display background fine positioning (BGHFP and

BGVFP registers). Its colour is determined by the BGCOL

and BGBRT registers.

Within this area PIPs are defined dependent on the PIP

mode. The PIP sizes are determined by the display

reduction factors as is shown in Table 2.

The display fine positioning determines the location of the

PIPs with respect to the background. Sub-channel and

main channel both have their independent PIP size and

location control, which is shown in Fig.3.

Table 2

PIP sizes

REDUCTION

H/1

H/2

H/3

H/4

V/1

V/2

V/3

V/4

Pixels

672

336

224

168

Lines

228

114

76

57

background image

1996 Aug 13

10

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Fig.3  Display fine positioning.

handbook, full pagewidth

MGC964

BGHFP

BGVFP

MAIN CHANNEL

SUB CHANNEL

SAHFP

MAVFP

238 lines

MAHFP

SAVFP

696 pixels

PIP modes

The two independent acquisition channels can be

controlled independently on the display side. A wide

variety of modes is possible but a subset of 7 modes is

fixed and can be set easily by the I

2

C-bus. An overview of

the preconditioned modes is given in Table 3. For all PIP

modes the main and sub-display fine positioning must be

set to obtain a display configuration.

D

ATA TRANSFER

The internal data path has an 8-bit resolution and 4 : 1 : 1

data format. The communication to the external VDRAM

takes place at 864

×

H

sync

 (both display and acquisition).

Approximately 800 8-bit words can be fetched from the

external VDRAM in one display line which is not enough to

display one complete display line with true 8-bit resolution.

Two methods of reducing data are available. One is simply

skipping the 8-bit to 6-bit (SKIP6, I

2

C-bus bit) and the other

is a small form of data reduction to come from 8-bit to 6-bit

(SMART6, I

2

C-bus bit). If both bits are set to logic 0 the

device is in true 8-bit resolution mode. For the twin PIP

mode the main channel is not placed in the VDRAM but in

an internal buffer, so still 8-bit resolution is achieved.

background image

1996 Aug 13

11

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Table 3

PIP modes

PIP

COMBINATIONS

Figures 4, 5 and 6 provide an overview of possible combinations as they can be shown on the screen.

An example of fine positioning is given in the right four columns of Table 3.

More PIP modes can be obtained by varying the horizontal and vertical reduction factors to meet correct aspect ratios

when using 16 : 9 screens.

PIP MODES

SUB-CHANNEL

MAIN CHANNEL

SUB-CHANNEL

MAIN CHANNEL

NAME

FIGURE

MODE

REDH

REDV

REDH

REDV

HFP

VFP

HFP

VFP

SP

SP small

0000

1

4

1

4

SP

SP medium

0000

1

3

1

3

SP

SP large

0000

1

2

1

2

SP

SP small

0000

1

4

1

4

SP

SP medium

0000

1

3

1

3

SP

SP large

0000

1

2

1

2

DP

DP

0000

1

2

1

2

1

2

1

2

03H

46H

57H

46H

DP

twin PIP

1001

1

2

1

1

1

2

1

1

03H

05H

57H

05H

MP3L

POP-left

0010

1

4

1

4

08H

46H

MR3R

POP-right

0010

1

4

1

4

72H

10H

MR3D

POP-double

0010

1

4

1

4

1

4

1

4

08H

10H

72H

10H

MP7

POP-double

0011

1

4

1

4

03H

05H

MP8

MP7

0011

1

4

1

4

1

2

1

2

03H

05H

44H

20H

MP4

Quatro

0001

1

2

1

2

1

2

1

2

03H

05H

03H

77H

MP9

MP9

0100

1

3

1

3

1

3

1

3

03H

05H

51H

3BH

MP16

MP16

0101

1

4

1

4

03H

05H

03H

05H

MP16

MP16 mix

0110

1

4

1

4

1

4

1

4

03H

05H

03H

77H

FFS

full field still

0000

1

1

1

1

03H

05H

FFL

full field live

1000

1

1

1

1

03H

05H

MAN

manual

0111

X

X

X

X

X

X

X

X

background image

1996 Aug 13

12

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Fig.4  PIP Modes.

handbook, halfpage

MGD588

POP-Left

handbook, halfpage

MGD598

Twin-PIP

handbook, halfpage

MGD594

SP-Small

handbook, halfpage

MGD595

SP-Medium

handbook, halfpage

MGD596

SP-Large

handbook, halfpage

MGD597

DP

background image

1996 Aug 13

13

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Fig.5  PIP Modes (continued).

handbook, halfpage

MGD589

POP-Right

handbook, halfpage

MGD590

POP-Double

handbook, halfpage

MGD591

MP7

handbook, halfpage

MGD592

MP8

handbook, halfpage

MGD593

MP13

handbook, halfpage

MGD584

Quatro

background image

1996 Aug 13

14

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Fig.6  PIP Modes (continued).

handbook, halfpage

MGD585

MP9

handbook, halfpage

MGD586

MP16

handbook, halfpage

MGD587

Full Field Still

Full Field Live

background image

1996 Aug 13

15

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

I

2

C-bus description

The I

2

C-bus provides bi-directional 2-line communication

between different ICs. The SDA line is the serial data line

and SCL serves as serial clock line. Both lines must be

connected to a positive supply via a pull-up resistor when

connected to the output stages of a device. Data transfer

may be initiated only when the bus is not busy.

The SAB9076H has the I

2

C-bus addresses 2C and 2E,

switchable by the pin A0. Valid Sub-Addresses (SA) are

00H to 18H (Table 4) and 20H to 32H (Table 6).

I

2

C-bus control is in accordance with the I

2

C-bus protocol.

First a START sequence must be put on the I

2

C-bus, then

the I

2

C-bus address of the circuit must be send, followed

by a subaddress. After this sequence the data of the

subaddresses must be sent. An auto-increment function

gives the option to send data of the incremented

subaddresses until a STOP sequence is send. Table 4

gives an overview of the I

2

C-bus addresses.

Table 4

Overview of I

2

C-bus sub-addresses

Note

1. The data bits which are not used should be set to zero.

SA

DATA BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

00H

MPIPON

SPIPON

MFREEZE

SFREEZE

PIPMODE3

PIPMODE2

PIPMODE1

PIPMODE0

01H

note 1

note 1

M1FLD

S1FLD

note 1

DNONINT

MNONINT

SNONINT

02H

DFILT

FILLOFF

SMART6

SKIP6

YTH3

YTH2

YTH1

YTH0

03H

BGHFP3

BGHFP2

BGHFP1

BGHFP0

BGVFP3

BGVFP2

BGVFP1

BGVFP0

04H

SDHFP7

SDHFP6

SDHFP5

SDHFP4

SDHFP3

SDHFP2

SDHFP1

SDHFP0

05H

SDVFP7

SDVFP6

SDVFP5

SDVFP4

SDVFP3

SDVFP2

SDVFP1

SDVFP0

06H

MDHFP7

MDHFP6

MDHFP5

MDHFP4

MDHFP3

MDHFP2

MDHFP1

MDHFP0

07H

MDVFP7

MDVFP6

MDVFP5

MDVFP4

MDVFP3

MDVFP2

MDVFP1

MDVFP0

08H

MDREDH1

MDREDH0

MDREDV1

MDREDV0

SDREDH1

SDREDH0

SDREDV1

SDREDV0

09H

MAREDH1

MAREDH0

MAREDV1

MAREDV0

SAREDH1

SAREDH0

SAREDV1

SAREDV0

0AH

MAHFP3

MAHFP2

MAHFP1

MAHFP0

SAHFP3

SAHFP2

SAHFP1

SAHFP0

0BH

SAVFP7

SAVFP6

SAVFP5

SAVFP4

SAVFP3

SAVFP2

SAVFP1

SAVFP0

0CH

MAVFP7

MAVFP6

MAVFP5

MAVFP4

MAVFP3

MAVFP2

MAVFP1

MAVFP0

0DH

MLSEL3

MLSEL2

MLSEL1

MLSEL0

SLSEL3

SLSEL2

SLSEL1

SLSEL0

0EH

MBSEL3

MBSEL2

MBSEL1

MBSEL0

SBSEL3

SBSEL2

SBSEL1

SBSEL0

0FH

BHSIZE3

BHSIZE2

BHSIZE1

BHSIZE0

BVSIZE3

BVSIZE2

BVSIZE1

BVSIZE0

10H

note 1

SBON

SBBRT1

SBBRT0

note 1

SBCOL2

SBCOL1

SBCOL0

11H

note 1

SBSON

SBSBRT1

SBSBRT0

note 1

SBSCOL2

SBSCOL1

SBSCOL0

12H

note 1

MBON

MBBRT1

MBBRT0

note 1

MBCOL2

MBCOL1

MBCOL0

13H

note 1

MBSON

MBSBRT1

MBSBRT0

note 1

MBSCOL2

MBSCOL1

MBSCOL0

14H

note 1

BGON

BGBRT1

BGBRT0

note 1

SBGCOL2

SBGCOL1

SBGCOL0

15H

note 1

note 1

note 1

SVFILT

SUVPOL

SVSPOL

SHSYNC

SFPOL

16H

note 1

note 1

note 1

MVFILT

MUVPOL

MVSPOL

MHSYNC

MFPOL

17H

note 1

FBDEL2

FBDEL1

FBDEL0

DUVPOL

DVSPOL

DHSYNC

DFPOL

18H

PEDESTV3 PEDESTV2 PEDESTV1 PEDESTV0 PEDESTU3 PEDESTU2 PEDESTU1 PEDESTU0

background image

1996 Aug 13

16

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

SA 00H PIP

REGISTER

The MPIPON and SPIPON bits switch respectively the

main and sub PIPs of the SAB9076H on or off.

The MFREEZE and SFREEZE bits make the current live

pictures for the channels main and sub frozen. The writing

to the VDRAM is stopped. The PIPMODE3 to PIPMODE0

bits set the PIP mode in accordance with Table 3.

SA 01H

DISPLAY REGISTER

The M1FLD and S1FLD

(1)

 bits control the use of the

reserved second field in the VDRAM. If this bit is set to

logic 0 then address spaces are reserved for both fields in

the VDRAM. This avoids joint line errors. Whether these

address spaces are used is dependent on the interlacing

of the input signals and the three NONINT bits. If a 1FLD

bit is set to logic 1 then only 1 address space is used in the

VDRAM for both fields. In some PIP modes the use of a

second field is not possible since there is not enough

space in the VDRAM, in these modes the 1FLD bit must be

set to logic 1. DNONINT controls the interlace mode of the

display part. If set to logic 1 then data is only read from one

field in the VDRAM. If set to logic 0 then both fields (if

available) are used for display.

The MNONINT and SNONINT bits control the interlace

mode of the acquisition blocks. If set to logic 1 then data is

only written to one field in the VDRAM (two fields remain

allocated). If set to logic 0 then both fields (if available) are

used for acquisition.

SA 02H

DISPLAY REGISTER

The DFILT bit controls an interpolating filter that changes

the internal 864 pixels data rate to the output data rate of

2

×

864 pixels. If DFILT is set to logic 1 then the filter is on.

The FILLOFF bit controls filling of PIPs when the PIP mode

is switched. If FILLOFF is set to logic 0 then all PIPs are

filled with a 30% gray until their channel has been updated.

If FILLOFF is set to logic 1 then the VDRAM content is

always visible. This is useful when a new, ‘similar’ to the

previous one, PIP mode is set. The previous data can then

be displayed.

The SMART6 and SKIP6 bits control the data transfer

mode to the external VDRAM. For modes which display a

complete line (672 pixels) a type of data reduction has to

be carried out.

Two transfer modes are available. One is simply skipping

the 8-bit data path to 6-bit (SKIP6). The other is carry out

an intelligent data reduction which retains an 8-bit

resolution (SMART6).

(1) The 1 FLD bits only operate when the NONINT bits of the

corresponding channel is set.

The YTH3 to YTH0 bits control the video output. If the

current Y-value is less then YTH

×

16 then the fast blank

is switched off, the original live background will be visible.

This feature can be used to pick up sub-titles and display

them as On-Screen Display (OSD) anywhere on the

screen.

SA 03H

DISPLAY BACKGROUND FINE POSITIONING REGISTER

The BGHFP3 to BGHFP0 bits control the horizontal

display positioning of the background. The resolution is

16 steps of 4 pixels. The BGVFP3 to BGVFP0 bits control

the vertical display positioning of the background.

The resolution is 16 steps of 2 lines/field. The background

fine positioning moves the complete display. It is a general

offset of all the PIP pictures and background. It is intended

only to adjust once the centring of all PIP modes (see

Fig.3).

SA 04H

AND

SA 05H

DISPLAY SUB

-

CHANNEL FINE

POSITIONING REGISTERS

These registers control the horizontal and vertical fine

positioning of the display sub-channel with respect to the

display background. This is the actual fine positioning (see

Fig.3). The horizontal resolution is 256 steps of 4 pixels

and the vertical resolution is 256 steps of 1 line/field.

SA 06H

AND

SA 07H

DISPLAY MAIN

-

CHANNEL FINE

POSITIONING REGISTERS

These registers control the horizontal and vertical fine

positioning off the display main-channel with respect to the

display background. This is the actual fine positioning (see

Fig.3). The horizontal resolution is 256 steps of 4 pixels

and the vertical resolution is 256 steps of 1 line/field.

SA 08H

DISPLAY REDUCTION FACTORS REGISTER

This register sets the display reduction factors,

independent of the acquisition reduction factors. It sets the

PIP size to a certain default value in such a way that the

border drawn around the PIP is just fitting.

SA 09H

ACQUISITION REDUCTION FACTORS REGISTER

This register sets the acquisition reduction factors,

independent of the display reduction factors. If the HRED

is 1 : 1 then the VRED must also be 1 : 1.

Restrictions are:

The DREDH and AREDH must be the same

The DREDV is equal or smaller than the AREDV

(e.g DREDV is 1 : 2 and AREDV is 1 : 1).

background image

1996 Aug 13

17

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

SA 0AH

TO

SA 0CH

ACQUISITION FINE POSITIONING

REGISTERS

These registers determine the start of the acquisition area.

Horizontal fine positioning can be adjusted with 16 steps of

2 pixels, vertical fine positioning can be adjusted with

256 steps of 1 line/field.

SA 0DH

TO

SA 0EH

SELECTION REGISTERS

The MLSEL3 to MLSEL0 and SLSEL3 to SLSEL0 bits

control which PIP is live. Both main channel and

sub-channel can have one live PIP. Counting is carried out

from upper-left to lower-right.

The MBSEL3 to MBSEL0 and SBSEL3 to SBSEL0 bits

control which PIP border has a different colour. Both main

channel and sub-channel can have a different PIP channel

border selection. Counting is done from upper-left to

lower-right.

SA 0FH

BORDER SIZE REGISTER

This register controls the border size. The minimum

horizontal border is 2 pixels. The minimum vertical border

is 1 line. The vertical border size is multiplied by the

FH mode number before it is displayed on the screen.

SA 10H

AND

SA 11H

BORDER COLOUR AND BORDER SELECT

COLOUR OF SUB

-

CHANNEL REGISTERS

(see Table 5)

If SBON is set to logic 1 then the border of the sub-channel

is visible. SBBRT and SBCOL control the brightness and

colour of the sub-channel border colour.

If SBSON is set to logic 1 then one sub-PIP border can

have a different colour. This border is selected by the

SBSEL3 to SBSEL0 bits.

The SBSBRT and SBSCOL bits control the brightness and

colour off the sub-border selection colour.

SA 12H

AND

SA 13H

BORDER COLOUR AND BORDER

SELECTION COLOUR OF MAIN CHANNEL REGISTERS

(see Table 5)

If MBON is set to logic 1 then the border of the main

channel is visible.

The MBBRT and MBCOL bits control the brightness and

colour of the main-channel border colour.

If MBSON is set to logic 1 then one main PIP border can

have a different colour. This border is selected by the

MBSEL3 to MBSEL0 bits.

The MBSBRT and MBSCOL bits control the brightness

and colour off the main-border selection colour.

SA 14H

BACKGROUND CONTROL REGISTER

(see Table 5)

If BGON is set to logic 1 then the background is visible.

BGBRT and BGCOL registers control the brightness and

colour of the background colour.

background image

1996 Aug 13

18

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Table 5

Colour types and brightness levels

COLOUR TYPE

BRIGHTNESS LEVEL

COLOUR

VALUE

4H

5H

6H

7H

Black

0H

0%

10%

30%

50%

Blue

1H

30%

50%

70%

100%

Red

2H

30%

50%

70%

100%

Magenta

3H

30%

50%

70%

100%

Green

4H

30%

50%

70%

100%

Cyan

5H

30%

50%

70%

100%

Yellow

6H

30%

50%

70%

100%

White

7H

60%

70%

80%

100%

Table 5 indicates how I

2

C-bus register settings control the

colour and brightness. All colour registers are similar, they

contain one on/off bit, two brightness bits and three colour

type bits. To determine which colour is visible in the event

two or more colours being displayed on the same position,

the next priority scheme is followed.

1. Sub-select colour (SBS)

2. Sub-border colour (SB)

3. Main-select colour (MBS)

4. Main-border colour (MB)

5. Background colour (BG).

SA 15H

AND

SA 16H

DECODER REGISTERS

The MVFILT and SVFILT bits can set the type of vertical

filtering. The MUVPOL and SUVPOL bits invert the UV

polarity of the incoming signals. The MVSPOL and

SVSPOL bits determine the active edge of the V

sync

 (see

Fig.7). MHSYNC and SHSYNC bits determine the timing

of the H

sync

 pulse (burstkey or H

sync

 timing). The MFPOL

and SFPOL bits can invert the field identification (ID) of the

incoming fields (see Fig.7).

SA 17H

DISPLAY SETTINGS REGISTER

The FBDEL2 to FBDEL0 bits can adjust the fast blank

delay in 8 steps of

1

2

 a clock cycle (

8 to +7). 0H is

mid-scale. The DUVPOL bit inverts the UV polarity of the

border colours.

The DVSPOL bit determines the active edge of the V

sync

(see Fig.7). The DHSYNC bit determines the timing of the

H

sync

 pulse (burstkey or H

sync

). The DFPOL bit can invert

the field identification of the incoming fields (see Fig.7).

SA 18H

PEDESTAL SETTINGS REGISTER

The PEDESTU3 to PEDESTU0 and

PEDESTV3 to PEDESTV0 bits provide the U and V DAC

outputs an offset of

8 to +7 LSB when the FBL is

switched off. This can be used to adjust the white point of

the system.

background image

1996 Aug 13

19

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Additional I

2

C-bus settings

Table 6

Overview of additional I

2

C-bus sub-addresses

Note

1. The data bits which are not used should be set to zero.

SA

DATA BYTE

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

20H

PRIO

note 1

note 1

note 1

MVRPN1

MVRPN0

SVRPN1

SVRPN0

21H

MHRPO31

MHRPO30

MHRPO21

MHRPO20

MHRPO11

MHRPO10

MHRPO01

MHRPO00

22H

MHRPN31

MHRPN30

MHRPN21

MHRPN20

MHRPN11

MHRPN10

MHRPN01

MHRPN00

23H

MHPIC7

MHPIC6

MHPIC5

MHPIC4

MHPIC3

MHPIC2

MHPIC1

MHPIC0

24H

MVPIC7

MVPIC6

MVPIC5

MVPIC4

MVPIC3

MVPIC2

MVPIC1

MVPIC0

25H

MHDIS07

MHDIS06

MHDIS05

MHDIS04

MHDIS03

MHDIS02

MHDIS01

MHDIS00

26H

MHDIS17

MHDIS16

MHDIS15

MHDIS14

MHDIS13

MHDIS12

MHDIS11

MHDIS10

27H

MHDIS27

MHDIS26

MHDIS25

MHDIS24

MHDIS23

MHDIS22

MHDIS21

MHDIS20

28H

MHDIS37

MHDIS36

MHDIS35

MHDIS34

MHDIS33

MHDIS32

MHDIS31

MHDIS30

29H

MVDIS7

MVDIS6

MVDIS5

MVDIS4

MVDIS3

MVDIS2

MVDIS1

MVDIS0

2AH

SHRPO31

SHRPO30

SHRPO21

SHRPO20

SHRPO11

SHRPO10

SHRPO01

SHRPO00

2BH

SHRPN31

SHRPN30

SHRPN21

SHRPN20

SHRPN11

SHRPN10

SHRPN01

SHRPN00

2CH

SHPIC7

SHPIC6

SHPIC5

SHPIC4

SHPIC3

SHPIC2

SHPIC1

SHPIC0

2DH

SVPIC7

SVPIC6

SVPIC5

SVPIC4

SVPIC3

SVPIC2

SVPIC1

SVPIC0

2EH

SHDIS07

SHDIS06

SHDIS05

SHDIS04

SHDIS03

SHDIS02

SHDIS01

SHDIS00

2FH

SHDIS17

SHDIS16

SHDIS15

SHDIS14

SHDIS13

SHDIS12

SHDIS11

SHDIS10

30H

SHDIS27

SHDIS26

SHDIS25

SHDIS24

SHDIS23

SHDIS22

SHDIS21

SHDIS20

31H

SHDIS37

SHDIS36

SHDIS35

SHDIS34

SHDIS33

SHDIS32

SHDIS31

SHDIS30

32H

SVDIS7

SVDIS6

SVDIS5

SVDIS4

SVDIS3

SVDIS2

SVDIS1

SVDIS0

In Manual mode more PIP modes become available with

the help of register 20H to 32H.

An overview of these I

2

C-bus registers is given in Table 6.

The meaning and relation of the I

2

C-bus registers is shown

in Fig.8. The background has a fixed size and can be fine

positioned with the BGHFP and BGHFP bits. The shown

PIPs are only for one channel (Main or Sub), the other

channel has the same control and can be displayed at the

same time. The SDHFP and MDHFP bits determine the

most left shown pixel for this channel in 256 steps of

4 pixels. The SDVFP and MDVFP bits determine the most

upper shown line for this channel in 256 steps of 1 line.

The SHPIC and MHPIC bits determine the horizontal

picture size in 256 steps of 4 pixels, the minimum value is

4 pixels. The SVPIC and MVPIC bits determine the vertical

picture size in 256 steps of 1 line, the minimum value is

1 line. The PIP mode is built-up of a maximum of four

horizontal rows. The minimum is one row, more rows can

be displayed by setting the Vertical Repetition Rate

Number VRPN bits. The distance between the rows can be

set by SVDIS and MVDIS bits. Every row is built-up of a

maximum of four PIPs. The minimum is one PIP and the

distance between the starting points of those PIPs on a

row is determined by SHDIS and MHDIS bits.

SA 20H

CONTROL REGISTER

The PRIO bit sets the priority between Main and Sub

channel. If PRIO is set to logic 0, priority is given to the Sub

channel which means that the Sub channel PIPs, if

present, are placed on top of the Main PIPs. If PRIO is set

to logic 1, the Main PIPs are set on top of the Sub PIPs.

The MVRPN and SVRPN bits determine the number of

repeated PIP rows. There is always one row visible of each

channel. If no PIPs should be visible the PIP channel must

be switched off (SA 00, bit 7 or bit 6).

background image

1996 Aug 13

20

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

SA 21H

AND

SA 2AH H

ORIZONTAL

R

EPETITION

O

FFSET

REGISTERS FOR ROW

0

TO

3

The horizontal repetition offsets (MHRPO and SHRPO

bits) are strongly related to the horizontal distance (MHDIS

and SHDIS bits). These registers set for each row a certain

grid of possible starting points for the PIPS in that row.

Every grid point has a number 0 (the most left PIP), 1, 2 or

3. The MHRPO and SHRPO bits determine the first PIP

number which will be displayed. This mechanism can be

set for each row.

SA 22H

AND

SA 2BH H

ORIZONTAL

R

EPETITION

N

UMBER

REGISTERS FOR ROW

0

TO

3

The horizontal repetition numbers (MHRPN and SHRPN

bits) determine how many times the PIPs are repeated in

a row, once the first PIP is displayed. The repeated PIPs

stay in the grid determined by the MHDIS and SHDIS bits

for that row. This mechanism can be set for each row

independent.

SA 23H

AND

SA 24H; SA 2CH

AND

SA 2DH P

ICTURE SIZE

REGISTERS

The MHPIC and SHPIC bits determine the horizontal PIP

size in 256 steps of 4 pixels. The MVPIC and SVPIC bits

determine the vertical PIP size in 256 steps of 1 line.

SA 25H

AND

SA 29H; SA 2EH

AND

SA 32H P

ICTURE

D

ISTANCE REGISTERS

For each row the distance between starting points of PIPs

can be set with the bits MHDIS and SHDIS in 256 steps of

4 pixels. The distance between two rows can be set with

the MVDIS and SVDIS bits in 256 steps of 1 line.

Acquisition Channel ADCs

Both channels convert the analog input signals to digital

signals by means of two ADCs for each channel. The input

levels of the ADCs of each channel are equal and can be

set by the AV

refT

 and AV

refB

 pins.

The reference levels are made internally by a resistor

network which divides the analog supply voltage to a

default set of preferred levels. External capacitors are

needed to filter AC components on the reference levels.

The resolution of the ADCs is 8 bit. Differential

Non-Linearity (DNL) is 7-bit; Integral Non-Linearity (INL) is

6-bit, and the sampling is carried out at the system

frequency of 27 MHz for the Y input. The U/V inputs are

multiplexed and sampled at 13.5 MHz. The analog input

signals are amplified to make maximum use of the

dynamic range of the ADCs. A bias voltage V

bias

 is used

for decoupling AC components on internal references. The

inputs should be AC-coupled and an internal clamping

circuit will clamp the input to AV

refB

 for the luminance

channels and to

 for the

chrominance channels. The clamping starts at the active

edge of the burst key.

Output DACs

The digitally processed signals are converted to analog

signals by three 8-bit DACs. The output voltages of these

DACs are default set by the DAV

refT

pin for the top level

and DAV

refB

pin for the bottom level. Default values are

1.5 V.

External Memory

For the external memory two VDRAMs of type Mitsubishi

M5M442256 are used. They have a storage capacity of

262 144 words of 4-bit each and will be used in parallel.

It is also possible to use a 2 Mbit VDRAM with a storage

capacity of 262 144 words of 8 bit each. An overview of the

timing diagrams is given in Fig.9.

AV

refT

AV

refB

2

-----------------------------------------

LSB

2

------------

+

background image

1996 Aug 13

21

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Fig.7  Vertical synchronization timing and field identification.

handbook, full pagewidth

MBE100

432

389

43

1st field

2nd field

field ID (internal)

(number of pixels)

H          (external)

sync

V          (external)

sync

V          (external)

sync

handbook, full pagewidth

MGD583

BGHFP

BGVFP

DVFP

VPIC

VDIS

HDIS

DHFP

HPIC

+

 VRPN rows

+

 HRPN columns

Fig.8  Relation of display I

2

C-bus register.

background image

1996 Aug 13

22

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Fig.9  VDRAM timing

handbook, full pagewidth

MGC970

AD0 to AD8

ROW

COLUMN

COLUMN

COLUMN

COLUMN

COLUMN

write cycle (main or sub)

WE

DAO0 to DAO7

CAS

RAS

CLOCK

AD0 to AD8

ROW

COLUMN

read cycle

WE

DT

CAS

RAS

CLOCK

CAS

RAS

CLOCK

refresh cycle 

SC

DAI0 to DAI7

shift clock cycles

(2)

(2)

(1)

(1) CLOCK = 13.5 MHz.

(2) CLOCK = 27 MHz.

background image

1996 Aug 13

23

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Human body model: see

UZW-B0/FQ-B302; The numbers of the quality specification can be found in the “Quality

Reference Handbook”. The handbook can be ordered using the code 9397 750 00192.

2. Machine model: see

UZW-B0/FQ-A302; The numbers of the quality specification can be found in the “Quality

Reference Handbook”. The handbook can be ordered using the code 9397 750 00192.

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611 part E”. The numbers of the quality specification can be found in the “Quality

Reference Handbook”. The handbook can be ordered using the code 9397 750 00192.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

V

DD

supply voltage

0.5

+6.5

V

P

max

maximum power dissipation

1.5

W

T

stg

storage temperature

25

+150

°

C

T

amb

operating ambient temperature

25

+70

°

C

V

esd

electrostatic discharge handling

Human body model

3000

(1)

V

Machine model

300

(2)

V

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

R

th j-a

thermal resistance from junction to ambient

in free air

34

K/W

background image

1996 Aug 13

24

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

CHARACTERISTICS

 V

DD

= 5.0 V; T

amb

= 25

°

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

V

DD

all positive supply voltages

4.5

5.0

5.5

V

V

SS

all ground voltages

0

V

V

DD(max)

maximum difference between supply voltages

0

100

mV

V

SS(max)

maximum difference between ground voltages

0

100

mV

I

DDDQ

quiescent current of digital supply voltages

note 1

0

50

µ

A

I

MPVDDA

main PLL supply current

6

mA

I

SPVDDA

sub PLL supply current

6

mA

I

DPVDDA

display PLL supply current

6

mA

I

MAVDDA

main ADCs supply current

40

mA

I

SAVDDA

sub ADCs supply current

40

mA

I

DAVDDA

display DACs supply current

20

mA

I

DDA(tot)

total analog supply current

115

mA

I

DDD(tot)

total digital supply current

100

mA

Analog-to-digital converter and clamping

V

refT

top reference voltage

note 2

1.9

2.1

2.3

V

V

refB

bottom reference voltage

note 2

0.3

0.4

0.5

V

V

i(Y,U,V)(p-p)

input signal amplitude (peak-to peak value)

note 2

1.2

1.5

1.6

V

I

i

input current

clamping off

0.1

µ

A

clamping on

100

µ

A

C

i

input capacitance

5

pF

f

s

sample frequency rate

note 3

1728HS

MHz

RES

resolution

6

8

bit

DNL

differential non-linearity

2.0

+2.0

LSB

INL

integral non-linearity

4.0

+4.0

LSB

α

cs

channel separation

48

dB

PSRR

power supply rejection ratio

48

dB

V

clampY

clamping voltage level Y

note 4

V

refB

V

V

clampUV

clamping voltage level U/V

note 5

V

background image

1996 Aug 13

25

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Notes

1. Digital clocks are silent, POR is V

DD

.

2. The V

refT

 and V

refB

 are made by a resistor division of the V

DD

. They can be calculated with the formulas:

 and

The analogue supply voltages are 5 V.

3. The internal system frequency is 1728 times the H

sync

 input frequency for both the acquisition and display PLLs.

4. The Y-channel is clamped to the V

refB

 of the ADCs.

5. The UV-channel is clamped to

1

/

2

(V

refT

+ V

refB

+ V

LSB

).

6. The gain of the SAB9076H is 1 under the condition that the R

L

 is 220

.

Digital-to-analog converter and output stage

V

refT

top reference voltage

2.2

2.3

2.4

V

V

refB

bottom reference voltage

0.3

0.4

0.5

V

V

o(Y,U,V)

output signal amplitude

note 6

1.5

1.6

V

R

L

load resistance

note 6

75

220

10

×

10

3

C

L

load capacitance

0

50

pF

f

s

sample frequency rate

note 3

1728HS

MHz

RES

resolution

6

8

8

bit

DNL

differential non-linearity

1.0

+1.0

LSB

INL

integral non-linearity

1.0

+1.0

LSB

α

cs

channel separation

48

dB

PSRR

power supply rejection ratio

48

dB

PLL and clock generation acquisition

f

i(PLL)

input frequency

note 3

14

15.75

18

kHz

PLL and clock generation display

f

i(PLL)

input frequency

note 3

14

15.75

18

kHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V

refT

AV

DD

2.0

5.0

--------

×

V

=

V

refB

AV

DD

0.4

5.0

--------

×

V

=

background image

1996 Aug 13

26

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

DC CHARACTERISTICS FOR THE DIGITAL PART

V

DDD

= 4.5 to 5.5 V (all V

DDD

 pins); T

amb

=

20 to +75

°

C; unless otherwise specified.

Note

1. V

i

 is attached to the V

DDD

or V

SSD

.

AC CHARACTERISTICS FOR THE DIGITAL PART

V

DDD

= 4.5 to 5.5 V (all V

DDD

 pins); T

amb

=

20 to +75

°

C; unless otherwise specified.

Note

1. The internal system frequency is1728 times the H

sync

 input frequency for both the acquisition and display PLLs.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V

IH

HIGH level input voltage

HPF01

70

%V

DD

HPP01

70

%V

DD

HUP07

80

%V

DD

IOI41

70

%V

DD

V

IL

LOW level input voltage

HPF01

30

%V

DD

HPP01

30

%V

DD

HUP07

20

%V

DD

IOI41

30

%V

DD

V

hys

hysteresis voltage

HUP07

33

%V

DD

V

OH

HIGH level output voltage

OPF20; I

OL

=

2 mA; V

DDD

= 4.5 V

4.1

V

V

OL

LOW level output voltage

IOI41; I

OL

= +4 mA; V

DDD

= 4.5 V

0.4

V

OPF20; I

OL

= +2 mA; V

DDD

= 4.5 V

0.4

V

I

LI

input leakage current

HPF01; V

DDD

= 5.5 V; note 1

0.1

1

µ

A

HPP01; V

DDD

= 5.5 V; note 1

0.1

1

µ

A

I

OZ

3-state output leakage current IOI41; V

DDD

= 5.5 V; note 1

0.2

5

µ

A

R

pu

internal pull-up resistor

HUP07

17

134

k

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

f

sys

system frequency

acquisition; note 1

27

30

MHz

display; note 1

27

30

MHz

t

r

rise time

6

25

ns

t

f

fall time

6

25

ns

background image

1996 Aug 13

27

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

TEST AND APPLICATION INFORMATION

The application diagram for 1 FH mode in a standard

configuration is shown in Fig.10. Two input signals

MCVBS and SCVBS of different sources are processed by

the SAB9076H and inserted by the YUV/RGB switch.

The synchronization of the display PLL is derived from the

deflection circuit. The main signals are also fed to the

deflection circuit and the YUV/RGB switch where the

SAB9076H signals can be inserted. The signals for

deflection can also be taken from the main channel or

sub-channel decoder.

Fig.10  Application diagram for 1 FH mode.

handbook, full pagewidth

MGC971

YUV

TO

RGB

Y

U

V

R

G

B

FLB

VS

HS (1 FH)

SAB9076H

Y

U

V

HS

VS

DECODER

MAIN

MCVBS

Y

U

V

HS

VS

DECODER

SUB

SCVBS

VDRAM

2 Mbit

HS

VS

Y

main signals

U

V

YUV/RGB SWITCH

AND

DEFLECTION

CIRCUIT

R

G

B

HS

VS

background image

1996 Aug 13

28

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

Fig.11  Application diagram.

All capacitors are 100 nF.

On the application board a ground plane should be used.

handbook, full pagewidth

1

MPVbias

MAVbias

MAVrefB

MAVrefT

MAVDDA

MAVSSA

MVDDD

MCVDDD

MCVSSD

MVSSD

MV

MU

TDCLK

TACLK

TC

TM0

TM1

n.c.

MY

MPVDDA

MAVDDD

MAVSSD

MPVSSA

MPHsync

MVsync

SPVbias

SAVbias

SAVrefB

SAVrefT

SAVDDA

SAVSSA

SVDDD

SCVDDD

SCVSSD

SVSSD

SV

SU

POR

SDA

SCL

A0

SY

SPVDDA

SAVDDD

SAVSSD

SPVSSA

SPHsync

SVsync

DPV

SSA

DAV

DDA

DAV

SSA

DAV

SSD

DAV

DDD

DPV

DDA

DPV

bias

DAV

bias

DAV

refT

DAV

refB

DPH

sync

DV

sync

DFB

DU

DV

DDD

DV

SSD

DCV

DDD

DCV

SSD

V

DDD

V

SSD

DAO0

to DAO7

RAS

CAS

WE

DT

SC

AD0 to AD8

DAI0

to DAI7

DV

DY

5

4

3

11

12

14

13

15

16

18

63

19

20

21

22

2

HOUT

CVBS/Y

CVBS/Y

main-channel input

CVBS/Y

sub-channel input

VOUT

TDA8315T

SAB9076H

V

U

Y

HOUT

CVBS/Y

VOUT

TDA8315T

V

U

Y

99

100

97

98

91

+

5 V

+

5 V

+

5 V

80

82

81

77

78

79

64

76

73

72

75

74

71

70

69

67

68

66

65

62

+

5 V

+

5 V

+

5 V

+

5 V

+

5 V

+

5 V

+

5 V

+

5 V

+

5 V

+

5 V

+

5 V

92

84

83

96

89

95

94 93

90

87

88

85

86

8

9

6

7

10

17

59

46

MGC972

45

+

5 V

42

41

+

5 V

43

44

49

48

47

31

2 Mbit MEMORY

40

32, 34,

36, 38,

39, 37,

35, 33

23, 25,

27, 29,

30, 28,

26, 24

51, 53,

55, 57,

58, 56,

54, 52,

50

61

60

9

8

8

background image

1996 Aug 13

29

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

PACKAGE OUTLINE

UNIT

A

1

A

2

A

3

b

p

c

E

(1)

e

H

E

L

L

p

Q

Z

y

w

v

θ

 REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

 IEC

 JEDEC

 EIAJ

mm

0.25

0.05

2.90

2.65

0.25

0.40

0.25

0.25

0.14

14.1

13.9

0.65

18.2

17.6

1.4

1.2

1.0

0.6

7

0

o

o

0.15

0.1

0.2

1.95

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 

1.0

0.6

 SOT317-2

92-11-17

95-02-04

D

(1)

(1)

(1)

20.1

19.9

H

D

24.2

23.6

E

Z

0.8

0.4

D

e

θ

E

A

1

A

L

p

Q

detail X

L

(A  )

3

B

30

c

b

p

E

H

A

2

D

Z D

A

Z E

e

v

M

A

1

100

81

80

51

50

31

pin 1 index

X

y

b

p

D

H

v

M

B

w

M

w

M

0

5

10 mm

scale

QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

SOT317-2

A

max.

3.20

background image

1996 Aug 13

30

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

SOLDERING

Introduction

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our

“IC Package Databook” (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all QFP

packages.

The choice of heating method may be influenced by larger

plastic QFP packages (44 leads, or more). If infrared or

vapour phase heating is used and the large packages are

not absolutely dry (less than 0.1% moisture content by

weight), vaporization of the small amount of moisture in

them can cause cracking of the plastic body. For more

information, refer to the Drypack chapter in our

“Quality

Reference Handbook” (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,

thermal conduction by heated belt. Dwell times vary

between 50 and 300 seconds depending on heating

method. Typical reflow temperatures range from

215 to 250

°

C.

Preheating is necessary to dry the paste and evaporate

the binding agent. Preheating duration: 45 minutes at

45

°

C.

Wave soldering

Wave soldering is not recommended for QFP packages.

This is because of the likelihood of solder bridging due to

closely-spaced leads and the possibility of incomplete

solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following

conditions must be observed:

A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)

soldering technique should be used.

The footprint must be at an angle of 45

°

 to the board

direction and must incorporate solder thieves

downstream and at the side corners.

Even with these conditions, do not consider wave

soldering the following packages: QFP52 (SOT379-1),

QFP100 (SOT317-1), QFP100 (SOT317-2),

QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Maximum permissible solder temperature is 260

°

C, and

maximum duration of package immersion in solder is

10 seconds, if cooled to less than 150

°

C within

6 seconds. Typical dwell time is 4 seconds at 250

°

C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300

°

C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds between

270 and 320

°

C.

background image

1996 Aug 13

31

Philips Semiconductors

Preliminary specification

Picture-In-Picture (PIP) controller

SAB9076H

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

PURCHASE OF PHILIPS I

2

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the specification

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

2

C components conveys a license under the Philips’ I

2

C patent to use the

components in the I

2

C system provided the system conforms to the I

2

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

background image

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1996

 SCA51

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. +7 095 926 5361, Fax. +7 095 564 8323

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,

Tel. +27 11 470 5911, Fax. +27 11 470 5494

South America: Rua do Rocio 220, 5th floor, Suite 51,

04552-903 São Paulo, SÃO PAULO - SP, Brazil,

Tel. +55 11 821 2333, Fax. +55 11 829 1849

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 3 301 6312, Fax. +34 3 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 632 2000, Fax. +46 8 632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2686, Fax. +41 1 481 7730

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,

Chung Hsiao West Road, Sec. 1, P.O. Box 22978,

TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 825 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,

Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 689 211, Fax. +359 2 689 102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. +45 32 88 2636, Fax. +45 31 57 1949

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. +358 615 800, Fax. +358 615 80920

France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. +30 1 4894 339/911, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722

Indonesia: see Singapore

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. +9-5 800 234 7381

Middle East: see Italy

Printed in The Netherlands

537021/50/01/pp32

 Date of release: 1996 Aug 13

Document order number:

 9397 750 01016