background image

Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OCTOBER 1996

©1996 Integrated Device Technology, Inc.

DSC-2738/6

IDT7005S/L

HIGH-SPEED

8K x 8 DUAL-PORT

STATIC RAM

FEATURES:

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• High-speed access

— Military: 20/25/35/55/70ns (max.)

— Commercial:15/17/20/25/35/55ns (max.)

• Low-power operation

— IDT7005S

Active: 750mW (typ.)

Standby: 5mW (typ.)

— IDT7005L

Active: 750mW (typ.)

Standby: 1mW (typ.)

• IDT7005 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading

more than one device

• M/

S

 = H for 

BUSY

 output flag on Master,

M/

S

 = L for 

BUSY

 input on Slave

• Busy and Interrupt Flags

• On-chip port arbitration logic

• Full on-chip hardware support of Semaphore signaling

between ports

• Fully asynchronous operation from either port

• Devices are capable of withstanding greater than 2001V

electrostatic discharge

• Battery backup operation—2V data retention

• TTL-compatible, single 5V (

±

10%) power supply

• Available in 68-pin PGA, 68-pin quad flatpack, 68-pin

PLCC, and a 64-pin TQFP

• Industrial temperature range (–40

°

C to +85

°

C) is avail-

able, tested to military electrical specifications

DESCRIPTION:

The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM.

The IDT7005 is designed to be used as a stand-alone Dual-

Port RAM or as a combination MASTER/SLAVE Dual-Port

NOTES:

1. (MASTER):

BUSY

 is output;

(SLAVE): 

BUSY

is input.

2.

BUSY 

outputs

and 

INT 

outputs

are non-tri-stated

push-pull.

FUNCTIONAL BLOCK DIAGRAM

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

1

I/O

Control

Address

Decoder

MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

R/

W

L

CE

L

OE

L

BUSY

L

A

12L

A

0L

2738 drw 01

I/O

0L

- I/O

7L

CE

L

OE

L

R/

W

L

SEM

L

INT

L

M/

S

BUSY

R

I/O

0R

-I/O

7R

A

12R

A

0R

SEM

R

INT

R

CE

R

OE

R

(2)

(1,2)

(1,2)

(2)

R/

W

R

CE

R

OE

R

R/

W

R

13

13

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

6.06

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6.06

2

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

RAM for 16-bit-or-more word systems.  Using the IDT MAS-

TER/SLAVE Dual-Port RAM approach in 16-bit or wider

memory system applications results in full-speed, error-free

operation without the need for additional discrete logic.

This device provides two independent ports with separate

control, address, and I/O pins that permit independent,

asynchronous access for reads or writes to any location in

memory.  An automatic power down feature controlled by 

CE

permits the on-chip circuitry of each port to enter a very low

standby power mode.

Fabricated using IDT’s CMOS high-performance technol-

ogy, these devices typically operate on only 750mW of power.

Low-power (L) versions offer battery backup data retention

capability with typical power consumption of 500

µ

W from a 2V

battery.

The IDT7005 is packaged in a ceramic 68-pin PGA, a 68-

pin quad flatpack, a 68-pin PLCC and a 64-pin Thin Plastic

Quad Flatpack (TQFP). Military grade product is manufac-

tured in compliance with the latest revision of MIL-STD-883,

Class B, making it ideally suited to military temperature

applications demanding the highest level of performance and

reliability.

PIN CONFIGURATIONS 

(1,2)

2738 drw 02

12

13

14

15

16

17

18

INDEX

19

20

21

22

9

8

7

6

5

4

3

2

1 68 67 66 65

27 28 29 30 31 32 33 34 35 36 37 38 39

V

CC

V

CC

I/O

1R

I/O

2R

I/O

3R

I/O

4R

INT

L

GND

A

4L

A

3L

A

2L

A

1L

A

0L

A

3R

A

0R

A

1R

A

2R

I/O

2L

A

5L

R/

W

L

11

10

M/

S

23

24

25

26

40 41 42 43

58

57

56

55

54

53

52

51

50

49

48

59

60

47

46

45

44

64 63 62 61

I/O

3L

GND

I/O

0R

V

CC

A

4R

BUSY

L

GND

BUSY

R

INT

R

A

12R

I/O

7R

N/C

GND

OE

R

R/

W

R

SEM

R

CE

R

OE

L

SEM

L

CE

L

N/C

I/O

0L

I/O

1L

IDT7005

J68-1

F68-1

PLCC / FLATPACK

TOP VIEW 

(3)

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

5R

I/O

6R

N/C

A

12L

N/C

A

11R

N/C

A

10R

A

9R

A

8R

A

7R

A

6R

A

5R

A

11L

A

10L

A

9L

A

8L

A

7L

A

6L

N/C

NOTES:

1.  All Vcc pins must be connected to the power supply.

2.  All GND pins must be connected to the ground supply.

3.  This text does not indicate orientation of the the actual part-marking.

INDEX

IDT7005

PN-64

TQFP

TOP VIEW 

(3)

8

9

10

11

12

13

14

15

16

1

2

3

4

5

6

7

46

45

44

43

42

41

40

39

38

37

36

35

34

47

48

33

17

18

19

20

32

31

30

29

28

27

26

25

24

23

22

21

49

50

51

52

63

62

61

60

59

58

57

56

55

54

53

64

I/O

2L

V

CC

GND

GND

A

4R

BUSY

L

BUSY

R

INT

R

INT

L

GND

M/

S

OE

L

A

5L

I/O

1L

R/

W

L

CE

L

SEM

L

V

CC

N/C

N/C

OE

R

CE

R

R/

W

R

SEM

R

A

12R

GND

I/O

3L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

I/O

0R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

6R

I/O

7R

A

11R

A

10R

A

9R

A

8R

A

7R

A

6R

A

5R

A

3R

A

2R

A

1R

A

0R

A

0L

A

1L

A

2L

A

3L

A

4L

A

6L

A

7L

A

8L

A

9L

A

10L

A

11L

A

12L

I/O

0L

2738 drw 03

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IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.06

3

Left Port

Right Port

Names

CE

L

CE

R

Chip Enable

R/

W

L

R/

W

R

Read/Write Enable

OE

L

OE

R

Output Enable

A

0L

 – A

12L

A

0R

 – A

12R

Address

I/O

0L

 – I/O

7L

I/O

0R

 – I/O

7R

Data Input/Output

SEM

L

SEM

R

Semaphore Enable

INT

L

INT

R

Interrupt Flag

BUSY

L

BUSY

R

Busy Flag

M/

S

Master or Slave Select

V

CC

Power

GND

Ground

PIN NAMES

2738 tbl 01

NOTES:

1. All V

CC

 pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. This text does not indicate oriention of the actual part-marking

PIN CONFIGURATIONS (CON'T.)

(1,2)

2738 drw 04

51

50

48

46

44

42

40

38

36

53

55

57

59

61

63

65

67

68

66

1

3

5

7

9

11

13

15

20

22

24

26

28

30

32

35

IDT7005

G68-1

68-PIN PGA

TOP VIEW(3)

A

B

C

D

E

F

G

H

J

K

L

47

45

43

41

34

21

23

25

27

29

31

33

2

4

6

8

10

12

14

16

18

19

17

56

58

60

62

64

11

10

09

08

07

06

05

04

03

02

01

52

54

49

39

37

A

5L

INT

L

N/C

SEM

L

CE

L

V

CC

OE

L

R/

W

L

I/O

0L

N/C

GND

GND

I/O

0R

V

CC

N/C

OE

R

R/

W

R

SEM

R

CE

R

GND

BUSY

R

BUSY

L

M/

S

INT

R

N/C

GND

A

1R

N/C

N/C

INDEX

A

4L

A

2L

A

0L

A

3R

A

2R

A

4R

A

5R

A

7R

A

6R

A

9R

A

8R

A

11R

A

10R

A

12R

A

0R

A

7L

A

6L

A

3L

A

1L

A

9L

A

8L

A

11L

A

10L

A

12L

V

CC

I/O

2R

I/O

3R

I/O

5R

I/O

6R

I/O

1R

I/O

4R

I/O

7R

I/O

1L

I/O

2L

I/O

4L

I/O

7L

I/O

3L

I/O

5L

I/O

6L

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6.06

4

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL

                   Inputs

(1)

Outputs

CE

CE

CE

CE

CE

R/

W

W

W

W

W

OE

OE

OE

OE

OE

SEM

SEM

SEM

SEM

SEM

I/O

0-7

         Mode

H

X

X

H

High-Z

Deselected:  Power-Down

L

L

X

H

DATA

IN

Write to Memory

L

H

L

H

DATA

OUT

Read Memory

X

X

H

X

High-Z

Outputs Disabled

NOTE:

2738 tbl 02

1. A

0L

 — A

12L

 is not equal to A

0R

 — A

12R.

RECOMMENDED DC OPERATING

CONDITIONS

Symbol

Parameter

Min.

Typ.

Max. Unit

V

CC

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

V

IH

Input High Voltage

2.2

6.0

(2)

V

V

IL

Input Low Voltage

–0.5

(1)

0.8

V

NOTES:

2738 tbl 06

1. V

IL

 > -1.5V for pulse width less than 10ns.

2. V

TERM

 must not exceed Vcc + 0.5V.

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Ambient

Grade

Temperature

GND

V

CC

Military

–55

°

C to +125

°

C

0V

5.0V 

±

 10%

Commercial

0

°

C to +70

°

C

0V

5.0V 

±

 10%

2738 tbl 05

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Rating

Commercial

Military

Unit

V

TERM

(2)

Terminal Voltage –0.5 to +7.0

–0.5 to +7.0

V

with Respect

to GND

T

A

Operating

0 to +70

–55 to +125

°

C

Temperature

T

BIAS

Temperature

–55 to +125

–65 to +135

°

C

Under Bias

T

STG

Storage

–55 to +125

–65 to +150

°

C

Temperature

I

OUT

DC Output

50

50

mA

Current

NOTES:

2738 tbl 04

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device.  This is a stress

rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied.  Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. V

TERM

 must not exceed Vcc + 0.5V for more than 25% of the cycle time

or 10% maximum, and is limited to < 20mA for the period of V

TERM 

> Vcc

+  0.5V.

CAPACITANCE

(1)

(T

A

 = +25

°

C, f = 1.0MHz) TQFP PACKAGE

Symbol

Parameter

Conditions

(2)

Max.

Unit

C

IN

Input Capacitance

V

IN

 = 3dV

9

pF

C

OUT

Output

V

OUT

 = 3dV

10

pF

Capacitance

NOTES:

2738 tbl 07

1. This parameter is determined by device characterization but is not

production tested.

2.   3dv references the interpolated capacitance when the input and output

signals switch from 0V to 3V or from 3V to 0V.

TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL

(1)

                 Inputs

Outputs

CE

CE

CE

CE

CE

R/

W

W

W

W

W

OE

OE

OE

OE

OE

SEM

SEM

SEM

SEM

SEM

I/O

0-7

         Mode

H

H

L

L

DATA

OUT

Read in Semaphore Flag Data 0ut

H

u

X

L

DATA

IN

Write I/O

0

 into Semaphore Flag

L

X

X

L

Not Allowed

2738 tbl 03

NOTE:

1. There are eight semaphore flags written to via I/O

0

 and read from  I/O

0 - 

I/O

15

.  These eight semaphores are addressed by A

0

 - A

2.

background image

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.06

5

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(1)

 

 

(V

CC 

= 5.0V 

±

 10%)

7005X15

7005X17

7005X20

7005X25

Test

Com'l. Only

Com'l. Only

Symbol

Parameter

Condition                    

 Version

    Typ.

(2)

 Max.    Typ.

(2)

    Max.      Typ.

(2)

  Max.    Typ.

(2)

   Max.  Unit

I

CC

Dynamic Operating     

CE

 = V

IL

, Outputs Open       

MIL.

 S

160

370

155

340

mA

Current

SEM

 = V

IH

L

150

320

145

280

(Both Ports Active)     f = f

MAX

(3)

COM.

S

170

310

170

310

160

290

155

265

L

160

260

160

260

150

240

145

220

I

SB1

Standby Current         

CE

L

 = 

CE

= V

IH

MIL.

S

20

90

16

80

mA

(Both Ports — TTL     

SEM

R

 = 

SEM

= V

IH

L

10

70

10

65

Level Inputs                f = f

MAX

(3)

COM.

S

20

60

  20

60

20

60

16

60

L

10

60

  10

50

10

50

10

50

I

SB2

Standby Current         

CE

"A"=

V

IL

 and 

CE

"B"=

V

IH

(5)

MIL.

S

95

240

90

215

mA

(One Port — TTL        Active Port Outputs Open

L

 85

210

80

180

Level Inputs)               f = f

MAX

(3)

COM.

S

105

190

  105

190

95

180

90

170

SEM

R

 = 

SEM

> V

IH

L

95

160

  95

160

85

150

80

140

I

SB3

Full Standby Current  Both Ports 

CE

and

MIL.

S

1.0

30

1.0

30

mA

(Both Ports — All       

CE

R

 > V

CC

 - 0.2V

(5)

L

0.2

10

0.2

10

CMOS Level Inputs)   V

IN

 > V

CC

 - 0.2V or

COM.

S

1.0

15

1.0

15

1.0

15

1.0

15

V

IN

 < 0.2V, f = 0

(4)

L

0.2

5

0.2

  5

0.2

5

0.2

5

                                   

SEM

R

 = 

SEM

> V

CC

 - 0.2V

I

SB4

Full Standby Current  

CE"

B" 

< 0.2V and

MIL.

S

90

225

85

200

mA

(One Port — All          

CE"

B"

 > V

CC

 - 0.2v

CMOS Level Inputs)   

SEM

R

 = 

SEM

> V

CC

 - 0.2V

L

80

200

75

170

V

IN

 > V

CC

 - 0.2V or

COM.

S

100

170

  100

170

90

155

85

145

V

IN

 < 0.2V

                                   Active Port Outputs Open,

L

90

140

  90

140

80

130

75

120

f = f

MAX

(3)

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE 

(V

CC 

= 5.0V 

±

 10%)

IDT7005S

IDT7005L

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

|I

LI

|

Input Leakage Current

(1)

V

CC

 = 5.5V, V

IN

 = 0V to V

CC

10

5

µ

A

|I

LO

|

Output Leakage Current

CE

 = V

IH

, V

OUT

 = 0V to V

CC

10

5

µ

A

V

OL

Output Low Voltage

I

OL

 = 4mA

0.4

0.4

V

V

OH

Output High Voltage

I

OH

 = -4mA

2.4

2.4

V

NOTES:

2738 tbl 09

1. "X" in part numbers indicates power rating (S or L).

2. V

CC

 = 5V, T

A

 = +25

°

C, and are not production tested. I

CC DC

 = 120mA typ.)

3. At f = f

MAX

,

 address and I/O'

 are cycling at the maximum frequency read cycle of 1/t

RC

, and using “AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5.  Port "A"may be either left or right port. Port "B" is the port opposite port "A".

NOTE:

2738 tbl 08

1.  At Vcc < 2.0V input leakages are undefined.

background image

6.06

6

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(1)

(Cont'd.)

 

(V

CC 

= 5.0V 

±

 10%)

7005X35

7005X55

7005X70

Test

Mil. Only

Symbol

Parameter

Condition

Version

Typ.

(2)

Max.

Typ.

(2)

Max. Typ.

(2)

Max. Unit

I

CC

Dynamic Operating

CE

 = V

IL

, Outputs Open

MIL.

S

150

300

150

300

140

300

mA

Current

SEM 

= V

IH

L

140

250

140

250

130

250

(Both Ports Active)

f = f

MAX

(3)

COM’L.

S

150

250

150

250

L

140

210

140

210

I

SB1

Standby Current

CE

L

 = 

CE

=

 

V

IH

MIL.

S

13

80

13

80

10

80

mA

(Both Ports — TTL

SEM

R

 = 

SEM

 = V

IH

L

10

65

10

65

10

65

Level Inputs)

f = f

MAX

(3)

COM’L.

S

13

60

13

60

L

10

50

10

50

I

SB2

Standby Current

CE

"A"

=V

IL

 and

 CE

"B"

=V

IL

(5)

MIL.

S

85

190

85

190

80

190

mA

(One Port — TTL

Active Port Outputs Open

L

75

160

75

160

70

160

Level Inputs)

f = f

MAX

(3)

COM’L.

S

85

155

85

155

SEM

R

 = 

SEM

= V

IH

L

75

130

75

130

I

SB3

Full Standby Current

Both Ports 

CE

and

MIL.

S

1.0

30

1.0

30

1.0

30

mA

(Both Ports — All

CE

R

 > V

CC

 - 0.2V

L

0.2

10

0.2

10

0.2

10

CMOS Level Inputs)

V

IN

 > V

CC

 - 0.2V or

COM’L.

S

1.0

15

1.0

15

V

IN

 < 0.2V, f = 0

(4)

L

0.2

5

0.2

5

SEM

R

 = 

SEM

> V

CC

 - 0.2V

I

SB4

Full Standby Current

One Port 

CE

"A" 

< 0.2V

MIL.

S

80

175

80

175

75

175

mA

(One Port — All

CE

"B"

 > V

CC

 - 0.2V

(5)

CMOS Level Inputs)

SEM

R

 = 

SEM

> V

CC

 - 0.2V

L

70

150

70

150

65

150

V

IN

 > V

CC

 - 0.2V or

COM’L.

S

80

135

80

135

V

IN

 < 0.2V

Active Port Outputs Open,

L

70

110

80

110

f = f

MAX

(3)

NOTES:

2738 tbl 10

1. "X" in part numbers indicates power rating (S or L).

2. V

CC

 = 5V, T

A

 = +25

°

C and are not production tested. I

CC DC

 = 120mA (typ.)

3. At f = f

MAX

,

 address and I/O'

 are cycling at the maximum frequency read cycle of 1/t

RC

, and using “AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5.   Port "A" may be either left or right port. Port "B" is the port opposite port "A".

DATA RETENTION MODE

V

CC

CE

2738 drw 05

4.5V

t

CDR

t

R

V

IH

V

DR

V

IH

4.5V

V

DR

2V

DATA RETENTION WAVEFORM

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)

(V

LC

 = 0.2V, V

HC

 = V

CC

 - 0.2V)

(4)

Symbol

Parameter

Test Condition

Min.

Typ.

(1)

Max.

Unit

V

DR

V

CC

 for Data Retention

V

CC

 = 2V

2.0

V

I

CCDR

Data Retention Current

CE

 > V

HC

MIL.

100

4000

µ

A

V

IN

 > V

HC

 or 

 V

LC

COM’L.

100

1500

t

CDR

(3)

Chip Deselect to Data Retention Time

SEM

 > V

HC

0

ns

t

R

(3)

Operation Recovery Time

t

RC

(2)

ns

NOTES:

2738 tbl 11

1. T

A

 = +25

°

C, V

CC

 = 2V, and are not production tested.

2. t

RC

 = Read Cycle Time

3. This parameter is guaranteed by device characteriation, but is not production tested.

background image

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.06

7

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

5ns Max.

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

Figure 1 and 2

2738 tbl 12

IDT7005X35

IDT7005X55

IDT7005X70

Mil. Only

 

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

t

RC

Read Cycle Time

35

55

70

ns

t

AA

Address Access Time

35

55

70

ns

t

ACE

Chip Enable Access Time

(3)

35

55

70

ns

t

AOE

Output Enable Access Time

20

30

35

ns

t

OH

Output Hold from Address Change

3

3

3

ns

t

LZ

Output Low-Z Time

(1, 2)

3

3

3

ns

t

HZ

Output High-Z Time

(1, 2)

15

25

30

ns

t

PU

Chip Enable to Power Up Time

(2)

0

0

0

ns

t

PD

Chip Disable to Power Down Time

(2)

35

50

50

ns

t

SOP

Semaphore Flag Update Pulse (

OE

 or 

SEM

)

15

15

15

ns

t

SAA

Semaphore Address Access Time

35

55

70

ns

NOTES:

2738 tbl 13

1. Transition is measured 

±

500mV from Low or High-impedance voltage with Output Test Load (Figures 2).

2. This parameter is guaranteed by device characterization but not production tested.

3. To access RAM, 

CE

 = V

IL and

 

SEM

 = V

IH

. To access semaphore, 

CE

 = V

IH and 

SEM

 = V

IL.

4. "X" in part numbers indicates power rating (S or L).

1250

30pF

775

DATA

OUT

BUSY

INT

5V

5V

1250

5pF

775

DATA

OUT

2738 drw 06

Figure 1.  AC Output Test Load

Figure 2. Output Load

(For t

LZ

, t

HZ

, t

WZ

, t

OW

)

Including scope and jig

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(4)

AC ELECTRICAL CHARACTERISTICS OVER THE

          IDT7005X15

IDT7005X17

IDT7005X20

IDT7005X25

         Com'l. Only

Com'l. Only

 

Symbol

                Parameter

               Min.    Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

t

RC

Read Cycle Time

               15     —

17

20

25

ns

t

AA

Address Access Time

               —      15

 —

17

20

25

ns

t

ACE

Chip Enable Access Time

(3)

               —      15

17

20

25

ns

t

AOE

Output Enable Access Time

               —      10

10

12

13

ns

t

OH

Output Hold from Address Change

               3

3

3

3

ns

t

LZ

Output Low-Z Time

(1, 2)

               3       —

3

3

3

ns

t

HZ

Output High-Z Time

(1, 2)

     10

10

12

15

ns

t

PU

Chip Enable to Power Up Time

(2)

               0

0

0

0

ns

t

PD

Chip Disable to Power Down Time

(2)

     15

17

20

25

ns

t

SOP

Semaphore Flag Update Pulse (

OE

 or 

SEM

)      10

10

10

10

ns

t

SAA

Semaphore Address Access Time

      15

17

20

25

ns

background image

6.06

8

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

WAVEFORM OF READ CYCLES

(5)

NOTES:

1. Timing depends on which signal is asserted last, 

OE

 or 

CE

.

2. Timing depends on which signal is de-asserted first, 

CE

 or 

OE.

3.  t

BDD 

delay is required only in cases where the opposite port is completing a write operation to the same address location.  For simultaneous   read operations

BUSY

 has no relation to valid output  data.

4. Start of valid data depends on which timing becomes effective last t

AOE

, t

ACE

, t

AA

 or t

BDD

.

5.

SEM

 = V

IH

.

CE

2738 drw 08

t

PU

I

CC

I

SB

t

PD

50%

50%

t

RC

R/

W

CE

ADDR

t

AA

OE

2738 drw 07

(4)

t

ACE

(4)

t

AOE

(4)

(1)

t

LZ

t

OH

(2)

t

HZ

(3, 4)

t

BDD

DATA

OUT

BUSY

OUT

VALID DATA

(4)

TIMING OF POWER-UP POWER-DOWN

background image

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.06

9

     IDT7005X15

IDT7005X17

IDT7005X20

IDT7005X25

       Com'l. Only

Com'l. Only

Symbol

Parameter

        Min.    Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

t

WC

Write Cycle Time

         15

17

20

25

ns

t

EW

Chip Enable to End-of-Write

(3)

         12

12

15

20

ns

t

AW

Address Valid to End-of-Write

          12

12

15

20

ns

t

AS

Address Set-up Time

(3)

          0

0

0

0

ns

t

WP

Write Pulse Width

         12

12

15

20

ns

t

WR

Write Recovery Time

          0

0

0

0

ns

t

DW

Data Valid to End-of-Write

         10

10

15

15

ns

t

HZ

Output High-Z Time

(1, 2)

          —

10

10

12

15

ns

t

DH

Data Hold Time

(4)

          0

0

0

0

ns

t

WZ

Write Enable to Output in High-Z

(1, 2)

          —

10

10

12

15

ns

t

OW

Output Active from End-of-Write

(1, 2, 4)

          0

0

0

0

ns

t

SWRD

SEM

 Flag Write to Read Time

          5

5

5

5

ns

t

SPS

SEM

 Flag Contention Window

         5

5

5

5

ns

IDT7005X35

IDT7005X55

IDT7005X70

Mil. Only

   Symbol                              Parameter

                   Min.         Max.      Min.       Max.        Min.      Max.     Unit

WRITE CYCLE

t

WC

Write Cycle Time

35

55

70

ns

t

EW

Chip Enable to End-of-Write

(3)

30

45

50

ns

t

AW

Address Valid to End-of-Write

30

45

50

ns

t

AS

Address Set-up Time

(3)

0

0

0

ns

t

WP

Write Pulse Width

25

40

50

ns

t

WR

Write Recovery Time

0

0

0

ns

t

DW

Data Valid to End-of-Write

15

30

40

ns

t

HZ

Output High-Z Time

(1, 2)

15

25

30

ns

t

DH

Data Hold Time

(4)

0

0

0

ns

t

WZ

Write Enable to Output in High-Z

(1, 2)

15

25

30

ns

t

OW

Output Active from End-of-Write

(1, 2, 4)

0

0

0

ns

t

SWRD

SEM

 Flag Write to Read Time

5

5

5

ns

t

SPS

SEM

 Flag Contention Window

5

5

5

ns

NOTES:

2738 tbl 14

1. Transition is measured 

±

500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization but is not production tested.

3. To access RAM, 

CE

 = V

IL

,  

SEM

 = V

IH

.  To access semaphore, 

CE

 = V

IH

 and 

SEM

 = V

IL

.  Either condition must be valid for the entire t

EW

 time.

4. The specification for t

DH

 must be met by the device supplying write data to the RAM under all operating conditions.  Although t

DH

 and t

OW

 

values will vary

over voltage and temperature, the actual t

DH

 will always be smaller than the actual t

OW

.

5. "X" in part numbers indicates power rating (S or L).

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE

 (5)

background image

6.06

10

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

W

W

W

W

W

 CONTROLLED TIMING

(1,5,8)

NOTES:

1. R/

W

 or 

CE

 must be high during all address transitions.

2. A write occurs during the overlap (t

EW

 or t

WP

) of a Low 

CE

 and a Low R/

W

 for memory array writing cycle.

3. t

WR

 is measured from the earlier of 

CE

 or R/

W

 (or 

SEM

 or R/

W

) going High to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the 

CE

 or 

SEM

 Low transition occurs simultaneously with or after the R/

W

 Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, 

CE

  or R/

W

.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/- 500mv from steady state with the Output

Test Load (Figure 2).

8. If 

OE

 is Low during R/

W

 controlled write cycle, the write pulse width must be the larger of

 

t

WP

 or (t

WZ

 + t

DW

) to allow the I/O drivers to turn off and data

to be placed on the bus for the required t

DW

.  If 

OE

 is High during an R/

W

 controlled write cycle, this requirement does not apply and the write pulse can

be as short as the specified t

WP

.

9.  To access RAM,  

CE

 = V

IH and 

SEM

 = V

IL. 

To access semaphore

 

CE

 = V

IH

 and 

SEM

 = V

IL. 

t

EW 

must be met for either condition.

TIMING WAVEFORM OF WRITE CYCLE NO. 2, 

CE

CE

CE

CE

CE

 CONTROLLED TIMING

(1,5)

R/

W

t

WC

t

HZ

t

AW

t

WR

t

AS

t

WP

DATA

OUT

(2)

t

WZ

t

DW

t

DH

t

OW

OE

ADDRESS

DATA

IN

CE

 or 

SEM

(6)

(4)

(4)

(3)

2738 drw 09

(7)

(7)

(9)

2738 drw 10

t

WC

t

AS

t

WR

t

DW

t

DH

ADDRESS

DATA

IN

R/

W

t

AW

t

EW

(3)

(2)

(6)

(9)

CE

 or 

SEM

background image

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.06

11

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE

(1)

TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION

(1,3,4)

NOTES:

1.

CE

 = V

IH

 for the duration of the above timing (both write and read cycle).

2. "DATA

OUT

 VALID" represents all I/O's (I/O

0

-I/O

7

) equal to the semaphore value.

SEM

"A"

2738 drw 12

t

SPS

MATCH

R/

W

"A"

MATCH

A

0"A"

-A

2"A"

SIDE

“A”

(2)

SEM

"B"

R/

W

"B"

A

0"B"

-A

2"B"

SIDE

“B”

(2)

NOTES:

1. D

OR

 = D

OL

 = V

IL

CE

R

 = 

CE

L

 = V

IH

. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start.

2. All timing is the same for left and right ports. Port “A” may be either left or right port.  “B” is the opposite from port “A”.

3. This parameter is measured from R/

W

"A"

 or 

SEM

"A"

 going High to R/

W

"B"

 or 

SEM

"B"

 going High.

4. If t

SPS

 is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.

SEM

2738 drw 11

t

AW

t

EW

t

SOP

I/O

VALID ADDRESS

t

SAA

R/

W

t

WR

t

OH

t

ACE

VALID ADDRESS

DATA

IN

VALID

DATA

OUT

t

DW

t

WP

t

DH

t

AS

t

SWRD

t

AOE

Read Cycle

Write Cycle

A

0

-A

2

OE

VALID

(2)

background image

6.06

12

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

t

WH

Write Hold After 

BUSY

(5)

25

25

25

ns

BUSY TIMING (M/

SSSSS

 = V

IL

)

t

WB

BUSY

 Input to Write

(4)

0

0

0

ns

t

WH

Write Hold After 

BUSY

(5)

25

25

25

ns

PORT-TO-PORT DELAY TIMING

t

WDD

Write Pulse to Data Delay

(1)

60

80

95

ns

t

DDD

Write Data Valid to Read Data Delay

(1)

45

65

80

ns

BUSY TIMING (M/

SSSSS

 = V

IL

)

t

WB

BUSY

 Input to Write

(4)

                     0         —

0

0

0

ns

t

WH

Write Hold After 

BUSY

(5)

                   12         —

13

15

17

ns

PORT-TO-PORT DELAY TIMING

t

WDD

Write Pulse to Data Delay

(1)

                     —         30

30

45

50

ns

t

DDD

Write Data Valid to Read Data Delay

(1)

                  —

           

25

25

35

35

ns

                 IDT7005X15  IDT7005X17

IDT7005X20

IDT7005X25

                 Com'l. Only  Com'l. Only

Symbol

Parameter                       Min.   Max.    Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/

SSSSS

 = V

IH

)

t

BAA

BUSY

 Access Time from Address Match               —       15

17

20

20

ns

t

BDA

BUSY

 Disable Time from Address Not Matched    —       15

17

20

20

ns

t

BAC

BUSY

 Access Time from Chip Enable Low            —       15

17

20

20

ns

t

BDC

BUSY

 Disable Time from Chip Enable High           —       15

17

17

17

ns

t

APS

Arbitration Priority Set-up Time

(2)

                    5         —         5

5

5

ns

t

BDD

BUSY

 Disable to Valid Data

(3)

                      —       18

18

30

30

ns

t

WH

Write Hold After 

BUSY

(5)

                   12         —

13

15

17

ns

IDT7005X35

IDT7005X55

IDT7005X70

Mil. Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/

SSSSS

 = V

IH

)

t

BAA

BUSY

 Access Time from Address Match

20

45

45

ns

t

BDA

BUSY

 Disable Time from Address Not Matched

20

40

40

ns

t

BAC

BUSY

 Access Time from Chip Enable Low

20

40

40

ns

t

BDC

BUSY

 Disable Time from Chip Enable High

20

35

35

ns

t

APS

Arbitration Priority Set-up Time

(2)

5

5

5

ns

t

BDD

BUSY

 Disable to Valid Data

(3)

35

40

45

ns

NOTES:

2738 tbl 15

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and 

BUSY

".

2. To ensure that the earlier of the two ports wins.

3. t

BDD

 is a calculated parameter and is the greater of 0, t

WDD

 – t

WP

 (actual), or t

DDD

 – t

DW

 (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".

5. To ensure that a write cycle is completed on port "B"  after contention on port "A".

6. "X" in part numbers indicates power rating (S or L).

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(6)

background image

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.06

13

TIMING WAVEFORM  OF WRITE WITH PORT-TO-PORT READ WITH 

BUSY

BUSY

BUSY

BUSY

BUSY

 

(M/S = V

IH

)

(2,4,5)

NOTES:

1.  t

WH

  must be met for both 

BUSY

  input (slave) and output (master).

2.  

BUSY

 is asserted on Port "B" Blocking R/

W

"B", until 

BUSY

"B" goes High.

3.  t

WB

 is only for the 'Slave' Version.

NOTES:

1. To ensure that the earlier of the two ports wins. t

APS

 

is ignored for  for M/

= V

IL (slave).

2.

CE

L

 = 

CE

R

 = V

IL.

3.

OE

 = V

IL

 for the reading port.

4. If M/

S

 = V

IL 

(slave), 

BUSY

 is an input.  Then for this example 

BUSY

"A"

 = V

IH

 and 

BUSY

"B"

 input is shown above.

5.   All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".

2738 drw 13

t

DW

t

APS

ADDR

"A"

t

WC

DATA

OUT "B"

MATCH

t

WP

R/

W

"A"

DATA

IN "A"

ADDR

"B"

t

DH

VALID

(1)

MATCH

BUSY

"B"

t

BDA

VALID

t

BDD

t

DDD

(3)

t

WDD

2738 drw 14

R/

W

"A"

BUSY

"B"

t

WP

t

WB

R/

W

"B"

t

WH

(2)

(3)

(1)

TIMING WAVEFORM OF WITH WRITE 

BUSY

BUSY

BUSY

BUSY

BUSY

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HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT7005X35

IDT7005X55

IDT7005X70

Mil. Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

t

AS

Address Set-up Time

0

0

0

ns

t

WR

Write Recovery Time

0

0

0

ns

t

INS

Interrupt Set Time

25

40

50

ns

t

INR

Interrupt Reset Time

25

40

50

ns

IDT7005X15

IDT7005X17

IDT7005X20

IDT7005X25

Com'l. Only

Com'l. Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

t

AS

Address Set-up Time

  0

0

0

0

ns

t

WR

Write Recovery Time

  0

0

0

0

ns

t

INS

Interrupt Set Time

  0

15

15

20

20

ns

t

INR

Interrupt Reset Time

  0

15

15

20

20

ns

WAVEFORM OF BUSY ARBITRATION CONTROLLED BY 

CE

CE

CE

CE

CE

 TIMING

 

(M/

SSSSS

 = V

IH

)

(1)

2738 drw 15

ADDR

"A"

and 

"B"

ADDRESSES MATCH

CE

"A"

CE

"B"

BUSY

"B"

t

APS

t

BAC

t

BDC

(2)

NOTE:

2738 tbl 16

1. "X" in part numbers indicates power rating (S or L).

NOTES:

1. All timing is the same for left and right ports.  Port “A” may be either the left or right port.  Port “B” is the port opposite from port “A”.

2. If t

APS

 is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.

2738 drw 16

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

t

APS

t

BAA

t

BDA

(2)

MATCHING ADDRESS "N"

WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING

(M/

SSSSS

 = V

IH

)

(1)

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE

(1)

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IDT7005S/L

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MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.06

15

WAVEFORM OF INTERRUPT TIMING

(1)

TRUTH TABLES

TRUTH TABLE I — INTERRUPT FLAG

(1,4)

Left Port

Right Port

R/

W

W

W

W

W

L

CE

CE

CE

CE

CE

L

OE

OE

OE

OE

OE

L

A

12L

-A

0L

INT

INT

INT

INT

INT

L

R/

W

W

W

W

W

R

CE

CE

CE

CE

CE

R

OE

OE

OE

OE

OE

R

A

12R

-A

0R

INT

INT

INT

INT

INT

R

Function

L

L

X

1FFF

X

X

X

X

X

L

(2)

Set Right 

INT

R

 Flag

X

X

X

X

X

X

L

L

1FFF

H

(3)

Reset Right 

INT

R

 Flag

X

X

X

X

L

(3)

L

L

X

1FFE

X

Set Left 

INT

L

 Flag

X

L

L

1FFE

H

(2)

X

X

X

X

X

Reset Left 

INT

L

 Flag

NOTES:

2738 tbl 17

1. Assumes 

BUSY

L

 = 

BUSY

R

 = V

IH

.

2. If 

BUSY

L

 = V

IL

, then no change.

3. If 

BUSY

R

 = V

IL

, then no change.

4.

INT

R and 

 

INT

must be initialized at power-up.

NOTES:

1. All timing is the same for left and right ports.  Port “A” may be either the left or right port.  Port “B” is the port opposite from port “A”.

2. See Interrupt truth table.

3. Timing depends on which enable signal (

CE

 or R/

W

) asserted last.

4. Timing depends on which enable signal  (

CE

 or R/

W

) is de-asserted first.

2738 drw 18

ADDR

"B"

INTERRUPT CLEAR ADDRESS

CE

"B"

OE

"B"

t

AS

t

RC

(3)

t

INR

(3)

INT

"B"

(2)

2738 drw 17

ADDR

"A"

INTERRUPT SET ADDRESS

CE

"A"

R/

W

"A"

t

AS

t

WC

t

WR

(3)

(4)

t

INS

(3)

INT

"B"

(2)

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6.06

16

IDT7005S/L

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TRUTH TABLE II —

ADDRESS BUSY ARBITRATION

Inputs

Outputs

A

0L

-A

12L

CE

CE

CE

CE

CE

L

CE

CE

CE

CE

CE

R

A

0R

-A

12R

BUSY

BUSY

BUSY

BUSY

BUSY

L

(1)

BUSY

BUSY

BUSY

BUSY

BUSY

R

(1)

Function

X

X

NO MATCH

H

H

Normal

H

X

MATCH

H

H

Normal

X

H

MATCH

H

H

Normal

L

L

MATCH

(2)

(2)

Write Inhibit

(3)

NOTES:

2738 tbl 18

1. Pins 

BUSY

L

 and 

BUSY

R

 are both outputs when the part is configured as a master.  Both are inputs when configured as a slave.  

BUSY

X

 outputs on the

IDT7005 are push-pull, not open drain outputs.  On slaves the  

BUSY

X

 input internally inhibits writes.

2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port.  'H' if the inputs to the opposite port became stable after

the address and enable inputs of this port.  If t

APS

 is not met, either 

BUSY

L

 or 

BUSY

R

 = Low will result.   

BUSY

L

 and 

BUSY

R

 outputs can not be low

simultaneously.

3. Writes to the left port are internally ignored when 

BUSY

L

 outputs are driving low regardless of actual logic level on the pin.  Writes to the right port are

internally ignored when 

BUSY

R

 outputs are driving low regardless of actual logic level on the pin.

TRUTH TABLE III — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE

(1,2)

Functions

D

0

 - D

7

 Left

D

0

 - D

7

 Right

Status

No Action

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

Right Port Writes "0" to Semaphore

0

1

No change.  Right side has no write access to semaphore

Left Port Writes "1" to Semaphore

1

0

Right port obtains semaphore token

Left Port Writes "0" to Semaphore

1

0

No change.  Left port has no write access to semaphore

Right Port Writes "1" to Semaphore

0

1

Left port obtains semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

Right Port Writes "0" to Semaphore

1

0

Right port has semaphore token

Right Port Writes "1" to Semaphore

1

1

Semaphore free

Left Port Writes "0" to Semaphore

0

1

Left port has semaphore token

Left Port Writes "1" to Semaphore

1

1

Semaphore free

FUNCTIONAL DESCRIPTION

The IDT7005 provides two ports with separate control,

address and I/O pins that permit independent access for reads

or writes to any location in memory. The IDT7005 has an

automatic power down feature controlled by 

CE

. The 

CE

controls on-chip power down circuitry that permits the respec-

tive port to go into a standby mode when not selected (

CE

high).  When a port is enabled, access to the entire memory

array is permitted.

INTERRUPTS

If the user chooses to use the interrupt function, a memory

location (mail box or message center) is assigned to each port.

The left port interrupt flag (

INT

L

) is asserted when the right port

writes to memory location 1FFE (HEX), where a write is

defined as 

CE

 = R/

W

= V

IL 

per the Truth Table

 

.  The left port

clears the interrupt through access of address location 1FFE

when  

CE

 = 

OE

 = V

IL.

 For this example, R/

W

 is a "don't care".

Likewise, the right port interrupt flag (

INT

R

) is asserted when

the left port writes to memory location 1FFF (HEX) and to clear

the interrupt flag (

INT

R

), the right port must read the memory

location 1FFF.  The message (8 bits) at 1FFE or 1FFF is user-

defined, since it is an addressable SRAM location.  If the

interrupt function is not used, address locations 1FFE and

1FFF are not used as mail boxes, but as part of the random

access memory.  Refer to Truth Table for the interrupt opera-

tion.

BUSY LOGIC

Busy Logic provides a hardware indication that both ports

of the RAM have accessed the same location at the same

time.  It also allows one of the two accesses to proceed and

signals the other side that the RAM is “Busy”.  The busy pin can

then be used to stall the access until the operation on  the other

side is completed.  If a write operation has been attempted

from the side that receives a busy indication, the write signal

is gated internally to prevent the write from proceeding.

NOTES:

2738 tbl 19

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005.

2. There are eight semaphore flags written to via I/O

0

 and read from all I/O

's 

(I/O

0-

I/O

7

).  These eight semaphores are addressed by A

0

 - A

2

.

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The use of busy logic is not required or desirable for all

applications.  In some cases it may be useful to logically OR

the busy outputs together and use any busy indication as an

interrupt source to flag the event of an illegal or illogical

operation. If the write inhibit function of busy logic is not

desirable, the busy logic can be disabled by placing the part

in slave mode with the M/

S

 pin.  Once in slave mode the 

BUSY

pin operates solely as a write inhibit input pin. Normal opera-

tion can be programmed by tying the 

BUSY

 pins high.  If

desired, unintended write operations can be prevented to a

port by tying the busy pin for that port low.

The busy outputs on the IDT 7005 RAM in master mode,

are push-pull type outputs and do not require pull up resistors

to operate.  If these RAMs are being expanded in depth, then

the busy indication for the resulting array requires the use of

an external AND gate.

WIDTH EXPANSION WITH BUSY LOGIC

MASTER/SLAVE ARRAYS

When expanding an IDT7005 RAM array in width while

using busy logic, one master part is used to decide which side

of the RAM array will receive a busy indication, and to output

that indication.  Any number of slaves to be addressed in the

same address range as the master, use the busy signal as a

write inhibit signal.  Thus on the IDT7005 RAM the busy pin is

an output if the part is used as a master (M/

S

 pin = H), and the

busy pin is an input if the part used as a slave (M/

S

 pin = L) as

shown in Figure 3.

If two or more master parts were used when expanding in

width, a split decision could result with one master indicating

busy on one side of the array and another master indicating

busy on one other side of the array.  This would inhibit the write

operations from one port for part of a word and inhibit the write

operations from the other port for the other part of the word.

The busy arbitration, on a master, is based on the chip

enable and address signals only. It ignores whether an access

is a read or write. In a master/slave array, both address and

chip enable must be valid long enough for a busy flag to be

Figure 3.  Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs.

output from the master before the actual write pulse can be

initiated with the R/

W

 signal.  Failure to observe this timing can

result in a glitched internal write inhibit signal and corrupted

data in the slave.

SEMAPHORES

The IDT7005 is an extremely fast Dual-Port 8K x 8 CMOS

Static RAM with an additional 8 address locations dedicated

to binary semaphore flags.  These flags allow either processor

on the left or right side of the Dual-Port RAM to claim a

privilege over the other processor for functions defined by the

system designer’s software.  As an example, the semaphore

can be used by one processor to inhibit the other from

accessing a portion of the Dual-Port RAM or any other shared

resource.

The Dual-Port RAM features a fast access time, and both

ports are completely independent of each other.  This means

that the activity on the left port in no way slows the access time

of the right port.  Both ports are identical in function to standard

CMOS Static RAM and can be read from, or written to, at the

same time with the only possible conflict arising from the

simultaneous writing of, or a simultaneous READ/WRITE of,

a non-semaphore location.  Semaphores are protected against

such ambiguous situations and may be used by the system

program to avoid any conflicts in the non-semaphore portion

of the Dual-Port RAM.  These devices have an automatic

power-down feature controlled by 

CE

, the Dual-Port RAM

enable, and 

SEM

, the semaphore enable.  The 

CE

 and 

SEM

pins control on-chip power down circuitry that permits the

respective port to go into standby mode when not selected.

This is the condition which is shown in Truth Table where 

CE

and 

SEM

 are both high.

Systems which can best use the IDT7005 contain multiple

processors or controllers and are typically very high-speed

systems which are software controlled or software intensive.

These systems can benefit from a performance increase

offered by the IDT7005's hardware semaphores, which pro-

vide a lockout mechanism without requiring complex pro-

gramming.

2738 drw 19

MASTER

Dual Port

RAM

BUSY

L

BUSY

R

CE

MASTER

Dual Port

RAM

BUSY

L

BUSY

R

CE

SLAVE

Dual Port

RAM

BUSY

L

BUSY

R

CE

SLAVE

Dual Port

RAM

BUSY

L

BUSY

R

CE

BUSY

L

BUSY

R

DECODER

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MILITARY AND COMMERCIAL TEMPERATURE RANGES

until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all

data bits so that a flag that is a one reads as a one in all data

bits and a flag containing a zero reads as all zeros.  The read

value is latched into one side’s output register when that side's

semaphore select (

SEM

) and output enable (

OE

) signals go

active.  This serves to disallow the semaphore from changing

state in the middle of a read cycle due to a write cycle from the

other side.  Because of this latch, a repeated read of a

semaphore in a test loop must cause either signal (

SEM

 or 

OE

)

to go inactive or the output will never change.

A sequence WRITE/READ must be used by the sema-

phore in order to guarantee that no system level contention

will occur.  A processor requests access to shared resources

by attempting to write a zero into a semaphore location.  If the

semaphore is already in use, the semaphore request latch will

contain a zero, yet the semaphore flag will appear as one, a

fact which the processor will verify by the subsequent read

(see Table III).  As an example, assume a processor writes a

zero to the left port at a free semaphore location. On a

subsequent read, the processor will verify that it has written

successfully to that location and will assume control over the

resource in question.  Meanwhile, if a processor on the right

side attempts to write a zero to the same semaphore flag it will

fail, as will be verified by the fact that a one will be read from

that semaphore on the right side during subsequent read.

Had a sequence of READ/WRITE been used instead, system

contention problems could have occurred during the gap

between the read and write cycles.

It is important to note that a failed semaphore request must

be followed by either repeated reads or by writing a one into

the same location.  The reason for this is easily understood by

looking at the simple logic diagram of the semaphore flag in

Figure 4. Two semaphore request latches feed into a sema-

phore flag.  Whichever latch is first to present a zero to the

semaphore flag will force its side of the semaphore flag low

and the other side high.  This condition will continue until a one

is written to the same semaphore request latch.  Should the

other side’s semaphore request latch have been written to a

zero in the meantime, the semaphore flag will flip over to the

other side as soon as a one is written into the first side’s

request latch.  The second side’s flag will now stay low until its

semaphore request latch is written to a one.  From this it is

easy to understand that, if a semaphore is requested and the

processor which requested it no longer needs the resource,

the entire system can hang up until a one is written into that

semaphore request latch.

The critical case of semaphore timing is when both sides

request a single token by attempting to write a zero into it at

the same time.  The semaphore logic is specially designed to

resolve this problem.  If simultaneous requests are made, the

logic guarantees that only one side receives the token.  If one

side is earlier than the other in making the request, the first

side to make the request will receive the token.  If both

requests arrive at the same time, the assignment will be

arbitrarily made to one port or the other.

One caution that should be noted when using semaphores

is that semaphores alone do not guarantee that access to a

Software handshaking between processors offers the

maximum in system flexibility by permitting shared resources

to be allocated in varying configurations. The IDT7005 does

not use its semaphore flags to control any resources through

hardware, thus allowing the system designer total flexibility in

system architecture.

An advantage of using semaphores rather than the more

common methods of hardware arbitration is that wait states

are never incurred in either processor.  This can prove to be

a major advantage in very high-speed systems.

HOW THE SEMAPHORE FLAGS WORK

The semaphore logic is a set of eight latches which are

independent of the Dual-Port RAM.  These latches can be

used to pass a flag, or token, from one port to the other to

indicate that a shared resource is in use.  The semaphores

provide a hardware assist for a use assignment method called

“Token Passing Allocation.”  In this method, the state of a

semaphore latch is used as a token indicating that shared

resource is in use.  If the left processor wants to use this

resource, it requests the token by setting the latch.  This

processor then verifies its success in setting the latch by

reading it.  If it was successful, it proceeds to assume control

over the shared resource.  If it was not successful in setting the

latch, it determines that the right side processor has set the

latch first,  has the token and is using the shared resource.  The

left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore

to  perform another task and occasionally attempt again to

gain control of the token via the set and test sequence.  Once

the right side has relinquished the token, the left side should

succeed in gaining control.

The semaphore flags are active low.  A token is requested

by writing a zero into a semaphore latch and is released when

the same side writes a one to that latch.

The eight semaphore flags reside within the IDT7005 in a

separate memory space from the Dual-Port RAM. This

address space is accessed by placing a low input on the 

SEM

pin (which acts as a chip select for the semaphore flags) and

using the other control pins (Address, 

OE

, and R/

W

) as they

would be used in accessing a standard static RAM.  Each of

the flags has a unique address which can be accessed by

either side through address pins A0 – A2.  When accessing the

semaphores, none of the other address pins has any effect.

When writing to a semaphore, only data pin D

0

 is used.  If

a low level is written into an unused semaphore location, that

flag will be set to a zero on that side and a one on the other side

(see Table III).  That semaphore can now only be modified by

the side showing the zero.  When a one is written into the same

location from the same side, the flag will be set to a one for both

sides (unless a semaphore request from the other side is

pending) and then can be written to by both sides.  The fact

that the side which is able to write a zero into a semaphore

subsequently locks out writes from the other side is what

makes semaphore flags useful in interprocessor communica-

tions.  (A thorough discussing on the use of this feature follows

shortly.)  A zero written into the same location from the other

side will be stored in the semaphore request latch for that side

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D

0

2738 drw 20

D

Q

WRITE

D

0

D

Q

WRITE

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

L PORT

R PORT

SEMAPHORE

READ

SEMAPHORE

READ

resource is secure.  As with any powerful programming

technique, if semaphores are misused or misinterpreted, a

software error can easily happen.

Initialization of the semaphores is not automatic and must

be handled via the initialization program at power-up.  Since

any semaphore request flag which contains a zero must be

reset to a one, all semaphores on both sides should have a

one written into them at initialization from both sides to assure

that they will be free when needed.

USING SEMAPHORES—SOME EXAMPLES

Perhaps the simplest application of semaphores is their

application as resource markers for the IDT7005’s Dual-Port

RAM.  Say the 8K x 8 RAM was to be divided into two 4K x 8

blocks which were to be dedicated at any one time to servicing

either the left or right port.  Semaphore 0 could be used to

indicate the side which would control the lower section of

memory, and Semaphore 1 could be defined as the indicator

for the upper section of memory.

To take a resource, in this example the lower 4K of

Dual-Port RAM, the processor on the left port could write and

then read a zero in to Semaphore 0.  If this task were

successfully completed (a zero was read back rather than a

one), the left processor would assume control of the lower 4K.

Meanwhile the right processor was attempting to gain control

of the  resource after the left processor, it would read back a

one in response to the zero it had attempted to write into

Semaphore 0.  At this point,  the software could choose to try

and gain control of the second 4K section by writing, then

reading a zero into Semaphore 1.  If it succeeded in gaining

control, it would lock out the left side.

Once the left side was finished with its task, it would write

a one to Semaphore 0 and may then try to gain access to

Semaphore 1.  If Semaphore 1 was still occupied by the right

side, the left side could undo its semaphore request and

perform other tasks until it was able to write, then read a zero

into Semaphore 1.  If the right processor performs a similar

task with Semaphore 0, this protocol would allow the two

processors to swap 4K blocks of Dual-Port RAM with each

other.

The blocks do not have to be any particular size and can

even be variable, depending upon the complexity of the

software using the semaphore flags.  All eight semaphores

could be used to divide the Dual-Port RAM or other shared

resources into eight parts.  Semaphores can even be as-

signed different meanings on different sides rather than being

given a common meaning as was shown in the example

above.

Semaphores are a useful form of arbitration in systems like

disk interfaces where the CPU must be locked out of a section

of memory during a transfer and the I/O device cannot tolerate

any wait states.  With the use of semaphores, once the two

devices has determined which memory area was “off-limits” to

the CPU, both the CPU and the I/O devices could access their

assigned portions of memory continuously without any wait

states.

Semaphores are also useful in applications where no

memory “WAIT” state is available on one or both sides.  Once

a semaphore handshake has been performed, both proces-

sors can access their assigned RAM segments at full speed.

Another application is in the area of complex data struc-

tures.  In this case, block arbitration is very important.  For this

application one processor may be responsible for building and

updating a data structure.  The other processor then reads

and interprets that data structure.  If the interpreting processor

reads an incomplete data structure, a major error condition

may exist.  Therefore, some sort of arbitration must be used

between the two different processors.  The building processor

arbitrates for the block, locks it and then is able to go in and

update the data structure.  When the update is completed, the

data structure block is released.  This allows the interpreting

processor to come back and read the complete data structure,

thereby guaranteeing a consistent data structure.

Figure 4.  IDT7005 Semaphore Logic

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MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION

2738 drw 21

A

Power

999

Speed

A

Package

A

Process/

Temperature

Range

Blank Commercial (0

°

C to +70

°

C)

B

Military (–55

°

C to +125

°

C)

Compliant to MIL-STD-883, Class B

PF

G

J

F

64-pin TQFP (PN64-1)

68-pin PGA (G68-1)

68-pin PLCC (J68-1)

68-pin Flatpack (F64-1)

15

17

20

25

35

55

70

Commercial Only

Commercial Only

Military Only

S

L

Standard Power

Low Power

XXXXX

Device

Type

64K (8K x 8) Dual-Port RAM

7005

IDT

Speed in nanoseconds