background image

Philips

Semiconductors

SA571

Compandor

Product specification

1997 Aug 14

INTEGRATED CIRCUITS

IC17 Data Handbook

background image

Philips Semiconductors

Product specification

SA571

Compandor

 2

1997 Aug 14

853-0812 18285

DESCRIPTION

The SA571 is a versatile low cost dual gain control circuit in which

either channel may be used as a dynamic range compressor or

expandor. Each channel has a full-wave rectifier to detect the

average value of the signal, a linerarized temperature-compensated

variable gain cell, and an operational amplifier.

The SA571 is well suited for use in cellular radio and radio

communications systems, modems, telephone, and satellite

broadcast/receive audio systems.

FEATURES

Complete compressor and expandor in one IChip

Temperature compensated

Greater than 110dB dynamic range

Operates down to 6VDC

System levels adjustable with external components

Distortion may be trimmed out

Dynamic noise reduction systems

Voltage-controlled amplifier

PIN CONFIGURATION

RECT CAP 1

RECT IN 1

AG CELL IN 1

GND

RECT CAP 2

AG CELL IN 2

RECT IN 2

V

CC

D, and N Packages

1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

15

INV. IN 1

RES. R

3

 1

OUTPUT 1

THD TRIM 1

INV. IN 2

RES. R

3

 2

OUTPUT 2

THD TRIM 2

TOP VIEW

NOTE:                                                          

1.  SOL - Released in Large SO Package Only.

SR00675

Figure 1.  Pin Configuration

APPLICATIONS

Cellular radio

High level limiter

Low level expandor—noise gate

Dynamic filters

CD Player

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

ORDER CODE

DWG #

16-Pin Plastic Small Outline Large (SOL)

-40 to +85

°

C

SA571D

SOT162-1

16-Pin Plastic Dual In-Line Package (DIP)

-40 to +85

°

C

SA571N

SOT38-4

BLOCK DIAGRAM

VARIABLE

GAIN

G IN

RECT IN

V

REF

THD TRIM

R2 20k

R1 10k

RECT CAP

R3

R3 20k

R4 30k

1.8V

INVERTER IN

OUTPUT

+

RECTIFIER

SR00676

Figure 2.  Block Diagram

background image

Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

 3

ABSOLUTE MAXIMUM RATINGS

SYMBOL

PARAMETER

RATING

UNITS

V

CC

Maximum operating voltage

571

18

VDC

T

A

Operating ambient temperature range

SA

-40 to +85

°

C

P

D

Power dissipation

400

mW

AC ELECTRICAL CHARACTERISTICS

V

CC

 = +6V,  T

A

 = 25

°

C; unless otherwise stated.

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

SA571

5

UNITS

MIN

TYP

MAX

V

CC

Supply voltage

6

18

V

I

CC

Supply current

No signal

3.2

4.8

mA

I

OUT

Output current capability

±

20

mA

SR

Output slew rate

±

.5

V/

µ

s

Gain cell distortion

2

Untrimmed

Trimmed

0.5

0.1

2.0

%

Resistor tolerance

±

5

±

15

%

Internal reference voltage

1.65

1.8

1.95

V

Output DC shift

3

Untrimmed

±

30

±

150

mV

Expandor output noise

No signal, 15Hz-20kHz

1

20

60

µ

V

Unity gain level

6

1kHz

-1.5

0

+1.5

dBm

Gain change

2, 4

±

0.1

dB

Reference drift

4

+2, -25

+20,  -50

mV

Resistor drift

4

+8, -0

%

Tracking error (measured relative to

value at unity gain) equals [V

O

 - V

O

(unity gain)] dB - V

2

dBm

Rectifier input,

V

2

 = +6dBm, V

1

 = 0dB

V

2

 = -30dBm, V

1

 = 0dB

+0.2

+0.2

-1, +1.5

dB

Channel separation

60

dB

NOTES:

1. Input to V

1

 and V

2

 grounded.

2. Measured at 0dBm, 1kHz.

3. Expandor AC input change from no signal to 0dBm.

4. Relative to value at T

A

 = 25

°

C.

5. Electrical characteristics for the SA571 only are specified over -40 to +85

°

C temperature range.

6. 0dBm = 775mV

RMS

.

background image

Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

 4

CIRCUIT DESCRIPTION

The SA571 compandor building blocks, as shown in the block

diagram, are a full-wave rectifier, a variable gain cell, an operational

amplifier and a bias system. The arrangement of these blocks in the

IC result in a circuit which can perform well with few external

components, yet can be adapted to many diverse applications.

The full-wave rectifier rectifies the input current which flows from the

rectifier input, to an internal summing node which is biased at V

REF

.

The rectified current is averaged on an external filter capacitor tied

to the C

RECT

 terminal, and the average value of the input current

controls the gain of the variable gain cell. The gain will thus be

proportional to the average value of the input signal for

capacitively-coupled voltage inputs as shown in the following

equation. Note that for capacitively-coupled inputs there is no offset

voltage capable of producing a gain error.  The only error will come

from the bias current of the rectifier (supplied internally) which is

less than 0.1

µ

A.

G

T

|V

IN

*

V

REF

| avg

R

1

or

G

T

| V

IN

| avg

R

1

The speed with which gain changes to follow changes in input signal

levels is determined by the rectifier filter capacitor. A small capacitor

will yield rapid response but will not fully filter low frequency signals.

Any ripple on the gain control signal will modulate the signal passing

through the variable gain cell. In an expander or compressor

application, this would lead to third harmonic distortion, so there is a

trade-off to be made between fast attack and decay times and

distortion. For step changes in amplitude, the change in gain with

time is shown by this equation.

G(t)

+

(G

initial

*

G

final

)

e

*

t

ńt

)

G

final

;

t +

10k x C

RECT

The variable gain cell is a current-in, current-out device with the ratio

I

OUT

/I

IN

 controlled by the rectifier. I

IN

 is the current which flows from

the 

G input to an internal summing node biased at V

REF

. The

following equation applies for capacitively-coupled inputs. The

output current, I

OUT

, is fed to the summing node of the op amp.

I

IN

+

V

IN

*

V

REF

R

2

+

V

IN

R

2

A compensation scheme built into the 

G cell compensates for

temperature and cancels out odd harmonic distortion. The only

distortion which remains is even harmonics, and they exist only

because of internal offset voltages. The THD trim terminal provides

a means for nulling the internal offsets for low distortion operation.

The operational amplifier (which is internally compensated) has the

non-inverting input tied to V

REF

, and the inverting input connected to

the 

G cell output as well as brought out externally. A resistor, R

3

, is

brought out from the summing node and allows compressor or

expander gain to be determined only by internal components.

The output stage is capable of 

±

20mA output current. This allows a

+13dBm (3.5V

RMS

) output into a 300

 load which, with a series

resistor and proper transformer, can result in +13dBm with a 600

output impedance.

A bandgap reference provides the reference voltage for all summing

nodes, a regulated supply voltage for the rectifier and 

G cell, and a

bias current for the 

G cell. The low tempco of this type of reference

provides very stable biasing over a wide temperature range.

The typical performance characteristics illustration shows the basic

input-output transfer curve for basic compressor or expander

circuits.

+20

+10

0

–10

–20

–30

–40

–50

–60

–70

–80

–40

–30

–20

–10

0

+10

COMPRESSOR OUTPUT LEVEL

OR

EXPANDOR INPUT LEVEL (dBm)

COMPRESSOR INPUT LEVEL

 OR 

EXP

ANDOR OUTPUT LEVEL

 (dBm)

SR00677

Figure 3.  Basic Input-Output Transfer Curve

TYPICAL TEST CIRCUIT

20k

10k

13

3.14

2.2

2.15

4

1.16

2.2

5.12

8.2k

8.9

200pF

30k

20k

7.10

6.11

V

1

V

2

V

O

V

CC

 = 15V

V

REF

G

10

µ

F

0.1

µ

F

2.2

µ

F

SR00678

Figure 4.  Typical Test Circuit

INTRODUCTION

Much interest has been expressed in high performance electronic

gain control circuits. For non-critical applications, an integrated

circuit operational transconductance amplifier can be used, but

when high-performance is required, one has to resort to complex

discrete circuitry with many expensive, well-matched components.

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Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

 5

This paper describes an inexpensive integrated circuit, the SA571

Compandor, which offers a pair of high performance gain control

circuits featuring low distortion (<0.1%), high signal-to-noise ratio

(90dB), and wide dynamic range (110dB).

CIRCUIT BACKGROUND

The SA571 Compandor was originally designed to satisfy the

requirements of the telephone system. When several telephone

channels are multiplexed onto a common line, the resulting

signal-to-noise ratio is poor and companding is used to allow a wider

dynamic range to be passed through the channel. Figure 5

graphically shows what a compandor can do for the signal-to-noise

ratio of a restricted dynamic range channel. The input level range of

+20 to -80dB is shown undergoing a 2-to-1 compression where a

2dB input level change is compressed into a 1dB output level

change by the compressor. The original 100dB of dynamic range is

thus compressed to a 50dB range for transmission through a

restricted dynamic range channel. A complementary expansion on

the receiving end restores the original signal levels and reduces the

channel noise by as much as 45dB.

The significant circuits in a compressor or expander are the rectifier

and the gain control element. The phone system requires a simple

full-wave averaging rectifier with good accuracy, since the rectifier

accuracy determines the (input) output level tracking accuracy. The

gain cell determines the distortion and noise characteristics, and the

phone system specifications here are very loose. These specs could

have been met with a simple operational transconductance

multiplier, or OTA, but the gain of an OTA is proportional to

temperature and this is very undesirable. Therefore, a linearized

transconductance multiplier was designed which is insensitive to

temperature and offers low noise and low distortion performance.

These features make the circuit useful in audio and data systems as

well as in telecommunications systems.

BASIC CIRCUIT HOOK-UP AND OPERATION

Figure 6 shows the block diagram of one half of the chip, (there are

two identical channels on the IC). The full-wave averaging rectifier

provides a gain control current, I

G

, for the variable gain (

G) cell.

The output of the 

G cell is a current which is fed to the summing

node of the operational amplifier. Resistors are provided to establish

circuit gain and set the output DC bias.

INPUT

LEVEL

COMPRESSION

EXP

ANSION

OUTPUT

LEVEL

NOISE

+20

0dB

–40

–80

–20

0dB

–40

–80

SR00679

Figure 5.  Restricted Dynamic Range Channel

The circuit is intended for use in single power supply systems, so

the internal summing nodes must be biased at some voltage above

ground. An internal band gap voltage reference provides a very

stable, low noise 1.8V reference denoted V

REF

. The non-inverting

input of the op amp is tied to V

REF

, and the summing nodes of the

rectifier and 

G cell (located at the right of R

1

 and R

2

) have the

same potential. The THD trim pin is also at the V

REF

 potential.

Figure 7 shows how the circuit is hooked up to realize an expandor.

The input signal, V

IN

, is applied to the inputs of both the rectifier and

the 

G cell. When the input signal drops by 6dB, the gain control

current will drop by a factor of 2, and so the gain will drop 6dB. The

output level at V

OUT

 will thus drop 12dB, giving us the desired 2-to-1

expansion.

Figure 8 shows the hook-up for a compressor. This is essentially an

expandor placed in the feedback loop of the op amp. The 

G cell is

setup to provide AC feedback only, so a separate DC feedback loop

is provided by the two R

DC

 and C

DC

. The values of R

DC

 will

determine the DC bias at the output of the op amp. The output will

bias to:

V

OUT

DC

+

1

)

R

DC1

)

R

DC2

R

4

V

CC

 PIN 13

GND PIN 4

OUTPUT

7,10

V

REF

1.8V

R

4

30k

1,16

C

RECT

R

1

10k

2,15

RECT

IN

G

IN

3,14

20k

R

2

20k

R

3

6,11

5,12

INV

IN

R

3

THD TRIM

8,9

IG

G

SR00680

Figure 6.  Chip Block Diagram (1 of 2 Channels)

V

IN

V

OUT

V

REF

G

*C

IN1

*C

IN2

*C

RECT

+

R

3

R

4

R

1

R

2

GAIN

+

2 R

3

V

IN

(avg)

R

1

R

2

I

B

NOTE:

I

B

 = 140

µ

A

*EXTERNAL COMPONENTS

SR00681

Figure 7.  Basic Expander

V

REF

+

ǒ

1

)

R

DCTOT

30k

Ǔ

1.8V

The output of the expander will bias up to:

V

OUT

DC

+

1

)

R

3

R

4

V

REF

V

REF

+

ǒ

1

)

20k

30k

Ǔ

1.8V

+

3.0V

The output will bias to 3.0V when the internal resistors are used.

External resistors may be placed in series with R

3

, (which will affect

the gain), or in parallel with R

4

 to raise the DC bias to any desired

value.

background image

Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

 6

NOTES:

GAIN

+

ǒ

R

1

R

2

IB

2R3 VINavg

Ǔ

1

2

I

B

 = 140

µ

A

External components

V

IN

C

IN

C

F

R

1

R

2

R

3

V

OUT

G

*

C

RECT

*

R

DC

*

R

DC

*

C

DC

*

V

REF

R

4

SR00682

Figure 8.  Basic Compressor

10k

C

R

I

G

R

S

R

1

V

IN

V+

I = V

IN

 / R

1

SR00684

Figure 9.  Rectifier Concept

CIRCUIT DETAILS—RECTIFIER

Figure 9 shows the concept behind the full-wave averaging rectifier.

The input current to the summing node of the op amp, V

IN

R

1

, is

supplied by the output of the op amp. If we can mirror the op amp

output current into a unipolar current, we will have an ideal rectifier.

The output current is averaged by R

5

, CR, which set the averaging

time constant, and then mirrored with a gain of 2 to become I

G

, the

gain control current.

Figure 10 shows the rectifier circuit in more detail. The op amp is a

one-stage op amp, biased so that only one output device is on at a

time. The non-inverting input, (the base of Q

1

), which is shown

grounded, is actually tied to the internal 1.8V V

REF

. The inverting

input is tied to the op amp output, (the emitters of Q

5

 and Q

6

), and

the input summing resistor R

1

. The single diode between the bases

of Q

5

 and Q

6

 assures that only one device is on at a time. To detect

the output current of the op amp, we simply use the collector

currents of the output devices Q

5

 and Q

6

. Q

6

 will conduct when the

input swings positive and Q

5

 conducts when the input swings

negative. The collector currents will be in error by the 

a of Q

5

 or Q

6

on negative or positive signal swings, respectively. ICs such as this

have typical NPN 

β

s of 200 and PNP 

β

s of 40. The 

a’s of 0.995 and

0.975 will produce errors of 0.5% on negative swings and 2.5% on

positive swings. The 1.5% average of these errors yields a mere

0.13dB gain error.

At very low input signal levels the bias current of Q

2

, (typically

50nA), will become significant as it must be supplied by Q

5

. Another

low level error can be caused by DC coupling into the rectifier. If an

offset voltage exists between the V

IN

 input pin and the base of Q

2

,

an error current of V

OS

/R

1

 will be generated. A mere 1mV of offset

will cause an input current of 100nA which will produce twice the

error of the input bias current. For highest accuracy, the rectifier

should be coupled into capacitively. At high input levels the 

β

 of the

PNP Q

6

 will begin to suffer, and there will be an increasing error until

the circuit saturates. Saturation can be avoided by limiting the

current into the rectifier input to 250

µ

A. If necessary, an external

resistor may be placed in series with R

1

 to limit the current to this

value. Figure 11 shows the rectifier accuracy vs input level at a

frequency of 1kHz.

V+

10k

10k

Q

1

Q

2

Q

3

Q

4

Q

7

Q

5

Q

6

Q

8

Q

9

C

R

R

S

R

1

D

1

I

1

I

2

V

IN

V–

I

G +

2

VIN avg

R 1

NOTE:

SR00683

Figure 10.  Simplified Rectifier Schematic

At very high frequencies, the response of the rectifier will fall off. The

roll-off will be more pronounced at lower input levels due to the

increasing amount of gain required to switch between Q

5

 or Q

6

conducting. The rectifier frequency response for input levels of

0dBm, -20dBm, and -40dBm is shown in Figure 12. The response at

all three levels is flat to well above the audio range.

ERROR GAIN dB

+1

0

–1

–40

–20

0

RECTIFIER INPUT dBm

SR00685

Figure 11.  Rectifier Accuracy

background image

Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

 7

0

3

10k

1MEG

INPUT = 0dBm

–20dBm

–40dBm

FREQUENCY (Hz)

GAIN ERROR (dB)

SR00686

Figure 12.  Rectifier Frequency Response vs Input Level

VARIABLE GAIN CELL

Figure 13 is a diagram of the variable gain cell. This is a linearized

two-quadrant transconductance multiplier. Q

1

, Q

2

 and the op amp

provide a predistorted drive signal for the gain control pair, Q

3

 and

Q

4

. The gain is controlled by I

G

 and a current mirror provides the

output current.

The op amp maintains the base and collector of Q

1

 at ground

potential (V

REF

) by controlling the base of Q

2

. The input current I

IN

(=V

IN

/R

2

) is thus forced to flow through Q

1

 along with the current I

1

,

so I

C1

=I

1

+I

IN

. Since I

2

 has been set at twice the value of I

1

, the

current through Q

2

 is:

I

2

-(I

1

+I

IN

)=I

1

-I

IN

=I

C2

.

The op amp has thus forced a linear current swing between Q

1

 and

Q

2

 by providing the proper drive to the base of Q

2

. This drive signal

will be linear for small signals, but very non-linear for large signals,

since it is compensating for the non-linearity of the differential pair,

Q

1

 and Q

2

, under large signal conditions.

Q

1

Q

2

Q

3

Q

4

I

OUT

+

I

G

I

1

I

IN

+

I

G

V

IN

I

2

R

2

NOTE:

I

2

 (= 2I

1

)

280

µ

A

I

G

I

IN

V

IN

R

2

20k

I

1

140

µ

A

V+

V–

SR00687

Figure 13.  Simplified 

G Cell Schematic

The key to the circuit is that this same predistorted drive signal is

applied to the gain control pair, Q

3

 and Q

4

. When two differential

pairs of transistors have the same signal applied, their collector

current ratios will be identical regardless of the magnitude of the

currents. This gives us:

I

C1

I

C2

+

I

C4

I

C3

+

I

1

)

I

IN

I

1

*

I

IN

plus the relationships I

G

=I

C3

+I

C4

 and I

OUT

=I

C4

-I

C3

 will yield the

multiplier transfer function,

I

OUT

+

I

G

I

1

I

IN

+

V

IN

R

2

I

G

I

1

This equation is linear and temperature-insensitive, but it assumes

ideal transistors.

4

3

2

1

.34

–6

0

+6

4mV

3mV

2mV

1mV

INPUT LEVEL (dBm)

% THD

V

OS

 = 5mV

SR00688

Figure 14.  

G Cell Distortion vs Offset Voltage

If the transistors are not perfectly matched, a parabolic, non-linearity

is generated, which results in second harmonic distortion. Figure 14

gives an indication of the magnitude of the distortion caused by a

given input level and offset voltage. The distortion is linearly

proportional to the magnitude of the offset and the input level.

Saturation of the gain cell occurs at a +8dBm level. At a nominal

operating level of 0dBm, a 1mV offset will yield 0.34% of second

harmonic distortion. Most circuits are somewhat better than this,

which means our overall offsets are typically about mV. The

distortion is not affected by the magnitude of the gain control

current, and it does not increase as the gain is changed. This

second harmonic distortion could be eliminated by making perfect

transistors, but since that would be difficult, we have had to resort to

other methods. A trim pin has been provided to allow trimming of the

internal offsets to zero, which effectively eliminated

second harmonic distortion. Figure 15 shows the simple trim

network required.

Figure 16 shows the noise performance of the 

G cell. The

maximum output level before clipping occurs in the gain cell is

plotted along with the output noise in a 20kHz bandwidth. Note that

the noise drops as the gain is reduced for the first 20dB of gain

reduction. At high gains, the signal to noise ratio is 90dB, and the

total dynamic range from maximum signal to minimum noise is

110dB.

3.6V

V

CC

R

20k

6.2k

To THD Trim

200pF

SR00689

Figure 15.   THD Trim Network

background image

Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

 8

VCA GAIN (0dB)

+20

OUTPUT (dBm)

0

–20

–40

–60

–80

–100

–40

–20

0

MAXIMUM

SIGNAL LEVEL

NOISE IN

20kHz BW

90dB

110dB

SR00690

Figure 16.  Dynamic Range

Control signal feedthrough is generated in the gain cell by imperfect

device matching and mismatches in the current sources, I

1

 and I

2

.

When no input signal is present, changing I

G

 will cause a small

output signal. The distortion trim is effective in nulling out any control

signal feedthrough, but in general, the null for minimum feedthrough

will be different than the null in distortion. The control signal

feedthrough can be trimmed independently of distortion by tying a

current source to the 

G input pin. This effectively trims I

1

. Figure 17

shows such a trim network.

R-SELECT FOR

3.6V

470k

TO PIN 3 OR 14

100k

V

CC

SR00691

Figure 17.  Control Signal Feedthrough

OPERATIONAL AMPLIFIER

The main op amp shown in the chip block diagram is equivalent to a

741 with a 1MHz bandwidth. Figure 18 shows the basic circuit. Split

collectors are used in the input pair to reduce g

M

, so that a small

compensation capacitor of just 10pF may be used. The output

stage, although capable of output currents in excess of 20mA, is

biased for a low quiescent current to conserve power. When driving

heavy loads, this leads to a small amount of crossover distortion.

Q

1

Q

2

Q

4

Q

3

I

1

I

2

Q

6

D

1

D

2

Q

2

C

C

+IN

–IN

OUT

SR00692

Figure 18.  Operational Amplifier

RESISTORS

Inspection of the gain equations in Figures 7 and 8 will show that the

basic compressor and expander circuit gains may be set entirely by

resistor ratios and the internal voltage reference. Thus, any form of

resistors that match well would suffice for these simple hook-ups,

and absolute accuracy and temperature coefficient would be of no

importance. However, as one starts to modify the gain equation with

external resistors, the internal resistor accuracy and tempco become

very significant.  Figure 19 shows the effects of temperature on the

diffused resistors which are normally used in integrated circuits, and

the ion-implanted resistors which are used in this circuit. Over the

critical 0

°

C to +70

°

C  temperature range, there is a 10-to-1 improve-

ment in drift from a 5% change for the diffused resistors, to a 0.5%

change for the implemented resistors. The implanted resistors have

another advantage in that they can be made  the size of the diffused

resistors due to the higher resistivity. This saves a significant

amount of chip area.

ÇÇÇÇÇÇ

ÇÇÇÇÇÇ

1% ERROR

NORMALIZED RESIST

ANCE

TEMPERATURE

1.15

1.10

1.05

1.00

.95

–40

0

40

80

120

LOW TC

IMPLANTED

RESISTOR

BAND

1k

 /

140

 /

DIFFUSED

RESISTOR

SR00693

Figure 19.  Resistance vs Temperature

background image

Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

9

SO16:

plastic small outline package; 16 leads; body width 7.5 mm

SOT162-1

background image

Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

10

DIP16:

plastic dual in-line package; 16 leads (300 mil)

SOT38-4

background image

Philips Semiconductors

Product specification

SA571

Compandor

1997 Aug 14

11

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,

including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance.  Philips

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only.  Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing

or modification.

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This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips

Semiconductors reserves the right to make changes at any time without notice in order to improve design

and supply the best possible product.

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DEFINITIONS

Data Sheet Identification

Product Status

Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development.  Specifications

may change in any manner without notice.

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at any time without notice, in order to improve design and supply the best possible product.

©

 Copyright Philips Electronics North America Corporation 1997

All rights reserved. Printed in U.S.A.

Philips

Semiconductors