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ML4851

*

Low Current, Voltage Boost Regulator

BLOCK DIAGRAM

1

GENERAL DESCRIPTION

The ML4851 is a low power boost regulator designed for

DC to DC conversion in 1 to 3 cell battery powered

systems. The maximum switching frequency can exceed

100kHz, allowing the use of small, low cost inductors.

The combination of BiCMOS process technology, internal

synchronous rectification, variable frequency operation,

and low supply current make the ML4851 ideal for 1 cell

applications. The ML4851 is capable of start-up with input

voltages as low as 1V and is available in 5V and 3.3V

output versions with output voltage accuracy of ±3%.

An integrated synchronous rectifier eliminates the need

for an external Schottky diode and provides a lower

forward voltage drop, resulting in higher conversion

efficiency. In addition, low quiescent battery current and

variable frequency operation result in high efficiency

even at light loads. The ML4851 requires only one

inductor and two capacitors to build a very small

regulator circuit capable of achieving conversion

efficiencies in excess of 90%.

The circuit also contains a RESET output which goes low

when the IC can no longer function due to low input

voltage, or when the DETECT input drops below 200mV.

             

                                             *Some Packages Are Obsolete

FEATURES

n

Guaranteed full load start-up and operation at 1V input

n

Maximum switching frequency > 100kHz

n

Pulse Frequency Modulation (PFM) and internal

synchronous rectification for high efficiency

n

Minimum external components

n

Low ON resistance internal switching FETs

n

Micropower operation

n

5V and 3.3V output versions

FEATURING

Extended Commercial Temperature Range

-20˚C to 70˚C

for Portable Handheld Equipment

VREF

VOUT

VL

5

VIN

1

DETECT

4

PWR

GND

8

VREF

6

RESET

VREF

+

+

S

R

Q

Q

5µs

ONE SHOT

START-UP

REFERENCE

2

GND

3

VREF

+

COMP

7

July, 2000

DATASHEET

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2

ML4851

July, 2000

DATASHEET

PIN CONFIGURATION

PIN

NAME

FUNCTION

1

V

IN

Battery input voltage

2

V

REF

200mV reference output

3

GND

Analog signal ground

4

DETECT

Pulling this pin below V

REF

 causes the

RESET pin to go low

PIN

NAME

FUNCTION

5

V

OUT

Boost regulator output

6

V

L

Boost inductor connection

7

RESET

Output goes low when regulation

cannot be achieved, or when DETECT

goes below V

REF

8

PWR GND

Return for the NMOS output transistor

PIN DESCRIPTION

ML4851

8-Pin SOIC (S08)

  

1

2

3

4

8

7

6

5

VIN

VREF

GND

DETECT

PWR GND

RESET

VL

VOUT

  

TOP VIEW

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3

ML4851

July 2000

DATASHEET

OPERATING CONDITIONS

Temperature Range

ML4851CS-X .............................................. 0ºC to 70ºC

ML4851ES-X ........................................... –20ºC to 70ºC

V

IN 

Operating Range

ML4851CS-X ................................ 1.0V to V

OUT

 – 0.2V

ML4851ES-X ................................ 1.1V to V

OUT

 – 0.2V

Thermal Resistance (

q

JA

) .................................... 160ºC/W

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are those values beyond which

the device could be permanently damaged. Absolute

maximum ratings are stress ratings only and functional

device operation is not implied.

V

OUT

.......................................................................... 7V

Voltage on any other pin ..... GND – 0.3V to V

OUT

 + 0.3V

Peak Switch Current, I

(PEAK) ...................................................

1A

Average Switch Current, I

(AVG) .....................................

250mA

Junction Temperature .............................................. 150ºC

Storage Temperature  Range ...................... –65ºC to 150ºC

Lead Temperature (Soldering 10 sec.) ..................... 260ºC

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, V

IN 

= Operating Voltage Range, T

A

 = Operating Temperature Range (Note 1)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SUPPLY

I

IN

V

IN

 Current

V

IN

 = V

OUT 

– 0.2V

50

60

µA

I

OUT(Q)

V

OUT

 Quiescent Current

8

10

µA

I

L

V

L

 Quiescent Current

1

µA

REFERENCE

V

REF

Output Voltage

0 < I

REF

 < –5µA

190

200

210

mV

PFM REGULATOR

t

ON

Pulse Width

4.5

5

5.5

µs

OUTPUT VOLTAGE

V

OUT

Output Voltage

-3 Suffix

3.2

3.3

3.4

V

t

ON

 = 0 at V

OUT(MAX)

,

4.5µs 

£ t

ON

 

£ 5.5µs

-5 Suffix

4.85

5.0

5.15

V

at V

OUT(MIN)

Load Regulation

See Figure 1, -3 Suffix

3.2

3.3

3.4

V

V

IN

 = 1.2V, I

OUT

 

£ 10mA

See Figure 1, -3 Suffix

3.2

3.3

3.4

V

V

IN

 = 2.4V, I

OUT

 

£ 65mA

See Figure 1, -5 Suffix

4.85

5.0

5.15

V

V

IN

 = 1.2V, I

OUT

 

£ 18mA

See Figure 1, -5 Suffix

4.85

5.0

5.15

V

V

IN

 = 2.4V, I

OUT

 

£ 85mA

Undervoltage Lockout Threshold

0.85

0.95

V

RESET COMPARATOR

DETECT Threshold

194

200

206

mV

DETECT Bias Current

–100

100

nA

RESET Output High Voltage

I

OH

 = 100µA

V

OUT 

– 0.2

V

RESET Output Low Voltage

I

OL

 = -100µA

0.2

V

Note 1: Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.

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4

ML4851

July, 2000

DATASHEET

VREF

VOUT

VOUT

+

VL

VIN

L1

Q1

Q2

5

6

+

+

S

R

Q

Q

5µs

ONE SHOT

START-UP

A2

A1

R1

R2

C1

Figure 1.  Application Test Circuit

Figure 2.  PFM Regulator Block Diagram

Figure 3.  PFM Inductor Current Waveforms and Timing

ML4851

I

OUT

100

µ

F

1

µ

F

100

µ

F

V

IN

27

µ

H

(Sumida CD75)

V

OUT

V

IN

V

REF

GND

DETECT

PWR GND

RESET

V

L

V

OUT

R

A

R

B

Q(ONE SHOT)

Q1 ON

Q1 ON

Q2

ON

Q2

ON

INDUCTOR

CURRENT

Q1 & Q2 OFF

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5

ML4851

July 2000

DATASHEET

FUNCTIONAL DESCRIPTION

The ML4851 combines Pulse Frequency Modulation (PFM)

and synchronous rectification to create a boost converter

that is both highly efficient and simple to use. A PFM

regulator charges a single inductor for a fixed period of

time and then completely discharges before another cycle

begins, simplifying the design by eliminating the need for

conventional current limiting circuitry. Synchronous

rectification is accomplished by replacing an external

Schottky diode with an on-chip PMOS device, reducing

switching losses and external component count.

REGULATOR OPERATION

A block diagram of the boost converter is shown in Figure

2. The circuit remains idle when V

OUT

 is at or above the

desired output voltage, drawing 50µA from V

IN

, and 8µA

from V

OUT

 through the feedback resistors R1 and R2.

When V

OUT

 drops below the desired output level, the

output of amplifier A1 goes high, signaling the regulator

to deliver charge to the output. Since the output of

amplifier A2 is normally high, the flip-flop captures the

A1 set signal and creates a pulse at the gate of the NMOS

transistor Q1. The NMOS transistor will charge the

inductor L1 for 5µs, resulting in a peak current given by:

(1)

For reliable operation, L1 should be chosen so that I

L(PEAK)

does not exceed 1A.

When the one-shot times out, the NMOS transistor

releases the V

L

 pin, allowing the inductor to fly-back and

momentarily charge the output through the body diode of

PMOS transistor Q2. But, as the voltage across the PMOS

transistor changes polarity, its gate will be driven low by

the current sense amplifier A2, causing Q2 to short out its

body diode. The inductor then discharges into the load

through Q2. The output of A2 also serves to reset the flip-

flop and one-shot in preparation for the next charging

cycle. A2 releases the gate of Q2 when its current falls to

zero. If V

OUT

 is still low, the flip-flop will immediately

initiate another pulse. The output capacitor (C1) filters the

inductor current, limiting output voltage ripple. Inductor

current and one-shot waveforms are shown in Figure 3.

RESET COMPARATOR

An additional comparator is provided to detect low V

IN

,

or any other error condition that is important to the user.

The inverting input of the comparator is internally

connected to V

REF

, while the non-inverting input is

provided externally at the DETECT pin. The output of the

comparator is the RESET pin, which swings from V

OUT

 to

GND when an error is detected. (Refer to Block Diagram)

DESIGN CONSIDERATIONS

INDUCTOR

Selecting the proper inductor for a specific application

usually involves a trade-off between efficiency and

maximum output current. Choosing too high a value will

keep the regulator from delivering the required output

current under worst case conditions. Choosing too low a

value causes efficiency to suffer. It is necessary to know

the maximum required output current and the input

voltage range to select the proper inductor value. The

maximum inductor value can be estimated using the

following formula:

(2)

where 

h is the efficiency, typically between 0.8 and 0.9.

Note that this is the value of inductance that just barely

delivers the required output current under worst case

conditions. A lower value may be required to cover

inductor tolerance, the effect of lower peak inductor

currents caused by resistive losses, and minimum dead

time between pulses.

Another method of determining the appropriate inductor

value is to make an estimate based on the typical

performance curves given in Figures 4 and 5. Figure 4

shows maximum output current as a function of input

voltage for several inductor values. These are typical

performance curves and leave no margin for inductance

and ON-time variations. To accommodate worst case

conditions, it is necessary to derate these curves by at

least 10% in addition to inductor tolerance.

For example, a two cell to 5V application requires 60mA

of output current while using an inductor with 15%

tolerance. The output current should be derated by 25% to

80mA to cover the combined inductor and ON-time

tolerances. Assuming that 2V is the end of life voltage of

a two cell input, Figure 4 shows that with a 2V input, the

ML4851-5 delivers 80mA with an 18µH inductor.

Figure 5 shows efficiency under the conditions used to

create Figure 4. It can be seen that efficiency is mostly

independent of input voltage and is closely related to

inductor value. This illustrates the need to keep the

inductor value as high as possible to attain peak system

efficiency. As the inductor value goes down to 10µH, the

efficiency drops to around 75%. With 33µH, the

efficiency exceeds 90% and there is little room for

improvement.  At values greater than 33µH, the operation

of the synchronous rectifier becomes unreliable at low

input voltages because the inductor current is so small

that it is difficult for the control circuitry to detect. The

data used to generate Figures 4 and 5 is provided in Table

1.

I

t

V

L

s V

L

L PEAK

ON

IN

IN

(

)

=

×

=

×

1

5

1

µ

L

V

t

V

I

MAX

IN MIN

ON MIN

OUT

OUT MAX

=

×

×

×

×

(

)

(

)

(

)

2

2

η

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6

ML4851

July, 2000

DATASHEET

Figure 4. Output Current vs. Input Voltage

Figure 5. Typical Efficiency as a Function of V

IN

250

200

150

100

50

0

I OUT MAX 

(mA)

VIN (V)

1.0

1.5

2.0

3.0

2.5

L = 10µH

ML4851-3

L = 18µH

L = 33µH

L = 56µH

250

200

150

100

50

0

I OUT MAX

 (mA)

VIN (V)

1.0

2.0

4.5

3.5

1.5

2.5

4.0

3.0

ML4851-5

L = 10µH

L = 18µH

L = 33µH

L = 56µH

95

90

85

80

75

70

EFFICIENCY at I

OUT

 MAX (%)

VIN (V)

1.0

1.5

2.0

3.0

2.5

ML4851-3

L = 10µH

L = 18µH

L = 33µH

L = 56µH

95

90

85

80

75

70

EFFICIENCY at I

OUT

 MAX (%)

VIN (V)

1.0

1.5

2.0

3.0

2.5

ML4851-3

L = 10µH

L = 18µH

L = 33µH

L = 56µH

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7

ML4851

July 2000

DATASHEET

After the appropriate inductor value is chosen, it is

necessary to find the minimum inductor current rating

required. Peak inductor current is determined from the

following formula:

(3)

In the two cell application previously described, a

maximum input voltage of 3V would give a peak current

of 1A. When comparing various inductors, it is important

to keep in mind that suppliers use different criteria to

determine their ratings. Many use a conservative current

level, where inductance has dropped to 90% of its normal

level. In any case, it is a good idea to try inductors of

various current ratings with the ML4851 to determine

which inductor is the best choice. Check efficiency and

maximum output current, and if a current probe is

available, look at the inductor current to see if it looks

like the waveform shown in Figure 3. For additional

information, see Applications Note 29, “Choosing an

Inductor for Your ML4861 Application.”

Suitable inductors can be purchased from the following

suppliers:

Coilcraft

(847) 639-6400

Coiltronics

(561) 241-7876

Dale

(605) 665-9301

Sumida

(847) 956-0666

XFMRS, Inc. (317) 834-1066

OUTPUT CAPACITOR

The choice of output capacitor is also important, as it

controls the output ripple and optimizes the efficiency of

the circuit. Output ripple is influenced by three capacitor

parameters: capacitance, ESR, and ESL. The contribution

due to capacitance can be determined by looking at the

change in capacitor voltage required to store the energy

delivered by the inductor in a single charge-discharge

cycle, as determined by the following formula:

(4)

For a 2.4V input, and 5V output, a 18µH inductor, and a

47µF capacitor, the expected output ripple due to

capacitor value is 33mV.

Capacitor Equivalent Series Resistance (ESR) and

Equivalent Series Inductance (ESL), also contribute to the

output ripple due to the inductor discharge current

waveform. Just after the NMOS transistor turns off, the

output current ramps quickly to match the peak inductor

current. This fast change in current through the output

capacitor’s ESL causes a high frequency (5ns) spike that

can be over 1V in magnitude. After the ESL spike settles,

the output voltage still has a ripple component equal to

the inductor discharge current times the ESR. This

component will have a sawtooth shape and a peak value

equal to the peak inductor current times the ESR. ESR

also has a negative effect on efficiency by contributing

I

2

R losses during the discharge cycle.

An output capacitor with a capacitance of 100µF, an ESR

of less than 0.1

W, and an ESL of less than 5nH is a good

general purpose choice. Tantalum capacitors which meet

these requirements can be obtained from the following

suppliers:

Matsuo

(207) 282-5111

Sprague

(207) 324-4140

If ESL spikes are causing output noise problems, an EMI

filter can be added in series with the output.

INPUT CAPACITOR

Unless the input source is a very low impedance battery,

it will be necessary to decouple the input with a

capacitor with a value of between 47µF and 100µF. This

provides the benefits of preventing input ripple from

affecting the ML4851 control circuitry, and it also

improves efficiency by reducing I

2

R losses during the

charge and discharge cycles of the inductor. Again, a low

ESR capacitor (such as tantalum) is recommended.

REFERENCE CAPACITOR

Under some circumstances input ripple cannot be reduced

effectively. This occurs primarily in applications where

inductor currents are high, causing excess output ripple

due to “pulse grouping”, where the charge-discharge

pulses are not evenly spaced in time. In such cases it may

be necessary to decouple the reference pin (V

REF

) with a

small 10nF to 100nF ceramic capacitor. This is

particularly true if the ripple voltage at V

IN

 is greater than

100mV.

SETTING THE 

RESET THRESHOLD

To use the RESET comparator as an input voltage monitor,

as shown in Figure 1,  it is necessary to use an external

resistor divider tied to the DETECT pin as shown in the

block diagram. The resistor values R

A

 and R

B

 can be

calculated using the following equation:

(5)

The value of R

B

 should be 100k

W or less to minimize bias

current errors. R

A

 is then found by rearranging the

equation:

DESIGN CONSIDERATIONS

 (Continued)

V

R

IN MIN

B

(

)

A

B

.

R

R

=

×

+

0 2

1

6

V

t

V

L C

V

V

OUT

ON

IN

OUT

IN

=

×

× × ×

2

2

2

1

6

I

t

V

L

L PEAK

ON MAX

IN MAX

MIN

(

)

(

)

(

)

=

×

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8

ML4851

July, 2000

DATASHEET

TOP LAYER

BOTTOM LAYER

ML4851-3

ML4851-5

DESIGN CONSIDERATIONS

 (Continued)

Figure 6.  Sample PC Board Layout

Table 1.  Maximum Output Current and Efficiency vs. V

IN

V

IN

I

OUT

 (mA)

EFFICIENCY PERCENTAGE

L = 10µH

1.0

24.2

78.3

1.5

68.0

79.9

2.0

123.1

80.3

L = 18µH

1.0

15.7

82.3

1.5

43.3

84.8

2.0

80.4

85.7

2.5

125.3

86.2

3.0

169.9

86.5

3.5

236.9

87.0

L = 33µH

1.0

9.1

83.5

1.5

24.8

87.0

2.0

47.4

88.6

2.5

74.5

89.5

3.0

106.9

90.3

3.5

147.5

90.8

4.0

190.0

91.4

4.5

227.8

92.1

L = 56µH

1.0

5.5

80.1

1.5

13.9

85.9

2.0

28.5

88.9

2.5

45.7

90.3

3.0

67.1

91.4

3.5

92.5

92.3

4.0

122.1

92.6

4.5

149.6

93.8

V

IN

I

OUT

 (mA)

EFFICIENCY PERCENTAGE

L = 10µH

1.0

45.8

77.6

1.5

108.3

77.7

2.0

184.1

77.9

L = 18µH

1.0

30.1

82.5

1.5

70.9

83.5

2.0

125.5

83.9

2.5

185.7

84.5

3.0

243.4

85.4

L = 33µH

1.0

17.6

86.0

1.5

42.7

87.8

2.0

76.1

88.7

2.5

120.4

89.7

3.0

159.6

90.7

L = 56µH

1.0

10.6

85.2

1.5

25.9

89.1

2.0

47.6

90.8

2.5

75.8

92.0

3.0

108.0

93.1

R

R

V

A

B

IN MIN

=

×





(

)

.

0 2

1

(6)

LAYOUT

Good PC board layout practices will ensure the proper

operation of the ML4851. Important layout considerations

include:

n

Use adequate ground and power traces or planes

n

Keep components as close as possible to the ML4851

n

Use short trace lengths from the inductor to the V

L

 pin

and from the output capacitor to the V

OUT

 pin

n

Use a single point ground for the ML4851 PWR GND

pin and the input and output capacitors, and connect

GND to PWR GND with a separate trace

A sample PC board layout is shown in Figure 6.

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9

ML4851

July 2000

DATASHEET

PHYSICAL DIMENSIONS

 inches (millimeters)

SEATING PLANE

0.148 - 0.158

(3.76 - 4.01)

PIN 1 ID

0.228 - 0.244

(5.79 - 6.20)

0.189 - 0.199

(4.80 - 5.06)

0.012 - 0.020

(0.30 - 0.51)

0.050 BSC

(1.27 BSC)

0.015 - 0.035

(0.38 - 0.89)

0.059 - 0.069

(1.49 - 1.75)

0.004 - 0.010

(0.10 - 0.26)

0.055 - 0.061

(1.40 - 1.55)

8

0.006 - 0.010

(0.15 - 0.26)

0º - 8º

1

0.017 - 0.027

(0.43 - 0.69)

(4 PLACES)

Package: S08

8-Pin SOIC

ORDERING INFORMATION

PART NUMBER

OUTPUT VOLTAGE

TEMPERATURE RANGE

PACKAGE

ML4851CS-3

3.3V

0ºC to 70ºC

8-Pin SOIC (S08)

ML4851CS-5

5.0V

0ºC to 70ºC

8-Pin SOIC (S08)

ML4851ES-3

3.3V

–20ºC to 70ºC

8-Pin SOIC (S08)

ML4851ES-5

5.0V

–20ºC to 70ºC

8-Pin SOIC (S08)

ML4851IS-3  (obsolete)

3.3V

–40ºC to 85ºC

8-Pin SOIC (S08)

ML4851IS-5  (obsolete)

5.0V

–40ºC to 85ºC

8-Pin SOIC (S08)

Micro Linear Corporation

2092 Concourse Drive

San Jose, CA 95131

Tel: 408/433-5200

Fax: 408/432-0295

www.microlinear.com

© Micro Linear 1997.  is a registered trademark of Micro Linear Corporation.  All other trademarks are the property of their respective owners.

Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502;

5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167. Japan: 2,598,946;

2,619,299; 2,704,176.  Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability

arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits

contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits

infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult

with appropriate legal counsel before deciding on a particular application.

DS4851-03