background image

Semiconductor Group

1

1998-08-01

3.3 V  8M

×

 64/72-Bit 1 Bank SDRAM Module

3.3 V  16M

×

 64/72-Bit 2 Bank SDRAM Module

168 pin unbuffered DIMM Modules

HYS 64/72V8200GU

HYS 64/72V16220GU

168 Pin PC100-compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules

 for PC main memory applications

1 bank 8M

×

 64, 8M

×

 72 and 2 bank 16M

×

 64, 16M

×

 72 organization

Optimized for byte-write non-parity or ECC applications

JEDEC standard Synchronous DRAMs (SDRAM)

Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification

SDRAM Performance

Programmed Latencies

Single + 3.3 V (

±

 0.3 V ) power supply

Programmable CAS Latency, Burst Length and Wrap Sequence

(Sequential & Interleave)

Auto Refresh (CBR) and Self Refresh

Decoupling capacitors mounted on substrate

All inputs, outputs are  LVTTL compatible

Serial Presence Detect with E

2

PROM

Utilizes 8M

×

 8 SDRAMs in TSOPII-54 packages

4096 refresh cycles every 64 ms

133.35 mm

×

 31.75 mm

×

 4.00 mm card size with gold contact pads

-8

-8B

-10

Units

f

CK

Clock frequency (max.)

100

100

66

MHz

t

AC

Clock access time

6

6

8

ns

Product Speed

CL

t

RCD

t

RP

-8

PC100

2

2

2

-8B

PC100

3

2

3

-10

PC66

2

2

2

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

2

1998-08-01

The HYS 64(72)8200 and HYS 64(72)16220 are industry standard 168-pin 8-byte Dual in-line

Memory Modules (DIMMs) which are organized as 8M

×

 64, 8M

×

 72 in 1 bank  and 16M

×

 64 and

16M

×

 72 in two banks high speed memory arrays designed with 64M Synchronous DRAMs

(SDRAMs) for non-parity and ECC applications. The DIMMs use -8 and -8B speed sort

8M 8 SDRAM devices in TSOP-54 packages to meet the PC100 requirement. Modules which use

-10 parts are suitable for PC66 applications only. Decoupling capacitors are mounted on the PC

board. The PC board design is according to INTEL’s PC SDRAM Rev. 1.0 module specification.

The DIMMs have a serial presence detect, implemented with a serial E

2

PROM using the two pin I

2

C

protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are

available to the end user.

All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm

long footprint, with 1.25“ ( 31.75 mm) height.

Ordering Information

Type

Ordering Code Package

Descriptions

Module

Height

HYS 64V8200GU-8

PC100-222-620 L-DIM-168-30 100 MHz 8M

×

 64  1 bank

SDRAM module

1.25“

HYS 72V8200GU-8

PC100-222-620 L-DIM-168-30 100 MHz 8M

×

 72  1 bank

SDRAM module

1.25“

HYS 64V16220GU-8

PC100-222-620 L-DIM-168-30 100 MHz 16M

×

 64  2 bank

SDRAM module

1.25“

HYS 72V16220GU-8

PC100-222-620 L-DIM-168-30 100 MHz 16M

×

 72  2 bank

SDRAM module

1.25“

HYS 64V8200GU-8B

PC100-323-620 L-DIM-168-30 100 MHz 8M

×

 64  1 bank

SDRAM module

1.25“

HYS 64V16220GU-8B PC100-323-620 L-DIM-168-30 100 MHz 16M

×

 64  2 bank

SDRAM module

1.25“

HYS 64V8200GU-10

PC66-222-920

L-DIM-168-30 66  MHz 8M

×

 64  1 bank

SDRAM module

1.25“

HYS 72V8200GU-10

PC66-222-920

L-DIM-168-30 66  MHz 8M

×

 72  1 bank

SDRAM module

1.25“

HYS 64V16220GU-10 PC66-222-920

L-DIM-168-30 66  MHz 16M

×

 64  2 bank

SDRAM module

1.25“

HYS 72V16220GU-10 PC66-222-920

L-DIM-168-30 66  MHz 16M

×

 72  2 bank

SDRAM module

1.25“

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

3

1998-08-01

Pin Names

A0 - A11

Address Inputs

CLK0 - CLK3

Clock Input

BA0, BA1

Bank Selects

DQMB0 -

DQMB7

Data Mask

DQ0 - DQ63

Data Input/Output

CS0 - CS3

Chip Select

CB0 - CB7

Check Bits (

×

72

organization only)

V

CC

Power (+ 3.3 Volt)

RAS

Row Address Strobe

V

SS

Ground

CAS

Column Address Strobe

SCL

Clock for Presence Detect

WE

Read/Write Input

SDA

Serial Data Out for Presence Detect

CKE0, CKE1

Clock Enable

N.C.

No Connection

Address Format

Part Number

Rows

Columns Bank

Select

Refresh

Period

Interval

8M

×

 64

HYS 64V8200GU

12

9

2

4k

64 ms

15.6

µ

s

8M

×

 72

HYS 72V8200GU

12

9

2

4k

64 ms

15.6

µ

s

16M

×

 64 HYS 64V16220GU

12

9

2

4k

64 ms

15.6

µ

s

16M

×

 72 HYS 72V16220GU

12

9

2

4k

64 ms

15.6

µ

s

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

4

1998-08-01

Note: Pinnames in brackets are for the x72 ECC versions

Pin Configuration

PIN #

Symbol

PIN #

Symbol

PIN #

Symbol

PIN #

Symbol

1

V

SS

43

V

SS

85

V

SS

127

V

SS

2

DQ0

44

DU

86

DQ32

128

CKE0

3

DQ1

45

CS2

87

DQ33

129

CS3

4

DQ2

46

DQMB2

88

DQ34

130

DQMB6

5

DQ3

47

DQMB3

89

DQ35

131

DQMB7

6

V

CC

48

DU

90

V

CC

132

NC

7

DQ4

49

V

CC

91

DQ36

133

V

CC

8

DQ5

50

NC

92

DQ37

134

NC

9

DQ6

51

NC

93

DQ38

135

NC

10

DQ7

52

NC (CB2)

94

DQ39

136

CB6

11

DQ8

53

NC (CB3)

95

DQ40

137

CB7

12

V

SS

54

V

SS

96

V

SS

138

V

SS

13

DQ9

55

DQ16

97

DQ41

139

DQ48

14

DQ10

56

DQ17

98

DQ42

140

DQ49

15

DQ11

57

DQ18

99

DQ43

141

DQ50

16

DQ12

58

DQ19

100

DQ44

142

DQ51

17

DQ13

59

V

CC

101

DQ45

143

V

CC

18

V

CC

60

DQ20

102

V

CC

144

DQ52

19

DQ14

61

NC

103

DQ46

145

NC

20

DQ15

62

DU

104

DQ47

146

DU

21

NC (CB0)

63

CKE1

105

NC (CB4)

147

NC

22

NC (CB1)

64

V

SS

106

NC (CB5)

148

V

SS

23

V

SS

65

DQ21

107

V

SS

149

DQ53

24

NC

66

DQ22

108

NC

150

DQ54

25

NC

67

DQ23

109

NC

151

DQ55

26

V

CC

68

V

SS

110

V

CC

152

V

SS

27

WE

69

DQ24

111

CAS

153

DQ56

28

DQMB0

70

DQ25

112

DQMB4

154

DQ57

29

DQMB1

71

DQ26

113

DQMB5

155

DQ58

30

CS0

72

DQ27

114

CS1

156

DQ59

31

DU

73

V

CC

115

RAS

157

V

CC

32

V

SS

74

DQ28

116

V

SS

158

DQ60

33

A0

75

DQ29

117

A1

159

DQ61

34

A2

76

DQ30

118

A3

160

DQ62

35

A4

77

DQ31

119

A5

161

DQ63

36

A6

78

V

SS

120

A7

162

V

SS

37

A8

79

CLK2

121

A9

163

CLK3

38

A10

80

NC

122

BA0

164

NC

39

BA1

81

WP

123

A11

165

SA0

40

V

CC

82

SDA

124

V

CC

166

SA1

41

V

CC

83

SCL

125

CLK1

167

SA2

42

CLK0

84

V

CC

126

NC

168

V

CC

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

5

1998-08-01

Block Diagram for 8M

×

 64/72 SDRAM DIMM Modules (HYS 64/72V8200GU)

SPB03958

DQ0-DQ7

DQM

WE

D0

CS0

WE

DQ(7:0)

DQMB0

DQ0-DQ7

DQ(39:32)

DQMB4

DQM

D4

DQ0-DQ7

DQ(15:8)

DQMB1

DQM

D1

CS

DQ0-DQ7

DQ(47:40)

DQMB5

DQM

D5

DQ0-DQ7

CB(7:0)

DQM

CS

D8

DQ0-DQ7

DQ0-DQ7

DQ(31:24)

DQMB3

DQ(23:16)

DQMB2

DQM

DQM

CS2

CS

CS

CS

D3

D2

DQMB7

DQ(63:56)

DQMB6

DQ(55:48)

CS

D7

D6

DQ0-DQ7

DQM

DQ0-DQ7

DQM

A0-A11, BA0, BA1

D0-D7, (D8)

CC

V

SS

V

C0-C15, (C16, C17)

D0-D7, (D8)

RAS

D0-D7, (D8)

D0-D7, (D8)

CAS

Clock Wiring

16 M x 64

16 M x 72

CLK0

4 SDRAM + 3.3 pF

5 SDRAM

Termination

Termination

CLK1

4 SDRAM + 3.3 pF

4 SDRAM + 3.3 pF

CLK2

CLK3

47 k

SCL

SCL

2

SA0

SA1

SA2

E PROM (256 word x 8 Bit)

SA1

SA0

SA2

SDA

WP

CS

CS

WE

WE

WE

WE

CS

WE

WE

WE

WE

D0-D7, (D8)

CKE0

D0-D7, (D8)

Termination

Termination

Note: D8 is only used in the x72 ECC version.

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

6

1998-08-01

Block Diagram for 16M

×

 64/72 SDRAM DIMM Modules (HYS 64/72V1620GU)

SPB03769

DQ0-DQ7

DQM

CS

D0

DQ0-DQ7

DQM

D8

CS

CS0

CS1

DQ(7:0)

DQMB0

DQ0-DQ7

DQ(39:32)

DQMB4

DQM

CS

D4

CS

DQ0-DQ7

DQM

D12

DQ0-DQ7

DQ(15:8)

DQMB1

DQM

CS

D1

CS

DQ0-DQ7

DQM

D9

DQ0-DQ7

DQ(47:40)

DQMB5

DQM

CS

CS

D5

DQM

DQ0-DQ7

D13

DQ0-DQ7

CB(7:0)

DQM

CS

CS

D16

DQM

DQ0-DQ7

D17

DQ0-DQ7

DQ0-DQ7

DQ(31:24)

DQMB3

DQ(23:16)

DQMB2

DQM

DQM

CS3

CS2

CS

CS

CS

CS

CS

CS

D3

DQ0-DQ7

DQM

D2

DQM

DQ0-DQ7

DQMB7

DQ(63:56)

D11

DQMB6

DQ(55:48)

D10

CS

D7

D6

DQ0-DQ7

DQM

DQ0-DQ7

DQM

CS

DQ0-DQ7

DQM

D15

DQM

DQ0-DQ7

D14

A0-A11, BA0, BA1

D0-D15, (D16, D17)

DD

V

SS

V

C0-C31, (C32...C35)

D0-D15, (D16, D17)

D0-D7, (D8)

RAS, CAS, WE

D0-D15, (D16, D17)

D0-D7, (D16)

CKE0

D9-D15, (D17)

CKE1

DD

V

10 k

Clock Wiring

16 M x 64

16 M x 72

CLK0

4 SDRAM + 3.3 pF

5 SDRAM

5 SDRAM

4 SDRAM + 3.3 pF

CLK1

4 SDRAM + 3.3 pF

4 SDRAM + 3.3 pF

CLK2

4 SDRAM + 3.3 pF

CLK3

4 SDRAM + 3.3 pF

47 k

SCL

SCL

2

SA0

SA1

SA2

E PROM (256 word x 8 Bit)

SA1

SA0

SA2

SDA

WP

Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10

except otherwise noted.

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

7

1998-08-01

DC Characteristics

T

A

 = 0 to 70

°

C;

V

SS

 = 0 V;

V

DD

,

V

DDQ

 = 3.3 V

±

 0.3 V

Parameter

Symbol

Limit Values

Unit

min.

max.

Input high voltage

V

I

H

2.0

V

CC

+ 0.3

V

Input low voltage

V

I

L

– 0.5

0.8

V

Output high voltage (

I

OUT

 = – 2.0 mA)

V

OH

2.4

V

Output low voltage (

I

OUT

 = 2.0 mA)

V

OL

0.4

V

Input leakage current, any input

(0 V <

 V

I

N

 < 3.6 V, all other inputs = 0 V)

I

I

(L)

– 40

40

µ

A

Output leakage current

(DQ is disabled, 0 V <

V

OUT

<

V

CC

)

I

O(L)

– 40

40

µ

A

Capacitance

T

A

 = 0 to 70

°

C;

V

DD

 = 3.3 V

±

 0.3 V,

f

 = 1 MHz

Parameter

Symbol

Limit Values

Unit

max.

8M

×

64

max.

8M

×

72

max.

16M

×

64

max.

16M

×

72

Input capacitance

(A0 to A11, BA0, BA1, RAS, CAS, WE)

C

I1

45

55

70

80

pF

Input capacitance (CS0 - CS3)

C

I2

25

25

25

30

pF

Input capacitance (CLK0 - CLK3)

C

ICL

35

38

35

38

pF

Input capacitance (CKE0, CKE1)

C

I3

35

38

35

38

pF

Input capacitance (DQMB0 - DQMB7)

C

I4

13

13

20

20

pF

Input/Output capacitance

(DQ0 - DQ63, CB0 - CB7)

C

IO

10

10

15

15

pF

Input Capacitance (SCL, SA0 - 2)

C

SC

8

8

8

8

pF

Input/Output capacitance

C

SD

10

10

10

10

pF

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

8

1998-08-01

Operating Currents

T

A

 = 0 to 70

°

C,

V

DD

 = 3.3 V

±

 0.3 V

1

Recommended Operating Conditions unless otherwise noted

Parameter & Test Condition

Symb.

-8/-8B

-10

Unit

Note

max.

Operating Current

t

RC

=

t

RC(MIN.)

,

t

CK

=

t

CK(MIN.)

Outputs open Burst length = 4, CL = 3

All banks operated in random access,

all banks operated in ping-pong manner to maximize

gapless data access

I

CC1

110

75

mA

1

Precharged Standby Current in

Power Down Mode

CS =

V

IH(MIN.)

, CKE

V

IL(MAX.)

t

CK

=

min.

I

CC2P

2

2

mA

1

t

CK

= infinity

I

CC2PS

1

1

mA

1

Precharged Standby Current in

Non-power Down Mode

CS =

V

IH(MIN.)

, CKE

V

IH(MIN.)

t

CK

=

min.

I

CC2N

35

30

mA

1

t

CK

= infinity

I

CC2NS

5

5

1

No operating current

t

CK

= min., CS =

V

IH(MIN.)

,

active state (max. 4 banks)

CKE

V

IH(MIN.)

I

CC3N

45

40

mA

1

CKE

V

IL(MAX.)

I

CC3P

8

8

mA

1

Burst operating current

t

CK

= min.,

Read command cycling

I

CC4

70

50

mA

1, 2

Auto refresh current

t

CK

= min.,

Auto Refresh command cycling

I

CC5

130

90

mA

1

Self refresh current

Self Refresh Mode, CKE = 0.2 V

standard version

I

CC6

1

1

mA

1

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

9

1998-08-01

AC Characteristics

3, 4

T

A

 = 0 to 70

°

C;

V

SS

 = 0 V;

V

CC

 = 3.3 V

±

 0.3 V,

t

T

 = 1 ns

Parameter

Symbol

Limit Values

Unit

Note

-8

 PC100-222

-8B

PC100-323

-10

PC66

min.

max.

min.

max.

min.

max.

Clock and Clock Enable

Clock Cycle Time

CAS Latency = 3

CAS Latency = 2

t

CK

10

10

10

12

10

15

ns

ns

System Frequency

CAS Latency = 3

CAS Latency = 2

f

CK

100

100

100

83

100

66

MHz

MHz

Clock Access Time

CAS Latency = 3

CAS Latency = 2

t

AC

6

6

6

7

8

9

ns

ns

4, 5

Clock High Pulse Width

t

CH

3

3

3.5

ns

6

Clock Low Pulse Width

t

CL

3

3

3.5

ns

6

Input Setup Time

t

CS

2

2

3

ns

7

Input Hold Time

t

CH

1

1

1

ns

7

CKE Setup Time

(Power down mode)

t

CKSP

2.5

2.5

3

ns

8

CKE Setup Time

(Self Refresh Exit)

t

CKSR

8

10

8

ns

9

Transition Time

(rise and fall)

t

T

1

1

1

ns

Common Parameters

RAS to CAS delay

t

RCD

20

20

30

ns

Precharge Time

t

RP

20

30

30

ns

Active Command Period

t

RAS

50

100k

60

100k

70

100k

ns

Cycle Time

t

RC

70

80

80

ns

Bank to Bank Delay Time

t

RRD

16

20

20

ns

CAS to CAS Delay Time

(same bank)

t

CCD

1

1

1

CLK

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

10

1998-08-01

Refresh Cycle

Refresh Period

(4096 cycles)

t

REF

64

64

64

ms

8

Self Refresh Exit Time

t

SREX

10

10

10

ns

9

Read Cycle

Data Out Hold Time

t

OH

3

3

3

ns

4

Data Out to Low Impedance

t

LZ

0

0

0

ns

Data Out to High Impedance

t

HZ

3

8

3

10

3

10

ns

10

DQM Data Out Disable

Latency

t

DQZ

2

2

2

CLK

Write Cycle

Data input to Precharge

(write recovery)

t

DPL

2

2

2

CLK

Data In to Active/Refresh

t

DAL

5

5

5

CLK

DQM Write Mask Latency

t

DQW

0

0

0

CLK

AC Characteristics  (cont’d)

3, 4

T

A

 = 0 to 70

°

C;

V

SS

 = 0 V;

V

CC

 = 3.3 V

±

 0.3 V,

t

T

 = 1 ns

Parameter

Symbol

Limit Values

Unit

Note

-8

 PC100-222

-8B

PC100-323

-10

PC66

min.

max.

min.

max.

min.

max.

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

11

1998-08-01

Notes

1. The specified values are valid when addresses are changed no more than once during

t

CK(MIN.)

and when No Operation commands are registered on every rising clock edge during

t

RC(MIN.)

.

Values are shown per module bank.

2. The specified values are valid when data inputs (DQ’s) are stable during

t

RC(MIN.)

.

3. All AC characteristics are shown for device level.

An initial pause of 100

µ

s is required after power-up, then a Precharge All Banks command must

be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can

begin.

4. AC timing tests have

V

IL

 = 0.4 V and

V

IH

 = 2.4 V with the timing referenced to the 1.4 V crossover

point. The transition time is measured between

V

IH

 and

V

IL

. All AC measurements assume

t

T

= 1 ns with the AC output load circuit show. Specified

t

AC

 and

t

OH

 parameters are measured

with a 50 pF only, without any resistive termination and with a input signal of 1V/ns edge rate

between 0.8 V and 2.0 V.

.

5. If clock rising time is longer than 1ns, a time (

t

T

/2 – 0.5) ns has to be added to this parameter.

6. Rated at 1.5 V

7. If

t

T

 is longen than 1 ns, a time (

t

T

 – 1) ns has to be added to this parameter.

8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh

commands must be given to “wake-up“ the device.

9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after

CKE returns high. Self Refresh Exit is not complete until a time period equal to

t

RC

 is satisfied

once the Self Refresh Exit command is registered.

10.Referenced to the time which the output achieves the open circuit condition, not to output voltage

levels.

SPT03404

CLOCK

2.4 V

0.4 V

INPUT

HOLD

t

SETUP

t

t

T

OUTPUT

1.4 V

t

LZ

AC

t

t

AC

OH

t

HZ

t

1.4 V

CL

t

CH

t

50 pF

I/O

Measurement conditions for

t

AC

 and

t

OH

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

12

1998-08-01

A serial presence detect storage device - E

2

PROM  - is assembled onto the module. Information

about the module configuration, speed, etc. is written into the E

2

PROM device during module

production using a serial presence detect protocol (I

2

C synchronous 2-wire bus).

SPD-Table for PC100 Modules

Byte# Description

SPD

Entry

Value

Hex

8M

×

64

-8

8M

×

64

-8B

8M

×

72

-8

16M

×

64

-8

16M

×

64

-8B

16M

×

72

-8

0

Number of SPD

bytes

128

80

80

80

80

80

80

1

Total bytes in Serial

PD

256

08

08

08

08

08

08

2

Memory Type

SDRAM

04

04

04

04

04

04

3

Number of Row

Addresses

(without BS bits)

12

0C

0C

0C

0C

0C

0C

4

Number of Column

Addresses

(for 8M

×

 8

SDRAMs)

9

09

09

09

09

09

09

5

Number of DIMM

Banks

1/2

01

01

01

02

02

02

6

Module Data Width

64/72

40

40

48

40

40

48

7

Module Data Width

(cont’d)

0

00

00

00

00

00

00

8

Module Interface

Levels

LVTTL

01

01

01

01

01

01

9

SDRAM Cycle Time

at CL= 3

10.0 ns

A0

A0

A0

A0

A0

A0

10

SDRAM Access

time from Clock at

CL = 3

6.0 ns

60

60

60

60

60

60

11

Dimm Config

(Error Det/Corr.)

none/ECC

00

00

02

00

00

02

12

Refresh Rate/Type

Self

Refresh15.

6

µ

s

80

80

80

80

80

80

13

SDRAM width,

Primary

×

 

8

08

08

08

08

08

08

14

Error Checking

SDRAM data width

n/a /

×

 

8

00

00

08

00

00

08

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

13

1998-08-01

15

Minimum clock

delay for back-to-

back random

column address

t

CCD

 = 1

CLK

01

01

01

01

01

01

16

Burst Length

supported

1, 2, 4, 8 &

full page

8F

8F

8F

8F

8F

8F

17

Number of SDRAM

banks

4

04

04

04

04

04

04

18

Supported CAS

Latencies

CAS

latency =

2 & 3

06

06

06

06

06

06

19

CS Latencies

CS

latency = 0

01

01

01

01

01

01

20

WE Latencies

Write

latency = 0

01

01

01

01

01

01

21

SDRAM DIMM

module attributes

non

buffered/

non reg.

00

00

00

00

00

00

22

SDRAM Device

Attributes: General

V

CC

 tol

±

10%

06

06

06

06

06

06

23

Min. Clock Cycle

Time at CAS

Latency = 2

10.0/12.0

ns

A0

C0

A0

A0

C0

A0

24

Max. data access

time from Clock for

CL = 2

6.0/7.0 ns

60

70

60

60

60

60

25

Minimum Clock

Cycle Time at

CL = 1

not

supported

FF

FF

FF

FF

FF

FF

26

Maximum Data

Access Time from

Clock at CL = 1

not

supported

FF

FF

FF

FF

FF

FF

27

Minimum Row

Precharge Time

20/30 ns

14

1E

14

14

1E

14

28

Minimum Row

Active to Row

Active delay

t

RRD

16/20  ns

10

14

10

10

14

10

SPD-Table for PC100 Modules  (cont’d)

Byte# Description

SPD

Entry

Value

Hex

8M

×

64

-8

8M

×

64

-8B

8M

×

72

-8

16M

×

64

-8

16M

×

64

-8B

16M

×

72

-8

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

14

1998-08-01

29

Minimum RAS to

CAS delay

t

RCD

20  ns

14

14

14

14

14

14

30

Minimum RAS

pulse width

t

RAS

45  ns

2D

2D

2D

2D

2D

2D

31

Module Bank

Density (per bank)

64 MByte

10

10

10

10

10

10

32

SDRAM  input setup

time

2 ns

20

20

20

20

20

20

33

SDRAM input hold

time

1 ns

10

10

10

10

10

10

34

SDRAM data input

hold time

2 ns

20

20

20

20

20

20

35

SDRAM data input

setup time

1 ns

10

10

10

10

10

10

62-61

Superset

information (may

be used in future)

FF

FF

FF

FF

FF

FF

62

SPD Revision

Revision

1.2

12

12

12

12

12

12

63

Checksum for

bytes 0 - 62

D8

16

EA

D9

17

EB

64-

125

Manufacturers

information

(optional)

(FF

H

 if not used)

XX

XX

XX

XX

XX

XX

126

Frequency

Specification

100 MHz

64

64

64

64

64

64

127

100 MHz support

details

AF

AD

AF

FF

FD

FF

128+

Unused storage

locations

FF

FF

FF

FF

FF

FF

SPD-Table for PC100 Modules  (cont’d)

Byte# Description

SPD

Entry

Value

Hex

8M

×

64

-8

8M

×

64

-8B

8M

×

72

-8

16M

×

64

-8

16M

×

64

-8B

16M

×

72

-8

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

15

1998-08-01

SPD-Table for PC66 Modules

Byte# Description

SPD Entry Value

Hex

8M

×

64

-10

8M

×

72

-10

16M

×

64

-10

16M

×

72

-10

0

Number of SPD bytes

128

80

80

80

80

1

Total bytes in Serial PD

256

08

08

08

08

2

Memory Type

SDRAM

04

04

04

04

3

Number of Row Addresses

(without BS bits)

12

0C

0C

0C

0C

4

Number of Column

Addresses

(for x8 SDRAM)

9

09

09

09

09

5

Number of DIMM Banks

1/2

01

01

02

02

6

Module Data Width

64/72

40

48

40

48

7

Module Data Width (cont’d)

0

00

00

00

00

8

Module Interface Levels

LVTTL

01

01

01

01

9

SDRAM Cycle Time at

CL = 3

10.0 ns

A0

A0

A0

A0

10

SDRAM Access time from

Clock at C L= 3

8.0 ns

80

80

80

80

11

Dimm Config

(Error Det/Corr.)

none/ECC

00

02

00

02

12

Refresh Rate/Type

Self Refresh

15.6

µ

s

80

80

80

80

13

SDRAM width, Primary

×

8

08

08

08

08

14

Error Checking SDRAM

data width

n/a/

×

8

00

08

00

08

15

Minimum clock delay for

back-to-back random

column address

t

CCD

 = 1 CLK

01

01

01

01

16

Burst Length supported

1, 2, 4, 8 & full page

8F

8F

8F

8F

17

Number of SDRAM banks

4

04

04

04

04

18

Supported CAS Latencies

CAS latency = 2 & 3

06

06

06

06

19

CS Latencies

CS latency = 0

01

01

01

01

20

WE Latencies

Write latency = 0

01

01

01

01

21

SDRAM DIMM module

attributes

non buffered/

non reg.

00

00

00

00

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

16

1998-08-01

Byte# Description

SPD Entry Value

Hex

8M

×

64

-10

8M

×

72

-10

16M

×

64

-10

16M

×

72

-10

22

SDRAM Device Attributes:

General

V

CC

 tol

±

 10%

06

06

06

06

23

Min. Clock Cycle Time at

CAS Latency = 2

15.0 ns

F0

F0

F0

F0

24

Max. data access time from

Clock for CL= 2

9.0 ns

90

90

90

90

25

Minimum Clock Cycle Time

at CL = 1

not supported

FF

FF

FF

FF

26

Maximum Data Access

Time from Clock at CL = 1

not supported

FF

FF

FF

FF

27

Minimum Row Precharge

Time

30 ns

1E

1E

1E

1E

28

Minimum Row Active to

Row Active delay

t

RRD

20  ns

14

14

14

14

29

Minimum RAS to CAS delay

t

RCD

30  ns

1E

1E

1E

1E

30

Minimum RAS pulse width

t

RAS

45  ns

2D

2D

2D

2D

31

Module Bank Density (per

bank)

64 MByte

10

10

10

10

32

SDRAM  input setup time

3 ns

30

30

30

30

33

SDRAM input hold time

1 ns

10

10

10

10

34

SDRAM data input hold time 3 ns

30

30

30

30

35

SDRAM data input setup

time

1 ns

10

10

10

10

62-61

Superset information

(may be used in future)

FF

FF

FF

FF

62

SPD Revision

Revision 1.2

12

12

12

12

63

Checksum for bytes 0 - 62

B0

C2

B1

C3

64-

125

Manufacturers information

(optional)

(FF

H

 if not used)

XX

XX

XX

XX

126

Frequency Specification

66 MHz

66

66

66

66

127

Details

AF

AF

FF

FF

128+

Unused storage locations

FF

FF

FF

FF

SPD-Table for PC66 Modules  (cont’d)

background image

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

Semiconductor Group

17

1998-08-01

Package Outlines

L-DIM-168-30

SDRAM DIMM Module Package

GLD09159

133.35

10

11

3

6.35

6.35

41

40

42.18

84

127.35

3

1.27

0.1

±

85

94

95

124

125

168

2

17.78

±

0.1

4

3 min.

4

31.75

Detail of Contacts

min.

2.54

1

0.05

±

1.27

1

1.27

91 x 1.27 = 115.57

3.125

0.2

±

0.15

4.45

2.26

8.25

+0.1

R1.27

*) on ECC modules only

*)

*)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

SMD = Surface Mounted Device