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Semiconductor Group                                         1                                                                     4.96

4M x 1-Bit Dynamic RAM

Low Power 4M x 1-Bit Dynamic RAM

Advanced Information

4 194 304 words by 1-bit organization

0 to 70 ˚C operating temperature

Fast Page Mode Operation

Performance:

Single + 3.3 V (

±

0.3 V ) supply with a built-in

V

bb

 generator

Low power dissipation

max. 252 mW active (-50 version)

max. 216 mW active (-60 version)

max. 198 mW active (-70 version)

Standby power dissipation:

7.2 mW  max. standby (TTL)

3.6 mW max. standby (CMOS)

720

µ

W max. standby (CMOS) for Low Power Version

Output unlatched at cycle end allows two-dimensional chip selection

Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh,

hidden refresh and test mode capability

All inputs and outputs TTL-compatible

1024 refresh cycles / 16 ms

1024 refresh cycles / 128 ms Low Power Version

Plastic Packages: P-SOJ-26/20-5  with 300 mil width

-50

-60

-70

t

RAC

RAS access time

50

60

70

ns

t

CAC

CAS access time

13

15

20

ns

t

AA

Access time from address

25

30

35

ns

t

RC

Read/Write cycle time

95

110

130

ns

t

PC

Fast page mode cycle time

35

40

45

ns

HYB 314100BJ/BJL -50/-60/-70

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Semiconductor Group

2

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

The HYB 314100BJ/BJL is the new generation dynamic RAM organized as 4 194 304 words by

1-bit. The HYB 314100BJ/BJL utilizes CMOS silicon gate process as well as advances circuit

techniques to provide wide operation margins, both internally and for the system user. Multiplexed

address inputs permit the HYB 514100BJ/BJL to be packed in a standard plastic P-SOJ-26/20

package. This package size provides high system bit densities and is compatible with commonly

used automatic testing and insertion equipment. System oriented features include single + 3.3 V

(

±

0.3 V) power supply, direct interfacing with high performance logic device families.

Ordering Information

Type

Ordering Code

Package

Descriptions

HYB 314100BJ-50

Q67100-Q2035

P-SOJ-26/20-5

3.3 V DRAM

(access time 50 ns)

HYB 314100BJ-60

Q67100-Q2037

P-SOJ-26/20-5

3.3 V DRAM

(access time 60 ns)

HYB 314100BJ-70

Q67100-Q2039

P-SOJ-26/20-5

3.3 V DRAM

(access time 70 ns)

HYB 314100BJL-50

on request

P-SOJ-26/20-5

3.3 V Low Power DRAM

(access time 50 ns)

HYB 314100BJL-60

on request

P-SOJ-26/20-5

3.3 V Low Power DRAM

(access time 60 ns)

HYB 314100BJL-70

on request

P-SOJ-26/20-5

3.3 V Low Power DRAM

(access time 70 ns)

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Pin Configuration

(top view)

Pin Names

A0-A10

Address Input

RAS

Row Address Strobe

CAS

Column Address Strobe

WE

Read/Write Input

DI

Data In

DO

Data Out

V

CC

Power Supply (+ 3.3 V)

V

SS

Ground (0 V)

N.C.

No Connection

P-SOJ-26/20-5

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Semiconductor Group

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Block Diagram

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Absolute Maximum Ratings

Operating temperature range ............................................................................................0 to 70 ˚C

Storage temperature range......................................................................................– 55 to + 150 ˚C

Input/output voltage ........................................................................... – 1 to + min (

V

CC

 + 0.5, 4.6) V

Power Supply voltage .................................................................................................. – 1 to + 4.6 V

Data out current (short circuit) ................................................................................................ 50 mA

Note:

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent

damage of the device. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

DC Characteristics

T

A

 = 0 to 70 ˚C,

V

SS

 = 0 V,

V

CC

 = 3.3 V

±

 0.3 V ,

t

T

 = 5 ns

Parameter

Symbol

Limit Values

Unit Test

Condition

min.

max.

Input high voltage

V

IH

2.0

V

CC

 + 0.5 V

1)

Input low voltage

V

IL

– 1.0

0.8

V

1)

TTL Output high voltage (

I

OUT

 = – 2 mA)

V

OH

2.4

V

1)

TTL Output low voltage (

I

OUT

 = 2 mA)

V

OL

0.4

V

1)

CMOS Output high voltage (

I

OUT

 = – 100

µ

A)

V

OH

V

CC

 – 0.2 –

V

CMOS Output low voltage (

I

OUT  =

100

µ

A

)

V

OL

0.2

V

Input leakage current, any input

(0 V  <

 V

in

 <

V

CC

 + 0.3 V, all other input = 0 V)

I

I(L)

– 10

10

µ

A

1)

Output leakage current

(DO is disabled, 0 V <

 V

OUT

 <

V

CC

)

I

O(L)

– 10

10

µ

A

1)

Average

V

CC

 supply current

-50 version

-60 version

-70 version

I

CC1

_

70

60

55

mA

2) 3)4)

Standby

V

CC

 supply current

(RAS = CAS = WE =

V

IH

)

I

CC2

2

mA

Average

V

CC

 supply current during RAS-only

refresh cycles

-50 version

-60 version

-70 version

I

CC3

_

70

60

55

mA

2)4)

Average

V

CC

 supply current during fast page

mode operation

-50 version

-60 version

-70 version

I

CC4

50

45

40

mA

2) 3)4)

Standby

V

CC

 supply current

(RAS = CAS = WE =

V

CC

 – 0.2 V)

I

CC5

1

200

mA

µ

A

1)

L-version

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Average

V

CC

 supply current during

CAS before RAS refresh mode

-50 version

-60 version

-70 version

I

CC6

70

60

55

mA

2)4)

For Low Power Version only:

Battery backup current (average power supply

current in battery backup mode):

(CAS = CAS before RAS cycling or 0.2 V,

WE =

V

CC

 – 0.2 V or 0.2 V,

A0 to A10 =

V

CC

 – 0.2 V or 0.2 V;

D

I

 =

V

CC

 – 0.2 V or 0.2 V or open,

t

RC

 = 125

µ

s,

t

RAS

 =

t

RAS

 min = 1

µ

s)

I

CC7

250

µ

A

Capacitance

T

A

 = 0 to 70 ˚C;

V

CC

 = 3.3 V

±

 0.3 V;

f

  = 1 MHz

Parameter

Symbol

Limit Values

Unit

min.

max.

Input capacitance (A0 to A10, DI)

C

I1

5

pF

Input capacitance (RAS, CAS, WE)

C

I2

7

pF

Output capacitance (DO)

C

IO

7

pF

DC Characteristics  (cont’d)

T

A

 = 0 to 70 ˚C,

V

SS

 = 0 V,

V

CC

 = 3.3 V

±

 0.3 V ,

t

T

 = 5 ns

Parameter

Symbol

Limit Values

Unit Test

Condition

min.

max.

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

AC Characteristics

   5)6)

T

A

 = 0 to 70 ˚C,

V

CC

 = 3.3 V

±

 0.3 V,

t

T

 = 5 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

-70

min.

max. min.

max. min.

max.

Common Parameters

Random read or write cycle time

t

RC

95

110

130

ns

RAS precharge time

t

RP

35

40

50

ns

RAS pulse width

t

RAS

50

10k

60

10k

70

10k

ns

CAS pulse width

t

CAS

13

10k

15

10k

20

10k

ns

Row address setup time

t

ASR

0

0

0

ns

Row address hold time

t

RAH

8

10

10

ns

Column address setup time

t

ASC

0

0

0

ns

Column address hold time

t

CAH

10

15

15

ns

RAS to CAS delay time

t

RCD

18

37

20

45

20

50

ns

RAS to column address delay

time

t

RAD

13

25

15

30

15

35

ns

RAS hold time

t

RSH

13

15

20

ns

CAS hold time

t

CSH

50

60

70

ns

CAS to RAS precharge time

t

CRP

5

5

5

ns

Transition time (rise and fall)

t

T

3

50

3

50

3

50

ns

7

Refresh period

t

REF

16

16

16

ms

Refresh period for L-version

t

REF

128

128

128

ms

Read Cycle

Access time from RAS

t

RAC

50

60

70

ns

8, 9

Access time from CAS

t

CAC

13

15

20

ns

8, 9

Access time from column

address

t

AA

25

30

35

ns

8,10

Column addr. to RAS lead time

t

RAL

25

30

35

ns

Read command setup time

t

RCS

0

0

0

ns

Read command hold time

t

RCH

0

0

0

ns

11

Read command hold time

referenced to RAS

t

RRH

0

0

0

ns

11

CAS to output in low-Z

t

CLZ

0

0

0

ns

8

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Output buffer turn-off delay

t

OFF

0

13

0

15

0

20

ns

12

Write Cycle

Write command hold time

t

WCH

8

10

10

ns

Write command pulse width

t

WP

8

10

10

ns

Write command setup time

t

WCS

0

0

0

ns

13

Write command to RAS lead time

t

RWL

13

15

20

ns

Write command to CAS lead time

t

CWL

13

15

20

ns

Data setup time

t

DS

0

0

0

ns

14

Data hold time

t

DH

10

10

15

ns

14

Read-Modify-Write Cycle

Read-write cycle time

t

RWC

115

130

155

ns

RAS to WE delay time

t

RWD

50

60

70

ns

13

CAS to WE delay time

t

CWD

13

15

20

ns

13

Column address to WE delay

time

t

AWD

25

30

35

ns

13

Fast Page Mode Cycle

Fast page mode cycle time

t

PC

35

40

45

ns

CAS precharge time

t

CP

10

10

10

ns

Access time from CAS

precharge

t

CPA

30

35

40

ns

7

RAS pulse width

t

RAS

50

200 k 60

200 k 70

200 k ns

CAS precharge to RAS Delay

t

RHCP

30

35

40

ns

AC Characteristics  (cont’d)

   5)6)

T

A

 = 0 to 70 ˚C,

V

CC

 = 3.3 V

±

 0.3 V,

t

T

 = 5 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

-70

min.

max. min.

max. min.

max.

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Fast Page Mode Read-Modify-Write Cycle

Fast page mode read-write cycle

time

t

PRWC

55

60

70

ns

CAS precharge to WE

t

CPWD

30

35

40

ns

CAS-before-RAS refresh cycle

CAS setup time

t

CSR

10

10

10

ns

CAS hold time

t

CHR

10

10

10

ns

RAS to CAS precharge time

t

RPC

5

5

5

ns

Write to RAS precharge time

t

WRP

10

10

10

ns

Write hold time referenced to

RAS

t

WRH

10

10

10

ns

CAS-before-RAS counter test

cycle

CAS precharge time

t

CPT

35

40

40

ns

Test Mode

Write command setup time

t

WTS

10

10

10

ns

Write command hold time

t

WTH

10

10

10

ns

AC Characteristics  (cont’d)

   5)6)

T

A

 = 0 to 70 ˚C,

V

CC

 = 3.3 V

±

 0.3 V,

t

T

 = 5 ns

Parameter

Symbol

Limit Values

Unit

Note

-50

-60

-70

min.

max. min.

max. min.

max.

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Notes:

1) All voltages are referenced to

V

SS

.

2)

I

CC1

,

I

CC3

,

I

CC4

 and

I

CC6

 depend on cycle rate.

3)

I

CC1

 and

I

CC4

 depend on output loading. Specified values are measured with the output open.

4) Address can be changed once or less while RAS =

V

IL

. In the case of

I

CC4

 it can be changed once or less during

a fast page mode cycle (

t

PC

).

5) An initial pause of 200

µ

s is required after power-up followed by 8 RAS cycles of which at least one cycle has

to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a

minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.

6) AC measurements assume

t

T

 = 5 ns.

7)

V

IH (min.)

 and

V

IL (max.)

 are reference levels for measuring timing of input signals. Transition times are also

measured between

V

IH

 and

V

IL

.

8) Measured with the specified current load and 100 pF at

V

OL

 = 0.8 and

V

OH

 = 2.0 V.

9) Operation within the

t

RCD (max.)

 limit ensures that

t

RAC (max.)

 can be met.

t

RCD (max.)

 is specified as a reference point

only: If

t

RCD

 is greater than the specified

t

RCD (max.)

 limit, then access time is controlled by

t

CAC

.

10)Operation within the

t

RAD (max.)

 limit ensures that

t

RAC (max.)

 can be met.

t

RAD (max.)

 is specified as a reference point

only: If

t

RAD

 is greater than the specified

t

RAD (max.)

 limit, then access time is controlled by

t

AA

.

11)Either

t

RCH

 or

t

RRH

 must be satisfied for a read cycle.

12)

t

OFF (max.)

 defines the time at which the outputs achieve the open-circuit condition and are not referenced to

output voltage levels.

13)

t

WCS

,

t

RWD

,

t

CWD

,

t

AWD

 and

t

CPWD

 are not restrictive operating parameters. They are included in the data sheet as

electrical characteristics only. If

t

WCS

 >

t

WCS (min.)

, the cycle is an early write cycle and the data out pin will remain

open-circuit (high impedance) through the entire cycle; if

t

RWD

 >

t

RWD (min.)

,

t

CWD

 >

t

CWD (min.)

,

t

AWD

 >

t

AWD (min.)

 and

t

CPWD

 >

t

CPWD (min.)

, the cycle is a read-write cycle and DO will contain data read from the selected cells. If neither

of the above sets of conditions is satisfied, the condition of the DO pin (at access time) is indeterminate.

14)These parameters are referenced to the CAS leading edge in early write cycles and to the WE  leading edge

in read-write cycles.

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Semiconductor Group

11

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Read Cycle

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Semiconductor Group

12

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Write Cycle (Early Write)

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Semiconductor Group

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Read-Write (Read-Modify-Write) Cycle

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Semiconductor Group

14

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Fast Page Mode Read-Modify-Write Cycle

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Semiconductor Group

15

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Fast Page Mode Read Cycle

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Semiconductor Group

16

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Fast Page Mode Early Write Cycle

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17

HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

RAS-Only Refresh Cycle

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

CAS-Before-RAS Refresh Cycle

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Hidden Refresh Cycle (Read)

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Hidden Refresh Cycle (Early Write)

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

CAS-Before-RAS Refresh Counter Test Cycle

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Test Mode Entry

Test Mode

The HYB314100BJ/BJL  is organized 4 194 304 words by 1- bit but can internally be configured as

524 288  words by 8-bits. A WE, CAS-before-RAS cycle puts the device into Test Mode.

In Test Mode, data is written into 8 sectors in parallel and retrieved the same way. If, upon reading,

all bits are equal, the data output pin indicates a “1”. If any of the bits differ, the data output pin

indicates a “0”. In Test Mode the 4M DRAM can be tested as if it were a 512K DRAM. Test Mode

is exited by any refresh operation which is not a WE, CAS- before-RAS cycle. Addresses A10R,

A10C and A0C do not care during Test Mode.

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HYB 314100BJ/BJL-50/-60/-70

3.3V 4M x 1 DRAM

Package Outlines

Plastic Package P-SOJ-26/20-5

(Plastic Small Outline J-leaded Package)

GPJ05627

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

SMD = Surface Mounted Device